2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
42 #include <sys/sysctl.h>
44 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pcivar.h>
50 #include <x86/apicreg.h>
51 #include <machine/frame.h>
52 #include <machine/intr_machdep.h>
53 #include <x86/apicvar.h>
54 #include <machine/resource.h>
55 #include <machine/segments.h>
56 #include <x86/iommu/iommu_intrmap.h>
58 #define IOAPIC_ISA_INTS 16
59 #define IOAPIC_MEM_REGION 32
60 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
61 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
63 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
66 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
67 * as laid out in the ACPI System Interrupt number model where each I/O
68 * APIC has a contiguous chunk of the System Interrupt address space.
69 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
70 * IRQs behave as PCI IRQs by default. We also assume that the pin for
71 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the
72 * configuration of individual pins as indicated by their tables.
74 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
75 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
76 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
79 struct ioapic_intsrc {
80 struct intsrc io_intsrc;
86 u_int io_edgetrigger:1;
90 u_int io_remap_cookie;
95 u_int io_id:8; /* logical ID */
97 u_int io_intbase:8; /* System Interrupt base */
100 volatile ioapic_t *io_addr; /* XXX: should use bus_space */
102 STAILQ_ENTRY(ioapic) io_next;
103 device_t pci_dev; /* matched pci device, if found */
104 struct resource *pci_wnd; /* BAR 0, should be same or alias to
106 struct ioapic_intsrc io_pins[0];
109 static u_int ioapic_read(volatile ioapic_t *apic, int reg);
110 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
111 static const char *ioapic_bus_string(int bus_type);
112 static void ioapic_print_irq(struct ioapic_intsrc *intpin);
113 static void ioapic_enable_source(struct intsrc *isrc);
114 static void ioapic_disable_source(struct intsrc *isrc, int eoi);
115 static void ioapic_eoi_source(struct intsrc *isrc);
116 static void ioapic_enable_intr(struct intsrc *isrc);
117 static void ioapic_disable_intr(struct intsrc *isrc);
118 static int ioapic_vector(struct intsrc *isrc);
119 static int ioapic_source_pending(struct intsrc *isrc);
120 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
121 enum intr_polarity pol);
122 static void ioapic_resume(struct pic *pic, bool suspend_cancelled);
123 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id);
124 static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
125 static void ioapic_reprogram_intpin(struct intsrc *isrc);
127 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
128 struct pic ioapic_template = {
129 .pic_enable_source = ioapic_enable_source,
130 .pic_disable_source = ioapic_disable_source,
131 .pic_eoi_source = ioapic_eoi_source,
132 .pic_enable_intr = ioapic_enable_intr,
133 .pic_disable_intr = ioapic_disable_intr,
134 .pic_vector = ioapic_vector,
135 .pic_source_pending = ioapic_source_pending,
137 .pic_resume = ioapic_resume,
138 .pic_config_intr = ioapic_config_intr,
139 .pic_assign_cpu = ioapic_assign_cpu,
140 .pic_reprogram_pin = ioapic_reprogram_intpin,
143 static int next_ioapic_base;
144 static u_int next_id;
146 static int enable_extint;
147 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0,
148 "Enable the ExtINT pin in the first I/O APIC");
151 _ioapic_eoi_source(struct intsrc *isrc, int locked)
153 struct ioapic_intsrc *src;
155 volatile uint32_t *apic_eoi;
159 if (!lapic_eoi_suppression)
161 src = (struct ioapic_intsrc *)isrc;
162 if (src->io_edgetrigger)
164 io = (struct ioapic *)isrc->is_pic;
167 * Handle targeted EOI for level-triggered pins, if broadcast
168 * EOI suppression is supported by LAPICs.
172 * If IOAPIC has EOI Register, simply write vector
173 * number into the reg.
175 apic_eoi = (volatile uint32_t *)((volatile char *)
176 io->io_addr + IOAPIC_EOIR);
177 *apic_eoi = src->io_vector;
180 * Otherwise, if IO-APIC is too old to provide EOIR,
181 * do what Intel did for the Linux kernel. Temporary
182 * switch the pin to edge-trigger and back, masking
183 * the pin during the trick.
186 mtx_lock_spin(&icu_lock);
187 low1 = src->io_lowreg;
188 low1 &= ~IOART_TRGRLVL;
189 low1 |= IOART_TRGREDG | IOART_INTMSET;
190 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
192 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
195 mtx_unlock_spin(&icu_lock);
200 ioapic_read(volatile ioapic_t *apic, int reg)
203 mtx_assert(&icu_lock, MA_OWNED);
204 apic->ioregsel = reg;
205 return (apic->iowin);
209 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
212 mtx_assert(&icu_lock, MA_OWNED);
213 apic->ioregsel = reg;
218 ioapic_bus_string(int bus_type)
234 ioapic_print_irq(struct ioapic_intsrc *intpin)
237 switch (intpin->io_irq) {
251 printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
257 ioapic_enable_source(struct intsrc *isrc)
259 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
260 struct ioapic *io = (struct ioapic *)isrc->is_pic;
263 mtx_lock_spin(&icu_lock);
264 if (intpin->io_masked) {
265 flags = intpin->io_lowreg & ~IOART_INTMASK;
266 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
268 intpin->io_masked = 0;
270 mtx_unlock_spin(&icu_lock);
274 ioapic_disable_source(struct intsrc *isrc, int eoi)
276 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
277 struct ioapic *io = (struct ioapic *)isrc->is_pic;
280 mtx_lock_spin(&icu_lock);
281 if (!intpin->io_masked && !intpin->io_edgetrigger) {
282 flags = intpin->io_lowreg | IOART_INTMSET;
283 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
285 intpin->io_masked = 1;
289 _ioapic_eoi_source(isrc, 1);
291 mtx_unlock_spin(&icu_lock);
295 ioapic_eoi_source(struct intsrc *isrc)
298 _ioapic_eoi_source(isrc, 0);
302 * Completely program an intpin based on the data in its interrupt source
306 ioapic_program_intpin(struct ioapic_intsrc *intpin)
308 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
309 uint32_t low, high, value;
315 * If a pin is completely invalid or if it is valid but hasn't
316 * been enabled yet, just ensure that the pin is masked.
318 mtx_assert(&icu_lock, MA_OWNED);
319 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS &&
320 intpin->io_vector == 0)) {
321 low = ioapic_read(io->io_addr,
322 IOAPIC_REDTBL_LO(intpin->io_intpin));
323 if ((low & IOART_INTMASK) == IOART_INTMCLR)
324 ioapic_write(io->io_addr,
325 IOAPIC_REDTBL_LO(intpin->io_intpin),
326 low | IOART_INTMSET);
328 mtx_unlock_spin(&icu_lock);
329 iommu_unmap_ioapic_intr(io->io_apic_id,
330 &intpin->io_remap_cookie);
331 mtx_lock_spin(&icu_lock);
337 mtx_unlock_spin(&icu_lock);
338 error = iommu_map_ioapic_intr(io->io_apic_id,
339 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
340 intpin->io_activehi, intpin->io_irq, &intpin->io_remap_cookie,
342 mtx_lock_spin(&icu_lock);
344 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin),
346 intpin->io_lowreg = low;
347 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
350 } else if (error != EOPNOTSUPP) {
355 /* Set the destination. */
357 high = intpin->io_cpu << APIC_ID_SHIFT;
359 /* Program the rest of the low word. */
360 if (intpin->io_edgetrigger)
361 low |= IOART_TRGREDG;
363 low |= IOART_TRGRLVL;
364 if (intpin->io_activehi)
368 if (intpin->io_masked)
369 low |= IOART_INTMSET;
370 switch (intpin->io_irq) {
372 KASSERT(intpin->io_edgetrigger,
373 ("ExtINT not edge triggered"));
374 low |= IOART_DELEXINT;
377 KASSERT(intpin->io_edgetrigger,
378 ("NMI not edge triggered"));
382 KASSERT(intpin->io_edgetrigger,
383 ("SMI not edge triggered"));
387 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
389 low |= IOART_DELFIXED | intpin->io_vector;
392 /* Write the values to the APIC. */
393 value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
394 value &= ~IOART_DEST;
396 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
397 intpin->io_lowreg = low;
398 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
402 ioapic_reprogram_intpin(struct intsrc *isrc)
405 mtx_lock_spin(&icu_lock);
406 ioapic_program_intpin((struct ioapic_intsrc *)isrc);
407 mtx_unlock_spin(&icu_lock);
411 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id)
413 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
414 struct ioapic *io = (struct ioapic *)isrc->is_pic;
415 u_int old_vector, new_vector;
420 * - Stick to the first cpu for all I/O APIC pins.
421 * - And don't allow destination cpu changes.
423 if (vm_guest == VM_GUEST_HV) {
424 if (intpin->io_vector)
431 * keep 1st core as the destination for NMI
433 if (intpin->io_irq == IRQ_NMI)
437 * Set us up to free the old irq.
439 old_vector = intpin->io_vector;
440 old_id = intpin->io_cpu;
441 if (old_vector && apic_id == old_id)
445 * Allocate an APIC vector for this interrupt pin. Once
446 * we have a vector we program the interrupt pin.
448 new_vector = apic_alloc_vector(apic_id, intpin->io_irq);
453 * Mask the old intpin if it is enabled while it is migrated.
455 * At least some level-triggered interrupts seem to need the
456 * extra DELAY() to avoid being stuck in a non-EOI'd state.
458 mtx_lock_spin(&icu_lock);
459 if (!intpin->io_masked && !intpin->io_edgetrigger) {
460 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
461 intpin->io_lowreg | IOART_INTMSET);
462 mtx_unlock_spin(&icu_lock);
464 mtx_lock_spin(&icu_lock);
467 intpin->io_cpu = apic_id;
468 intpin->io_vector = new_vector;
469 if (isrc->is_handlers > 0)
470 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
472 printf("ioapic%u: routing intpin %u (", io->io_id,
474 ioapic_print_irq(intpin);
475 printf(") to lapic %u vector %u\n", intpin->io_cpu,
478 ioapic_program_intpin(intpin);
479 mtx_unlock_spin(&icu_lock);
482 * Free the old vector after the new one is established. This is done
483 * to prevent races where we could miss an interrupt.
486 if (isrc->is_handlers > 0)
487 apic_disable_vector(old_id, old_vector);
488 apic_free_vector(old_id, old_vector, intpin->io_irq);
494 ioapic_enable_intr(struct intsrc *isrc)
496 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
498 if (intpin->io_vector == 0)
499 if (ioapic_assign_cpu(isrc, intr_next_cpu()) != 0)
500 panic("Couldn't find an APIC vector for IRQ %d",
502 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
507 ioapic_disable_intr(struct intsrc *isrc)
509 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
512 if (intpin->io_vector != 0) {
513 /* Mask this interrupt pin and free its APIC vector. */
514 vector = intpin->io_vector;
515 apic_disable_vector(intpin->io_cpu, vector);
516 mtx_lock_spin(&icu_lock);
517 intpin->io_masked = 1;
518 intpin->io_vector = 0;
519 ioapic_program_intpin(intpin);
520 mtx_unlock_spin(&icu_lock);
521 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq);
526 ioapic_vector(struct intsrc *isrc)
528 struct ioapic_intsrc *pin;
530 pin = (struct ioapic_intsrc *)isrc;
531 return (pin->io_irq);
535 ioapic_source_pending(struct intsrc *isrc)
537 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
539 if (intpin->io_vector == 0)
541 return (lapic_intr_pending(intpin->io_vector));
545 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
546 enum intr_polarity pol)
548 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
549 struct ioapic *io = (struct ioapic *)isrc->is_pic;
552 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
553 ("%s: Conforming trigger or polarity\n", __func__));
556 * EISA interrupts always use active high polarity, so don't allow
557 * them to be set to active low.
559 * XXX: Should we write to the ELCR if the trigger mode changes for
560 * an EISA IRQ or an ISA IRQ with the ELCR present?
562 mtx_lock_spin(&icu_lock);
563 if (intpin->io_bus == APIC_BUS_EISA)
564 pol = INTR_POLARITY_HIGH;
566 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
568 printf("ioapic%u: Changing trigger for pin %u to %s\n",
569 io->io_id, intpin->io_intpin,
570 trig == INTR_TRIGGER_EDGE ? "edge" : "level");
571 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
574 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
576 printf("ioapic%u: Changing polarity for pin %u to %s\n",
577 io->io_id, intpin->io_intpin,
578 pol == INTR_POLARITY_HIGH ? "high" : "low");
579 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
583 ioapic_program_intpin(intpin);
584 mtx_unlock_spin(&icu_lock);
589 ioapic_resume(struct pic *pic, bool suspend_cancelled)
591 struct ioapic *io = (struct ioapic *)pic;
594 mtx_lock_spin(&icu_lock);
595 for (i = 0; i < io->io_numintr; i++)
596 ioapic_program_intpin(&io->io_pins[i]);
597 mtx_unlock_spin(&icu_lock);
601 * Create a plain I/O APIC object.
604 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase)
607 struct ioapic_intsrc *intpin;
608 volatile ioapic_t *apic;
612 /* Map the register window so we can access the device. */
613 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION);
614 mtx_lock_spin(&icu_lock);
615 value = ioapic_read(apic, IOAPIC_VER);
616 mtx_unlock_spin(&icu_lock);
618 /* If it's version register doesn't seem to work, punt. */
619 if (value == 0xffffffff) {
620 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
624 /* Determine the number of vectors and set the APIC ID. */
625 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
626 io = malloc(sizeof(struct ioapic) +
627 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
628 io->io_pic = ioapic_template;
631 mtx_lock_spin(&icu_lock);
632 io->io_id = next_id++;
633 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
634 if (apic_id != -1 && io->io_apic_id != apic_id) {
635 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
636 mtx_unlock_spin(&icu_lock);
637 io->io_apic_id = apic_id;
638 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
641 mtx_unlock_spin(&icu_lock);
643 intbase = next_ioapic_base;
644 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
646 } else if (intbase != next_ioapic_base && bootverbose)
647 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
648 io->io_id, intbase, next_ioapic_base);
649 io->io_intbase = intbase;
650 next_ioapic_base = intbase + numintr;
651 io->io_numintr = numintr;
656 printf("ioapic%u: ver 0x%02x maxredir 0x%02x\n", io->io_id,
657 (value & IOART_VER_VERSION), (value & IOART_VER_MAXREDIR)
661 * The summary information about IO-APIC versions is taken from
662 * the Linux kernel source:
664 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
665 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
667 * IO-APICs with version >= 0x20 have working EOIR register.
669 io->io_haseoi = (value & IOART_VER_VERSION) >= 0x20;
672 * Initialize pins. Start off with interrupts disabled. Default
673 * to active-hi and edge-triggered for ISA interrupts and active-lo
674 * and level-triggered for all others.
676 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
677 mtx_lock_spin(&icu_lock);
678 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
679 intpin->io_intsrc.is_pic = (struct pic *)io;
680 intpin->io_intpin = i;
681 intpin->io_irq = intbase + i;
684 * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
685 * Assume that pins 1-15 are ISA interrupts and that all
686 * other pins are PCI interrupts.
688 if (intpin->io_irq == 0)
689 ioapic_set_extint(io, i);
690 else if (intpin->io_irq < IOAPIC_ISA_INTS) {
691 intpin->io_bus = APIC_BUS_ISA;
692 intpin->io_activehi = 1;
693 intpin->io_edgetrigger = 1;
694 intpin->io_masked = 1;
696 intpin->io_bus = APIC_BUS_PCI;
697 intpin->io_activehi = 0;
698 intpin->io_edgetrigger = 0;
699 intpin->io_masked = 1;
703 * Route interrupts to the BSP by default. Interrupts may
704 * be routed to other CPUs later after they are enabled.
706 intpin->io_cpu = PCPU_GET(apic_id);
707 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
708 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
710 /* dummy, but sets cookie */
711 mtx_unlock_spin(&icu_lock);
712 iommu_map_ioapic_intr(io->io_apic_id,
713 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
714 intpin->io_activehi, intpin->io_irq,
715 &intpin->io_remap_cookie, NULL, NULL);
716 mtx_lock_spin(&icu_lock);
719 mtx_unlock_spin(&icu_lock);
725 ioapic_get_vector(void *cookie, u_int pin)
729 io = (struct ioapic *)cookie;
730 if (pin >= io->io_numintr)
732 return (io->io_pins[pin].io_irq);
736 ioapic_disable_pin(void *cookie, u_int pin)
740 io = (struct ioapic *)cookie;
741 if (pin >= io->io_numintr)
743 if (io->io_pins[pin].io_irq == IRQ_DISABLED)
745 io->io_pins[pin].io_irq = IRQ_DISABLED;
747 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
752 ioapic_remap_vector(void *cookie, u_int pin, int vector)
756 io = (struct ioapic *)cookie;
757 if (pin >= io->io_numintr || vector < 0)
759 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
761 io->io_pins[pin].io_irq = vector;
763 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
769 ioapic_set_bus(void *cookie, u_int pin, int bus_type)
773 if (bus_type < 0 || bus_type > APIC_BUS_MAX)
775 io = (struct ioapic *)cookie;
776 if (pin >= io->io_numintr)
778 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
780 if (io->io_pins[pin].io_bus == bus_type)
782 io->io_pins[pin].io_bus = bus_type;
784 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
785 ioapic_bus_string(bus_type));
790 ioapic_set_nmi(void *cookie, u_int pin)
794 io = (struct ioapic *)cookie;
795 if (pin >= io->io_numintr)
797 if (io->io_pins[pin].io_irq == IRQ_NMI)
799 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
801 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
802 io->io_pins[pin].io_irq = IRQ_NMI;
803 io->io_pins[pin].io_masked = 0;
804 io->io_pins[pin].io_edgetrigger = 1;
805 io->io_pins[pin].io_activehi = 1;
807 printf("ioapic%u: Routing NMI -> intpin %d\n",
813 ioapic_set_smi(void *cookie, u_int pin)
817 io = (struct ioapic *)cookie;
818 if (pin >= io->io_numintr)
820 if (io->io_pins[pin].io_irq == IRQ_SMI)
822 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
824 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
825 io->io_pins[pin].io_irq = IRQ_SMI;
826 io->io_pins[pin].io_masked = 0;
827 io->io_pins[pin].io_edgetrigger = 1;
828 io->io_pins[pin].io_activehi = 1;
830 printf("ioapic%u: Routing SMI -> intpin %d\n",
836 ioapic_set_extint(void *cookie, u_int pin)
840 io = (struct ioapic *)cookie;
841 if (pin >= io->io_numintr)
843 if (io->io_pins[pin].io_irq == IRQ_EXTINT)
845 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
847 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
848 io->io_pins[pin].io_irq = IRQ_EXTINT;
850 io->io_pins[pin].io_masked = 0;
852 io->io_pins[pin].io_masked = 1;
853 io->io_pins[pin].io_edgetrigger = 1;
854 io->io_pins[pin].io_activehi = 1;
856 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
862 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
867 io = (struct ioapic *)cookie;
868 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
870 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
872 activehi = (pol == INTR_POLARITY_HIGH);
873 if (io->io_pins[pin].io_activehi == activehi)
875 io->io_pins[pin].io_activehi = activehi;
877 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
878 pol == INTR_POLARITY_HIGH ? "high" : "low");
883 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
888 io = (struct ioapic *)cookie;
889 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
891 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
893 edgetrigger = (trigger == INTR_TRIGGER_EDGE);
894 if (io->io_pins[pin].io_edgetrigger == edgetrigger)
896 io->io_pins[pin].io_edgetrigger = edgetrigger;
898 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
899 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
904 * Register a complete I/O APIC object with the interrupt subsystem.
907 ioapic_register(void *cookie)
909 struct ioapic_intsrc *pin;
911 volatile ioapic_t *apic;
915 io = (struct ioapic *)cookie;
917 mtx_lock_spin(&icu_lock);
918 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
919 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
920 mtx_unlock_spin(&icu_lock);
921 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
922 io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
923 io->io_intbase + io->io_numintr - 1);
926 * Reprogram pins to handle special case pins (such as NMI and
927 * SMI) and register valid pins as interrupt sources.
929 intr_register_pic(&io->io_pic);
930 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
931 ioapic_reprogram_intpin(&pin->io_intsrc);
932 if (pin->io_irq < NUM_IO_INTS)
933 intr_register_source(&pin->io_intsrc);
937 /* A simple new-bus driver to consume PCI I/O APIC devices. */
939 ioapic_pci_probe(device_t dev)
942 if (pci_get_class(dev) == PCIC_BASEPERIPH &&
943 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) {
944 switch (pci_get_progif(dev)) {
945 case PCIP_BASEPERIPH_PIC_IO_APIC:
946 device_set_desc(dev, "IO APIC");
948 case PCIP_BASEPERIPH_PIC_IOX_APIC:
949 device_set_desc(dev, "IO(x) APIC");
961 ioapic_pci_attach(device_t dev)
963 struct resource *res;
964 volatile ioapic_t *apic;
970 * Try to match the enumerated ioapic. Match BAR start
971 * against io_paddr. Due to a fear that PCI window is not the
972 * same as the MADT reported io window, but an alias, read the
973 * APIC ID from the mapped BAR and match against it.
976 res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
977 RF_ACTIVE | RF_SHAREABLE);
980 device_printf(dev, "cannot activate BAR0\n");
983 apic = (volatile ioapic_t *)rman_get_virtual(res);
984 if (rman_get_size(res) < IOAPIC_WND_SIZE) {
987 "BAR0 too small (%jd) for IOAPIC window\n",
988 (uintmax_t)rman_get_size(res));
991 mtx_lock_spin(&icu_lock);
992 apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
993 /* First match by io window address */
994 STAILQ_FOREACH(io, &ioapic_list, io_next) {
995 if (io->io_paddr == (vm_paddr_t)rman_get_start(res))
998 /* Then by apic id */
999 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1000 if (io->io_apic_id == apic_id)
1003 mtx_unlock_spin(&icu_lock);
1006 "cannot match pci bar apic id %d against MADT\n",
1009 bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
1012 KASSERT(io->pci_dev == NULL,
1013 ("ioapic %d pci_dev not NULL", io->io_id));
1014 KASSERT(io->pci_wnd == NULL,
1015 ("ioapic %d pci_wnd not NULL", io->io_id));
1019 if (bootverbose && (io->io_paddr != (vm_paddr_t)rman_get_start(res) ||
1020 io->io_apic_id != apic_id)) {
1021 device_printf(dev, "pci%d:%d:%d:%d pci BAR0@%jx id %d "
1022 "MADT id %d paddr@%jx\n",
1023 pci_get_domain(dev), pci_get_bus(dev),
1024 pci_get_slot(dev), pci_get_function(dev),
1025 (uintmax_t)rman_get_start(res), apic_id,
1026 io->io_apic_id, (uintmax_t)io->io_paddr);
1028 mtx_unlock_spin(&icu_lock);
1032 static device_method_t ioapic_pci_methods[] = {
1033 /* Device interface */
1034 DEVMETHOD(device_probe, ioapic_pci_probe),
1035 DEVMETHOD(device_attach, ioapic_pci_attach),
1040 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0);
1042 static devclass_t ioapic_devclass;
1043 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0);
1046 ioapic_get_rid(u_int apic_id, uint16_t *ridp)
1052 mtx_lock_spin(&icu_lock);
1053 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1054 if (io->io_apic_id == apic_id)
1057 mtx_unlock_spin(&icu_lock);
1058 if (io == NULL || io->pci_dev == NULL)
1060 error = pci_get_id(io->pci_dev, PCI_ID_RID, &rid);
1068 * A new-bus driver to consume the memory resources associated with
1069 * the APICs in the system. On some systems ACPI or PnPBIOS system
1070 * resource devices may already claim these resources. To keep from
1071 * breaking those devices, we attach ourself to the nexus device after
1072 * legacy0 and acpi0 and ignore any allocation failures.
1075 apic_identify(driver_t *driver, device_t parent)
1079 * Add at order 12. acpi0 is probed at order 10 and legacy0
1080 * is probed at order 11.
1082 if (lapic_paddr != 0)
1083 BUS_ADD_CHILD(parent, 12, "apic", 0);
1087 apic_probe(device_t dev)
1090 device_set_desc(dev, "APIC resources");
1096 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length)
1100 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length);
1102 panic("apic_add_resource: resource %d failed set with %d", rid,
1104 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_SHAREABLE);
1108 apic_attach(device_t dev)
1113 /* Reserve the local APIC. */
1114 apic_add_resource(dev, 0, lapic_paddr, LAPIC_MEM_REGION);
1116 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1117 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION);
1123 static device_method_t apic_methods[] = {
1124 /* Device interface */
1125 DEVMETHOD(device_identify, apic_identify),
1126 DEVMETHOD(device_probe, apic_probe),
1127 DEVMETHOD(device_attach, apic_attach),
1132 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0);
1134 static devclass_t apic_devclass;
1135 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0);
1137 #include "opt_ddb.h"
1140 #include <ddb/ddb.h>
1143 ioapic_delivery_mode(uint32_t mode)
1147 case IOART_DELFIXED:
1149 case IOART_DELLOPRI:
1150 return ("lowestpri");
1161 case IOART_DELEXINT:
1169 db_ioapic_read(volatile ioapic_t *apic, int reg)
1172 apic->ioregsel = reg;
1173 return (apic->iowin);
1177 db_show_ioapic_one(volatile ioapic_t *io_addr)
1182 r = db_ioapic_read(io_addr, IOAPIC_VER);
1183 mre = (r & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT;
1184 db_printf("Id 0x%08x Ver 0x%02x MRE %d\n",
1185 db_ioapic_read(io_addr, IOAPIC_ID), r & IOART_VER_VERSION, mre);
1186 for (i = 0; i < mre; i++) {
1187 lo = db_ioapic_read(io_addr, IOAPIC_REDTBL_LO(i));
1188 hi = db_ioapic_read(io_addr, IOAPIC_REDTBL_HI(i));
1189 db_printf(" pin %d Dest %s/%x %smasked Trig %s RemoteIRR %d "
1190 "Polarity %s Status %s DeliveryMode %s Vec %d\n", i,
1191 (lo & IOART_DESTMOD) == IOART_DESTLOG ? "log" : "phy",
1192 (hi & IOART_DEST) >> 24,
1193 (lo & IOART_INTMASK) == IOART_INTMSET ? "" : "not",
1194 (lo & IOART_TRGRMOD) == IOART_TRGRLVL ? "lvl" : "edge",
1195 (lo & IOART_REM_IRR) == IOART_REM_IRR ? 1 : 0,
1196 (lo & IOART_INTPOL) == IOART_INTALO ? "low" : "high",
1197 (lo & IOART_DELIVS) == IOART_DELIVS ? "pend" : "idle",
1198 ioapic_delivery_mode(lo & IOART_DELMOD),
1199 (lo & IOART_INTVEC));
1203 DB_SHOW_COMMAND(ioapic, db_show_ioapic)
1205 struct ioapic *ioapic;
1209 db_printf("usage: show ioapic index\n");
1215 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) {
1217 db_show_ioapic_one(ioapic->io_addr);
1224 DB_SHOW_ALL_COMMAND(ioapics, db_show_all_ioapics)
1226 struct ioapic *ioapic;
1228 STAILQ_FOREACH(ioapic, &ioapic_list, io_next)
1229 db_show_ioapic_one(ioapic->io_addr);