2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Local APIC support on Pentium and later processors.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_atpic.h"
38 #include "opt_hwpmc_hooks.h"
39 #include "opt_kdtrace.h"
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/kernel.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
53 #include <sys/timeet.h>
58 #include <x86/apicreg.h>
59 #include <machine/cpu.h>
60 #include <machine/cputypes.h>
61 #include <machine/frame.h>
62 #include <machine/intr_machdep.h>
63 #include <machine/apicvar.h>
65 #include <machine/md_var.h>
66 #include <machine/smp.h>
67 #include <machine/specialreg.h>
70 #include <sys/interrupt.h>
75 #define SDT_APIC SDT_SYSIGT
76 #define SDT_APICT SDT_SYSIGT
79 #define SDT_APIC SDT_SYS386IGT
80 #define SDT_APICT SDT_SYS386TGT
81 #define GSEL_APIC GSEL(GCODE_SEL, SEL_KPL)
84 /* Sanity checks on IDT vectors. */
85 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
86 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
87 CTASSERT(APIC_LOCAL_INTS == 240);
88 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
90 /* Magic IRQ values for the timer and syscalls. */
91 #define IRQ_TIMER (NUM_IO_INTS + 1)
92 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
93 #define IRQ_DTRACE_RET (NUM_IO_INTS + 3)
94 #define IRQ_EVTCHN (NUM_IO_INTS + 4)
97 * Support for local APICs. Local APICs manage interrupts on each
98 * individual processor as opposed to I/O APICs which receive interrupts
99 * from I/O devices and then forward them on to the local APICs.
101 * Local APICs can also send interrupts to each other thus providing the
102 * mechanism for IPIs.
106 u_int lvt_edgetrigger:1;
107 u_int lvt_activehi:1;
115 struct lvt la_lvts[LVT_MAX + 1];
118 u_int la_cluster_id:2;
120 u_long *la_timer_count;
121 u_long la_timer_period;
123 uint32_t lvt_timer_cache;
124 /* Include IDT_SYSCALL to make indexing easier. */
125 int la_ioint_irqs[APIC_NUM_IOINTS + 1];
126 } static lapics[MAX_APIC_ID + 1];
128 /* Global defaults for local APIC LVT entries. */
129 static struct lvt lvts[LVT_MAX + 1] = {
130 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
131 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
132 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
133 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
134 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
135 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
136 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_CMC_INT }, /* CMCI */
139 static inthand_t *ioint_handlers[] = {
141 IDTVEC(apic_isr1), /* 32 - 63 */
142 IDTVEC(apic_isr2), /* 64 - 95 */
143 IDTVEC(apic_isr3), /* 96 - 127 */
144 IDTVEC(apic_isr4), /* 128 - 159 */
145 IDTVEC(apic_isr5), /* 160 - 191 */
146 IDTVEC(apic_isr6), /* 192 - 223 */
147 IDTVEC(apic_isr7), /* 224 - 255 */
151 static u_int32_t lapic_timer_divisors[] = {
152 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
153 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
156 extern inthand_t IDTVEC(rsvd);
158 volatile lapic_t *lapic;
159 vm_paddr_t lapic_paddr;
160 static u_long lapic_timer_divisor;
161 static struct eventtimer lapic_et;
163 static void lapic_enable(void);
164 static void lapic_resume(struct pic *pic, bool suspend_cancelled);
165 static void lapic_timer_oneshot(struct lapic *,
166 u_int count, int enable_int);
167 static void lapic_timer_periodic(struct lapic *,
168 u_int count, int enable_int);
169 static void lapic_timer_stop(struct lapic *);
170 static void lapic_timer_set_divisor(u_int divisor);
171 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
172 static int lapic_et_start(struct eventtimer *et,
173 sbintime_t first, sbintime_t period);
174 static int lapic_et_stop(struct eventtimer *et);
176 struct pic lapic_pic = { .pic_resume = lapic_resume };
179 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
183 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
184 if (la->la_lvts[pin].lvt_active)
185 lvt = &la->la_lvts[pin];
189 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
191 if (lvt->lvt_edgetrigger == 0)
192 value |= APIC_LVT_TM;
193 if (lvt->lvt_activehi == 0)
194 value |= APIC_LVT_IIPP_INTALO;
197 value |= lvt->lvt_mode;
198 switch (lvt->lvt_mode) {
199 case APIC_LVT_DM_NMI:
200 case APIC_LVT_DM_SMI:
201 case APIC_LVT_DM_INIT:
202 case APIC_LVT_DM_EXTINT:
203 if (!lvt->lvt_edgetrigger) {
204 printf("lapic%u: Forcing LINT%u to edge trigger\n",
206 value |= APIC_LVT_TM;
208 /* Use a vector of 0. */
210 case APIC_LVT_DM_FIXED:
211 value |= lvt->lvt_vector;
214 panic("bad APIC LVT delivery mode: %#x\n", value);
220 * Map the local APIC and setup necessary interrupt vectors.
223 lapic_init(vm_paddr_t addr)
228 /* Map the local APIC and setup the spurious interrupt handler. */
229 KASSERT(trunc_page(addr) == addr,
230 ("local APIC not aligned on a page boundary"));
232 lapic = pmap_mapdev(addr, sizeof(lapic_t));
233 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_APIC, SEL_KPL,
236 /* Perform basic initialization of the BSP's local APIC. */
239 /* Set BSP's per-CPU local APIC ID. */
240 PCPU_SET(apic_id, lapic_id());
242 /* Local APIC timer interrupt. */
243 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_APIC, SEL_KPL, GSEL_APIC);
245 /* Local APIC error interrupt. */
246 setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_APIC, SEL_KPL, GSEL_APIC);
248 /* XXX: Thermal interrupt */
250 /* Local APIC CMCI. */
251 setidt(APIC_CMC_INT, IDTVEC(cmcint), SDT_APICT, SEL_KPL, GSEL_APIC);
253 if ((resource_int_value("apic", 0, "clock", &i) != 0 || i != 0)) {
255 /* Intel CPUID 0x06 EAX[2] set if APIC timer runs in C3. */
256 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high >= 6) {
257 do_cpuid(0x06, regs);
258 if ((regs[0] & CPUTPM1_ARAT) != 0)
261 bzero(&lapic_et, sizeof(lapic_et));
262 lapic_et.et_name = "LAPIC";
263 lapic_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
265 lapic_et.et_quality = 600;
267 lapic_et.et_flags |= ET_FLAGS_C3STOP;
268 lapic_et.et_quality -= 200;
270 lapic_et.et_frequency = 0;
271 /* We don't know frequency yet, so trying to guess. */
272 lapic_et.et_min_period = 0x00001000LL;
273 lapic_et.et_max_period = SBT_1S;
274 lapic_et.et_start = lapic_et_start;
275 lapic_et.et_stop = lapic_et_stop;
276 lapic_et.et_priv = NULL;
277 et_register(&lapic_et);
282 * Create a local APIC instance.
285 lapic_create(u_int apic_id, int boot_cpu)
289 if (apic_id > MAX_APIC_ID) {
290 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
292 panic("Can't ignore BSP");
295 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
299 * Assume no local LVT overrides and a cluster of 0 and
300 * intra-cluster ID of 0.
302 lapics[apic_id].la_present = 1;
303 lapics[apic_id].la_id = apic_id;
304 for (i = 0; i <= LVT_MAX; i++) {
305 lapics[apic_id].la_lvts[i] = lvts[i];
306 lapics[apic_id].la_lvts[i].lvt_active = 0;
308 for (i = 0; i <= APIC_NUM_IOINTS; i++)
309 lapics[apic_id].la_ioint_irqs[i] = -1;
310 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
311 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] =
314 lapics[apic_id].la_ioint_irqs[IDT_DTRACE_RET - APIC_IO_INTS] =
318 lapics[apic_id].la_ioint_irqs[IDT_EVTCHN - APIC_IO_INTS] = IRQ_EVTCHN;
323 cpu_add(apic_id, boot_cpu);
328 * Dump contents of local APIC registers
331 lapic_dump(const char* str)
335 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
336 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
337 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
338 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
339 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
340 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
341 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x",
342 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error);
343 if (maxlvt >= LVT_PMC)
344 printf(" pmc: 0x%08x", lapic->lvt_pcint);
346 if (maxlvt >= LVT_CMCI)
347 printf(" cmci: 0x%08x\n", lapic->lvt_cmci);
351 lapic_setup(int boot)
356 char buf[MAXCOMLEN + 1];
358 la = &lapics[lapic_id()];
359 KASSERT(la->la_present, ("missing APIC structure"));
360 saveintr = intr_disable();
361 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
363 /* Initialize the TPR to allow all interrupts. */
366 /* Setup spurious vector and enable the local APIC. */
369 /* Program LINT[01] LVT entries. */
370 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
371 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
373 /* Program the PMC LVT entry if present. */
374 if (maxlvt >= LVT_PMC)
375 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
377 /* Program timer LVT and setup handler. */
378 la->lvt_timer_cache = lapic->lvt_timer =
379 lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
381 snprintf(buf, sizeof(buf), "cpu%d:timer", PCPU_GET(cpuid));
382 intrcnt_add(buf, &la->la_timer_count);
385 /* Setup the timer if configured. */
386 if (la->la_timer_mode != 0) {
387 KASSERT(la->la_timer_period != 0, ("lapic%u: zero divisor",
389 lapic_timer_set_divisor(lapic_timer_divisor);
390 if (la->la_timer_mode == 1)
391 lapic_timer_periodic(la, la->la_timer_period, 1);
393 lapic_timer_oneshot(la, la->la_timer_period, 1);
396 /* Program error LVT and clear any existing errors. */
397 lapic->lvt_error = lvt_mode(la, LVT_ERROR, lapic->lvt_error);
400 /* XXX: Thermal LVT */
402 /* Program the CMCI LVT entry if present. */
403 if (maxlvt >= LVT_CMCI)
404 lapic->lvt_cmci = lvt_mode(la, LVT_CMCI, lapic->lvt_cmci);
406 intr_restore(saveintr);
410 lapic_reenable_pmc(void)
415 value = lapic->lvt_pcint;
416 value &= ~APIC_LVT_M;
417 lapic->lvt_pcint = value;
423 lapic_update_pmc(void *dummy)
427 la = &lapics[lapic_id()];
428 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
433 lapic_enable_pmc(void)
438 /* Fail if the local APIC is not present. */
442 /* Fail if the PMC LVT is not present. */
443 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
444 if (maxlvt < LVT_PMC)
447 lvts[LVT_PMC].lvt_masked = 0;
451 * If hwpmc was loaded at boot time then the APs may not be
452 * started yet. In that case, don't forward the request to
453 * them as they will program the lvt when they start.
456 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
459 lapic_update_pmc(NULL);
467 lapic_disable_pmc(void)
472 /* Fail if the local APIC is not present. */
476 /* Fail if the PMC LVT is not present. */
477 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
478 if (maxlvt < LVT_PMC)
481 lvts[LVT_PMC].lvt_masked = 1;
484 /* The APs should always be started when hwpmc is unloaded. */
485 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early"));
487 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
492 lapic_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
497 la = &lapics[PCPU_GET(apic_id)];
498 if (et->et_frequency == 0) {
499 /* Start off with a divisor of 2 (power on reset default). */
500 lapic_timer_divisor = 2;
501 /* Try to calibrate the local APIC timer. */
503 lapic_timer_set_divisor(lapic_timer_divisor);
504 lapic_timer_oneshot(la, APIC_TIMER_MAX_COUNT, 0);
506 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
507 if (value != APIC_TIMER_MAX_COUNT)
509 lapic_timer_divisor <<= 1;
510 } while (lapic_timer_divisor <= 128);
511 if (lapic_timer_divisor > 128)
512 panic("lapic: Divisor too big");
514 printf("lapic: Divisor %lu, Frequency %lu Hz\n",
515 lapic_timer_divisor, value);
516 et->et_frequency = value;
517 et->et_min_period = (0x00000002LLU << 32) / et->et_frequency;
518 et->et_max_period = (0xfffffffeLLU << 32) / et->et_frequency;
520 if (la->la_timer_mode == 0)
521 lapic_timer_set_divisor(lapic_timer_divisor);
523 la->la_timer_mode = 1;
524 la->la_timer_period = ((uint32_t)et->et_frequency * period) >> 32;
525 lapic_timer_periodic(la, la->la_timer_period, 1);
527 la->la_timer_mode = 2;
528 la->la_timer_period = ((uint32_t)et->et_frequency * first) >> 32;
529 lapic_timer_oneshot(la, la->la_timer_period, 1);
535 lapic_et_stop(struct eventtimer *et)
537 struct lapic *la = &lapics[PCPU_GET(apic_id)];
539 la->la_timer_mode = 0;
540 lapic_timer_stop(la);
549 /* Software disable the local APIC. */
551 value &= ~APIC_SVR_SWEN;
560 /* Program the spurious vector to enable the local APIC. */
562 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
563 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
567 /* Reset the local APIC on the BSP during resume. */
569 lapic_resume(struct pic *pic, bool suspend_cancelled)
579 KASSERT(lapic != NULL, ("local APIC is not mapped"));
580 return (lapic->id >> APIC_ID_SHIFT);
584 lapic_intr_pending(u_int vector)
586 volatile u_int32_t *irr;
589 * The IRR registers are an array of 128-bit registers each of
590 * which only describes 32 interrupts in the low 32 bits.. Thus,
591 * we divide the vector by 32 to get the 128-bit index. We then
592 * multiply that index by 4 to get the equivalent index from
593 * treating the IRR as an array of 32-bit registers. Finally, we
594 * modulus the vector by 32 to determine the individual bit to
598 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
602 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
606 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
608 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
610 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
611 ("%s: intra cluster id %u too big", __func__, cluster_id));
612 la = &lapics[apic_id];
613 la->la_cluster = cluster;
614 la->la_cluster_id = cluster_id;
618 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
623 if (apic_id == APIC_ID_ALL) {
624 lvts[pin].lvt_masked = masked;
628 KASSERT(lapics[apic_id].la_present,
629 ("%s: missing APIC %u", __func__, apic_id));
630 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
631 lapics[apic_id].la_lvts[pin].lvt_active = 1;
633 printf("lapic%u:", apic_id);
636 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
641 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
647 if (apic_id == APIC_ID_ALL) {
652 KASSERT(lapics[apic_id].la_present,
653 ("%s: missing APIC %u", __func__, apic_id));
654 lvt = &lapics[apic_id].la_lvts[pin];
657 printf("lapic%u:", apic_id);
659 lvt->lvt_mode = mode;
661 case APIC_LVT_DM_NMI:
662 case APIC_LVT_DM_SMI:
663 case APIC_LVT_DM_INIT:
664 case APIC_LVT_DM_EXTINT:
665 lvt->lvt_edgetrigger = 1;
666 lvt->lvt_activehi = 1;
667 if (mode == APIC_LVT_DM_EXTINT)
673 panic("Unsupported delivery mode: 0x%x\n", mode);
678 case APIC_LVT_DM_NMI:
681 case APIC_LVT_DM_SMI:
684 case APIC_LVT_DM_INIT:
687 case APIC_LVT_DM_EXTINT:
691 printf(" -> LINT%u\n", pin);
697 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
700 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
702 if (apic_id == APIC_ID_ALL) {
703 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
707 KASSERT(lapics[apic_id].la_present,
708 ("%s: missing APIC %u", __func__, apic_id));
709 lapics[apic_id].la_lvts[pin].lvt_active = 1;
710 lapics[apic_id].la_lvts[pin].lvt_activehi =
711 (pol == INTR_POLARITY_HIGH);
713 printf("lapic%u:", apic_id);
716 printf(" LINT%u polarity: %s\n", pin,
717 pol == INTR_POLARITY_HIGH ? "high" : "low");
722 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
725 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
727 if (apic_id == APIC_ID_ALL) {
728 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
732 KASSERT(lapics[apic_id].la_present,
733 ("%s: missing APIC %u", __func__, apic_id));
734 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
735 (trigger == INTR_TRIGGER_EDGE);
736 lapics[apic_id].la_lvts[pin].lvt_active = 1;
738 printf("lapic%u:", apic_id);
741 printf(" LINT%u trigger: %s\n", pin,
742 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
747 * Adjust the TPR of the current CPU so that it blocks all interrupts below
748 * the passed in vector.
751 lapic_set_tpr(u_int vector)
758 tpr = lapic->tpr & ~APIC_TPR_PRIO;
772 lapic_handle_intr(int vector, struct trapframe *frame)
776 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id),
778 intr_execute_handlers(isrc, frame);
782 lapic_handle_timer(struct trapframe *frame)
785 struct trapframe *oldframe;
788 /* Send EOI first thing. */
791 #if defined(SMP) && !defined(SCHED_ULE)
793 * Don't do any accounting for the disabled HTT cores, since it
794 * will provide misleading numbers for the userland.
796 * No locking is necessary here, since even if we lose the race
797 * when hlt_cpus_mask changes it is not a big deal, really.
799 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
800 * and unlike other schedulers it actually schedules threads to
803 if (CPU_ISSET(PCPU_GET(cpuid), &hlt_cpus_mask))
807 /* Look up our local APIC structure for the tick counters. */
808 la = &lapics[PCPU_GET(apic_id)];
809 (*la->la_timer_count)++;
811 if (lapic_et.et_active) {
813 td->td_intr_nesting_level++;
814 oldframe = td->td_intr_frame;
815 td->td_intr_frame = frame;
816 lapic_et.et_event_cb(&lapic_et, lapic_et.et_arg);
817 td->td_intr_frame = oldframe;
818 td->td_intr_nesting_level--;
824 lapic_timer_set_divisor(u_int divisor)
827 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
828 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
829 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
830 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
834 lapic_timer_oneshot(struct lapic *la, u_int count, int enable_int)
838 value = la->lvt_timer_cache;
839 value &= ~APIC_LVTT_TM;
840 value |= APIC_LVTT_TM_ONE_SHOT;
842 value &= ~APIC_LVT_M;
843 lapic->lvt_timer = value;
844 lapic->icr_timer = count;
848 lapic_timer_periodic(struct lapic *la, u_int count, int enable_int)
852 value = la->lvt_timer_cache;
853 value &= ~APIC_LVTT_TM;
854 value |= APIC_LVTT_TM_PERIODIC;
856 value &= ~APIC_LVT_M;
857 lapic->lvt_timer = value;
858 lapic->icr_timer = count;
862 lapic_timer_stop(struct lapic *la)
866 value = la->lvt_timer_cache;
867 value &= ~APIC_LVTT_TM;
869 lapic->lvt_timer = value;
873 lapic_handle_cmc(void)
881 * Called from the mca_init() to activate the CMC interrupt if this CPU is
882 * responsible for monitoring any MC banks for CMC events. Since mca_init()
883 * is called prior to lapic_setup() during boot, this just needs to unmask
884 * this CPU's LVT_CMCI entry.
887 lapic_enable_cmc(void)
895 apic_id = PCPU_GET(apic_id);
896 KASSERT(lapics[apic_id].la_present,
897 ("%s: missing APIC %u", __func__, apic_id));
898 lapics[apic_id].la_lvts[LVT_CMCI].lvt_masked = 0;
899 lapics[apic_id].la_lvts[LVT_CMCI].lvt_active = 1;
901 printf("lapic%u: CMCI unmasked\n", apic_id);
905 lapic_handle_error(void)
910 * Read the contents of the error status register. Write to
911 * the register first before reading from it to force the APIC
912 * to update its value to indicate any errors that have
913 * occurred since the previous write to the register.
918 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr);
923 apic_cpuid(u_int apic_id)
926 return apic_cpuids[apic_id];
932 /* Request a free IDT vector to be used by the specified IRQ. */
934 apic_alloc_vector(u_int apic_id, u_int irq)
938 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
941 * Search for a free vector. Currently we just use a very simple
942 * algorithm to find the first free vector.
944 mtx_lock_spin(&icu_lock);
945 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
946 if (lapics[apic_id].la_ioint_irqs[vector] != -1)
948 lapics[apic_id].la_ioint_irqs[vector] = irq;
949 mtx_unlock_spin(&icu_lock);
950 return (vector + APIC_IO_INTS);
952 mtx_unlock_spin(&icu_lock);
957 * Request 'count' free contiguous IDT vectors to be used by 'count'
958 * IRQs. 'count' must be a power of two and the vectors will be
959 * aligned on a boundary of 'align'. If the request cannot be
960 * satisfied, 0 is returned.
963 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
965 u_int first, run, vector;
967 KASSERT(powerof2(count), ("bad count"));
968 KASSERT(powerof2(align), ("bad align"));
969 KASSERT(align >= count, ("align < count"));
971 for (run = 0; run < count; run++)
972 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
977 * Search for 'count' free vectors. As with apic_alloc_vector(),
978 * this just uses a simple first fit algorithm.
982 mtx_lock_spin(&icu_lock);
983 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
985 /* Vector is in use, end run. */
986 if (lapics[apic_id].la_ioint_irqs[vector] != -1) {
992 /* Start a new run if run == 0 and vector is aligned. */
994 if ((vector & (align - 1)) != 0)
1000 /* Keep looping if the run isn't long enough yet. */
1004 /* Found a run, assign IRQs and return the first vector. */
1005 for (vector = 0; vector < count; vector++)
1006 lapics[apic_id].la_ioint_irqs[first + vector] =
1008 mtx_unlock_spin(&icu_lock);
1009 return (first + APIC_IO_INTS);
1011 mtx_unlock_spin(&icu_lock);
1012 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
1017 * Enable a vector for a particular apic_id. Since all lapics share idt
1018 * entries and ioint_handlers this enables the vector on all lapics. lapics
1019 * which do not have the vector configured would report spurious interrupts
1023 apic_enable_vector(u_int apic_id, u_int vector)
1026 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1027 KASSERT(ioint_handlers[vector / 32] != NULL,
1028 ("No ISR handler for vector %u", vector));
1029 #ifdef KDTRACE_HOOKS
1030 KASSERT(vector != IDT_DTRACE_RET,
1031 ("Attempt to overwrite DTrace entry"));
1033 setidt(vector, ioint_handlers[vector / 32], SDT_APIC, SEL_KPL,
1038 apic_disable_vector(u_int apic_id, u_int vector)
1041 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1042 #ifdef KDTRACE_HOOKS
1043 KASSERT(vector != IDT_DTRACE_RET,
1044 ("Attempt to overwrite DTrace entry"));
1046 KASSERT(ioint_handlers[vector / 32] != NULL,
1047 ("No ISR handler for vector %u", vector));
1050 * We can not currently clear the idt entry because other cpus
1051 * may have a valid vector at this offset.
1053 setidt(vector, &IDTVEC(rsvd), SDT_APICT, SEL_KPL, GSEL_APIC);
1057 /* Release an APIC vector when it's no longer in use. */
1059 apic_free_vector(u_int apic_id, u_int vector, u_int irq)
1063 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1064 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1065 ("Vector %u does not map to an IRQ line", vector));
1066 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
1067 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] ==
1068 irq, ("IRQ mismatch"));
1069 #ifdef KDTRACE_HOOKS
1070 KASSERT(vector != IDT_DTRACE_RET,
1071 ("Attempt to overwrite DTrace entry"));
1075 * Bind us to the cpu that owned the vector before freeing it so
1076 * we don't lose an interrupt delivery race.
1081 if (sched_is_bound(td))
1082 panic("apic_free_vector: Thread already bound.\n");
1083 sched_bind(td, apic_cpuid(apic_id));
1086 mtx_lock_spin(&icu_lock);
1087 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1;
1088 mtx_unlock_spin(&icu_lock);
1096 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
1098 apic_idt_to_irq(u_int apic_id, u_int vector)
1102 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1103 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1104 ("Vector %u does not map to an IRQ line", vector));
1105 #ifdef KDTRACE_HOOKS
1106 KASSERT(vector != IDT_DTRACE_RET,
1107 ("Attempt to overwrite DTrace entry"));
1109 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS];
1117 * Dump data about APIC IDT vector mappings.
1119 DB_SHOW_COMMAND(apic, db_show_apic)
1121 struct intsrc *isrc;
1126 if (strcmp(modif, "vv") == 0)
1128 else if (strcmp(modif, "v") == 0)
1132 for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) {
1133 if (lapics[apic_id].la_present == 0)
1135 db_printf("Interrupts bound to lapic %u\n", apic_id);
1136 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
1137 irq = lapics[apic_id].la_ioint_irqs[i];
1138 if (irq == -1 || irq == IRQ_SYSCALL)
1140 #ifdef KDTRACE_HOOKS
1141 if (irq == IRQ_DTRACE_RET)
1145 if (irq == IRQ_EVTCHN)
1148 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
1149 if (irq == IRQ_TIMER)
1150 db_printf("lapic timer\n");
1151 else if (irq < NUM_IO_INTS) {
1152 isrc = intr_lookup_source(irq);
1153 if (isrc == NULL || verbose == 0)
1154 db_printf("IRQ %u\n", irq);
1156 db_dump_intr_event(isrc->is_event,
1159 db_printf("IRQ %u ???\n", irq);
1165 dump_mask(const char *prefix, uint32_t v, int base)
1170 for (i = 0; i < 32; i++)
1173 db_printf("%s:", prefix);
1176 db_printf(" %02x", base + i);
1182 /* Show info from the lapic regs for this CPU. */
1183 DB_SHOW_COMMAND(lapic, db_show_lapic)
1187 db_printf("lapic ID = %d\n", lapic_id());
1189 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
1191 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
1193 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
1194 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
1195 db_printf("TPR = %02x\n", lapic->tpr);
1197 #define dump_field(prefix, index) \
1198 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \
1201 db_printf("In-service Interrupts:\n");
1211 db_printf("TMR Interrupts:\n");
1221 db_printf("IRR Interrupts:\n");
1236 * APIC probing support code. This includes code to manage enumerators.
1239 static SLIST_HEAD(, apic_enumerator) enumerators =
1240 SLIST_HEAD_INITIALIZER(enumerators);
1241 static struct apic_enumerator *best_enum;
1244 apic_register_enumerator(struct apic_enumerator *enumerator)
1247 struct apic_enumerator *apic_enum;
1249 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1250 if (apic_enum == enumerator)
1251 panic("%s: Duplicate register of %s", __func__,
1252 enumerator->apic_name);
1255 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1259 * We have to look for CPU's very, very early because certain subsystems
1260 * want to know how many CPU's we have extremely early on in the boot
1264 apic_init(void *dummy __unused)
1266 struct apic_enumerator *enumerator;
1272 /* We only support built in local APICs. */
1273 if (!(cpu_feature & CPUID_APIC))
1276 /* Don't probe if APIC mode is disabled. */
1277 if (resource_disabled("apic", 0))
1280 /* Probe all the enumerators to find the best match. */
1283 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1284 retval = enumerator->apic_probe();
1287 if (best_enum == NULL || best < retval) {
1288 best_enum = enumerator;
1292 if (best_enum == NULL) {
1294 printf("APIC: Could not find any APICs.\n");
1296 panic("running without device atpic requires a local APIC");
1302 printf("APIC: Using the %s enumerator.\n",
1303 best_enum->apic_name);
1307 * To work around an errata, we disable the local APIC on some
1308 * CPUs during early startup. We need to turn the local APIC back
1309 * on on such CPUs now.
1311 if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL &&
1312 (cpu_id & 0xff0) == 0x610) {
1313 apic_base = rdmsr(MSR_APICBASE);
1314 apic_base |= APICBASE_ENABLED;
1315 wrmsr(MSR_APICBASE, apic_base);
1319 /* Probe the CPU's in the system. */
1320 retval = best_enum->apic_probe_cpus();
1322 printf("%s: Failed to probe CPUs: returned %d\n",
1323 best_enum->apic_name, retval);
1326 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL);
1329 * Setup the local APIC. We have to do this prior to starting up the APs
1333 apic_setup_local(void *dummy __unused)
1337 if (best_enum == NULL)
1340 /* Initialize the local APIC. */
1341 retval = best_enum->apic_setup_local();
1343 printf("%s: Failed to setup the local APIC: returned %d\n",
1344 best_enum->apic_name, retval);
1346 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local, NULL);
1349 * Setup the I/O APICs.
1352 apic_setup_io(void *dummy __unused)
1356 if (best_enum == NULL)
1360 * Local APIC must be registered before other PICs and pseudo PICs
1361 * for proper suspend/resume order.
1364 intr_register_pic(&lapic_pic);
1367 retval = best_enum->apic_setup_io();
1369 printf("%s: Failed to setup I/O APICs: returned %d\n",
1370 best_enum->apic_name, retval);
1375 * Finish setting up the local APIC on the BSP once we know how to
1376 * properly program the LINT pins.
1382 /* Enable the MSI "pic". */
1385 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL);
1389 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1390 * private to the MD code. The public interface for the rest of the
1391 * kernel is defined in mp_machdep.c.
1394 lapic_ipi_wait(int delay)
1399 * Wait delay loops for IPI to be sent. This is highly bogus
1400 * since this is sensitive to CPU clock speed. If delay is
1401 * -1, we wait forever.
1408 for (x = 0; x < delay; x += incr) {
1409 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1417 lapic_ipi_raw(register_t icrlo, u_int dest)
1419 register_t value, saveintr;
1421 /* XXX: Need more sanity checking of icrlo? */
1422 KASSERT(lapic != NULL, ("%s called too early", __func__));
1423 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1424 ("%s: invalid dest field", __func__));
1425 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1426 ("%s: reserved bits set in ICR LO register", __func__));
1428 /* Set destination in ICR HI register if it is being used. */
1429 saveintr = intr_disable();
1430 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1431 value = lapic->icr_hi;
1432 value &= ~APIC_ID_MASK;
1433 value |= dest << APIC_ID_SHIFT;
1434 lapic->icr_hi = value;
1437 /* Program the contents of the IPI and dispatch it. */
1438 value = lapic->icr_lo;
1439 value &= APIC_ICRLO_RESV_MASK;
1441 lapic->icr_lo = value;
1442 intr_restore(saveintr);
1445 #define BEFORE_SPIN 1000000
1446 #ifdef DETECT_DEADLOCK
1447 #define AFTER_SPIN 1000
1451 lapic_ipi_vectored(u_int vector, int dest)
1453 register_t icrlo, destfield;
1455 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1456 ("%s: invalid vector %d", __func__, vector));
1458 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE;
1461 * IPI_STOP_HARD is just a "fake" vector used to send a NMI.
1462 * Use special rules regard NMI if passed, otherwise specify
1465 if (vector == IPI_STOP_HARD)
1466 icrlo |= APIC_DELMODE_NMI | APIC_LEVEL_ASSERT;
1468 icrlo |= vector | APIC_DELMODE_FIXED | APIC_LEVEL_DEASSERT;
1471 case APIC_IPI_DEST_SELF:
1472 icrlo |= APIC_DEST_SELF;
1474 case APIC_IPI_DEST_ALL:
1475 icrlo |= APIC_DEST_ALLISELF;
1477 case APIC_IPI_DEST_OTHERS:
1478 icrlo |= APIC_DEST_ALLESELF;
1481 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1482 ("%s: invalid destination 0x%x", __func__, dest));
1486 /* Wait for an earlier IPI to finish. */
1487 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1488 if (panicstr != NULL)
1491 panic("APIC: Previous IPI is stuck");
1494 lapic_ipi_raw(icrlo, destfield);
1496 #ifdef DETECT_DEADLOCK
1497 /* Wait for IPI to be delivered. */
1498 if (!lapic_ipi_wait(AFTER_SPIN)) {
1499 #ifdef needsattention
1503 * The above function waits for the message to actually be
1504 * delivered. It breaks out after an arbitrary timeout
1505 * since the message should eventually be delivered (at
1506 * least in theory) and that if it wasn't we would catch
1507 * the failure with the check above when the next IPI is
1510 * We could skip this wait entirely, EXCEPT it probably
1511 * protects us from other routines that assume that the
1512 * message was delivered and acted upon when this function
1515 printf("APIC: IPI might be stuck\n");
1516 #else /* !needsattention */
1517 /* Wait until mesage is sent without a timeout. */
1518 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1520 #endif /* needsattention */
1522 #endif /* DETECT_DEADLOCK */