2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Local APIC support on Pentium and later processors.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_atpic.h"
38 #include "opt_hwpmc_hooks.h"
39 #include "opt_kdtrace.h"
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/kernel.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
53 #include <sys/timeet.h>
58 #include <x86/apicreg.h>
59 #include <machine/cpu.h>
60 #include <machine/cputypes.h>
61 #include <machine/frame.h>
62 #include <machine/intr_machdep.h>
63 #include <machine/apicvar.h>
65 #include <machine/md_var.h>
66 #include <machine/smp.h>
67 #include <machine/specialreg.h>
70 #include <sys/interrupt.h>
75 #define SDT_APIC SDT_SYSIGT
76 #define SDT_APICT SDT_SYSIGT
79 #define SDT_APIC SDT_SYS386IGT
80 #define SDT_APICT SDT_SYS386TGT
81 #define GSEL_APIC GSEL(GCODE_SEL, SEL_KPL)
84 /* Sanity checks on IDT vectors. */
85 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
86 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
87 CTASSERT(APIC_LOCAL_INTS == 240);
88 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
90 /* Magic IRQ values for the timer and syscalls. */
91 #define IRQ_TIMER (NUM_IO_INTS + 1)
92 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
93 #define IRQ_DTRACE_RET (NUM_IO_INTS + 3)
96 * Support for local APICs. Local APICs manage interrupts on each
97 * individual processor as opposed to I/O APICs which receive interrupts
98 * from I/O devices and then forward them on to the local APICs.
100 * Local APICs can also send interrupts to each other thus providing the
101 * mechanism for IPIs.
105 u_int lvt_edgetrigger:1;
106 u_int lvt_activehi:1;
114 struct lvt la_lvts[LVT_MAX + 1];
117 u_int la_cluster_id:2;
119 u_long *la_timer_count;
120 u_long la_timer_period;
122 uint32_t lvt_timer_cache;
123 /* Include IDT_SYSCALL to make indexing easier. */
124 int la_ioint_irqs[APIC_NUM_IOINTS + 1];
125 } static lapics[MAX_APIC_ID + 1];
127 /* Global defaults for local APIC LVT entries. */
128 static struct lvt lvts[LVT_MAX + 1] = {
129 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
130 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
131 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
132 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
133 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
134 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
135 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_CMC_INT }, /* CMCI */
138 static inthand_t *ioint_handlers[] = {
140 IDTVEC(apic_isr1), /* 32 - 63 */
141 IDTVEC(apic_isr2), /* 64 - 95 */
142 IDTVEC(apic_isr3), /* 96 - 127 */
143 IDTVEC(apic_isr4), /* 128 - 159 */
144 IDTVEC(apic_isr5), /* 160 - 191 */
145 IDTVEC(apic_isr6), /* 192 - 223 */
146 IDTVEC(apic_isr7), /* 224 - 255 */
150 static u_int32_t lapic_timer_divisors[] = {
151 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
152 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
155 extern inthand_t IDTVEC(rsvd);
157 volatile lapic_t *lapic;
158 vm_paddr_t lapic_paddr;
159 static u_long lapic_timer_divisor;
160 static struct eventtimer lapic_et;
163 static void lapic_enable(void);
164 static void lapic_resume(struct pic *pic);
165 static void lapic_timer_oneshot(struct lapic *,
166 u_int count, int enable_int);
167 static void lapic_timer_periodic(struct lapic *,
168 u_int count, int enable_int);
169 static void lapic_timer_stop(struct lapic *);
170 static void lapic_timer_set_divisor(u_int divisor);
171 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
172 static int lapic_et_start(struct eventtimer *et,
173 struct bintime *first, struct bintime *period);
174 static int lapic_et_stop(struct eventtimer *et);
175 static uint32_t lapic_version(void);
176 static uint32_t lapic_ldr(void);
177 static uint32_t lapic_dfr(void);
178 static uint32_t lapic_lvt_lint0(void);
179 static void lapic_set_lvt_lint0(uint32_t value);
180 static uint32_t lapic_lvt_lint1(void);
181 static void lapic_set_lvt_lint1(uint32_t value);
182 static uint32_t lapic_tpr(void);
183 static uint32_t lapic_svr(void);
184 static void lapic_set_svr(uint32_t value);
185 static uint32_t lapic_lvt_timer(void);
186 static void lapic_set_lvt_timer(uint32_t value);
187 static uint32_t lapic_lvt_thermal(void);
188 static uint32_t lapic_lvt_error(void);
189 static void lapic_set_lvt_error(uint32_t value);
190 static uint32_t lapic_lvt_pcint(void);
191 static void lapic_set_lvt_pcint(uint32_t value);
192 static uint32_t lapic_lvt_cmci(void);
193 static void lapic_set_lvt_cmci(uint32_t value);
194 static uint32_t lapic_esr(void);
195 static void lapic_set_esr(uint32_t value);
196 static uint32_t lapic_ccr_timer(void);
197 static void lapic_set_dcr_timer(uint32_t value);
198 static void lapic_set_icr_timer(uint32_t value);
199 uint32_t lapic_irr(int num);
200 uint32_t lapic_tmr(int num);
201 uint32_t lapic_isr(int num);
202 static uint32_t lapic_icr_lo(void);
203 static uint32_t lapic_icr_hi(void);
204 static void lapic_set_icr(uint64_t value);
205 static boolean_t lapic_missing(void);
207 struct pic lapic_pic = { .pic_resume = lapic_resume };
210 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
214 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
215 if (la->la_lvts[pin].lvt_active)
216 lvt = &la->la_lvts[pin];
220 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
222 if (lvt->lvt_edgetrigger == 0)
223 value |= APIC_LVT_TM;
224 if (lvt->lvt_activehi == 0)
225 value |= APIC_LVT_IIPP_INTALO;
228 value |= lvt->lvt_mode;
229 switch (lvt->lvt_mode) {
230 case APIC_LVT_DM_NMI:
231 case APIC_LVT_DM_SMI:
232 case APIC_LVT_DM_INIT:
233 case APIC_LVT_DM_EXTINT:
234 if (!lvt->lvt_edgetrigger) {
235 printf("lapic%u: Forcing LINT%u to edge trigger\n",
237 value |= APIC_LVT_TM;
239 /* Use a vector of 0. */
241 case APIC_LVT_DM_FIXED:
242 value |= lvt->lvt_vector;
245 panic("bad APIC LVT delivery mode: %#x\n", value);
251 * Map the local APIC and setup necessary interrupt vectors.
254 lapic_init(vm_paddr_t addr)
259 if ((cpu_feature2 & CPUID2_X2APIC) != 0 &&
260 (rdmsr(MSR_APICBASE) & APICBASE_X2APIC) != 0) {
263 printf("Local APIC access using x2APIC MSRs\n");
265 KASSERT(trunc_page(addr) == addr,
266 ("local APIC not aligned on a page boundary"));
267 lapic = pmap_mapdev(addr, sizeof(lapic_t));
270 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_APIC, SEL_KPL,
273 /* Perform basic initialization of the BSP's local APIC. */
276 /* Set BSP's per-CPU local APIC ID. */
277 PCPU_SET(apic_id, lapic_id());
279 /* Local APIC timer interrupt. */
280 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_APIC, SEL_KPL, GSEL_APIC);
282 /* Local APIC error interrupt. */
283 setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_APIC, SEL_KPL, GSEL_APIC);
285 /* XXX: Thermal interrupt */
287 /* Local APIC CMCI. */
288 setidt(APIC_CMC_INT, IDTVEC(cmcint), SDT_APICT, SEL_KPL, GSEL_APIC);
290 if ((resource_int_value("apic", 0, "clock", &i) != 0 || i != 0)) {
292 /* Intel CPUID 0x06 EAX[2] set if APIC timer runs in C3. */
293 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high >= 6) {
294 do_cpuid(0x06, regs);
295 if ((regs[0] & CPUTPM1_ARAT) != 0)
298 bzero(&lapic_et, sizeof(lapic_et));
299 lapic_et.et_name = "LAPIC";
300 lapic_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
302 lapic_et.et_quality = 600;
304 lapic_et.et_flags |= ET_FLAGS_C3STOP;
305 lapic_et.et_quality -= 200;
307 lapic_et.et_frequency = 0;
308 /* We don't know frequency yet, so trying to guess. */
309 lapic_et.et_min_period.sec = 0;
310 lapic_et.et_min_period.frac = 0x00001000LL << 32;
311 lapic_et.et_max_period.sec = 1;
312 lapic_et.et_max_period.frac = 0;
313 lapic_et.et_start = lapic_et_start;
314 lapic_et.et_stop = lapic_et_stop;
315 lapic_et.et_priv = NULL;
316 et_register(&lapic_et);
321 * Create a local APIC instance.
324 lapic_create(u_int apic_id, int boot_cpu)
328 if (apic_id > MAX_APIC_ID) {
329 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
331 panic("Can't ignore BSP");
334 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
338 * Assume no local LVT overrides and a cluster of 0 and
339 * intra-cluster ID of 0.
341 lapics[apic_id].la_present = 1;
342 lapics[apic_id].la_id = apic_id;
343 for (i = 0; i <= LVT_MAX; i++) {
344 lapics[apic_id].la_lvts[i] = lvts[i];
345 lapics[apic_id].la_lvts[i].lvt_active = 0;
347 for (i = 0; i <= APIC_NUM_IOINTS; i++)
348 lapics[apic_id].la_ioint_irqs[i] = -1;
349 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
350 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] =
353 lapics[apic_id].la_ioint_irqs[IDT_DTRACE_RET - APIC_IO_INTS] =
359 cpu_add(apic_id, boot_cpu);
364 * Dump contents of local APIC registers
367 lapic_dump(const char* str)
371 maxlvt = (lapic_version() & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
372 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
373 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
374 lapic_id(), lapic_version(), lapic_ldr(), lapic_dfr());
375 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
376 lapic_lvt_lint0(), lapic_lvt_lint1(), lapic_tpr(), lapic_svr());
377 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x",
378 lapic_lvt_timer(), lapic_lvt_thermal(), lapic_lvt_error());
379 if (maxlvt >= LVT_PMC)
380 printf(" pmc: 0x%08x", lapic_lvt_pcint());
382 if (maxlvt >= LVT_CMCI)
383 printf(" cmci: 0x%08x\n", lapic_lvt_cmci());
387 lapic_setup(int boot)
392 char buf[MAXCOMLEN + 1];
394 la = &lapics[lapic_id()];
395 KASSERT(la->la_present, ("missing APIC structure"));
396 saveintr = intr_disable();
397 maxlvt = (lapic_version() & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
399 /* Initialize the TPR to allow all interrupts. */
402 /* Setup spurious vector and enable the local APIC. */
405 /* Program LINT[01] LVT entries. */
406 lapic_set_lvt_lint0(lvt_mode(la, LVT_LINT0, lapic_lvt_lint0()));
407 lapic_set_lvt_lint1(lvt_mode(la, LVT_LINT1, lapic_lvt_lint1()));
409 /* Program the PMC LVT entry if present. */
410 if (maxlvt >= LVT_PMC)
411 lapic_set_lvt_pcint(lvt_mode(la, LVT_PMC, lapic_lvt_pcint()));
413 /* Program timer LVT and setup handler. */
414 la->lvt_timer_cache = lvt_mode(la, LVT_TIMER, lapic_lvt_timer());
415 lapic_set_lvt_timer(la->lvt_timer_cache);
417 snprintf(buf, sizeof(buf), "cpu%d:timer", PCPU_GET(cpuid));
418 intrcnt_add(buf, &la->la_timer_count);
421 /* Setup the timer if configured. */
422 if (la->la_timer_mode != 0) {
423 KASSERT(la->la_timer_period != 0, ("lapic%u: zero divisor",
425 lapic_timer_set_divisor(lapic_timer_divisor);
426 if (la->la_timer_mode == 1)
427 lapic_timer_periodic(la, la->la_timer_period, 1);
429 lapic_timer_oneshot(la, la->la_timer_period, 1);
432 /* Program error LVT and clear any existing errors. */
433 lapic_set_lvt_error(lvt_mode(la, LVT_ERROR, lapic_lvt_error()));
436 /* XXX: Thermal LVT */
438 /* Program the CMCI LVT entry if present. */
439 if (maxlvt >= LVT_CMCI)
440 lapic_set_lvt_cmci(lvt_mode(la, LVT_CMCI, lapic_lvt_cmci()));
442 intr_restore(saveintr);
446 lapic_reenable_pmc(void)
451 value = lapic_lvt_pcint();
452 value &= ~APIC_LVT_M;
453 lapic_set_lvt_pcint(value);
459 lapic_update_pmc(void *dummy)
463 la = &lapics[lapic_id()];
464 lapic_set_lvt_pcint(lvt_mode(la, LVT_PMC, lapic_lvt_pcint()));
469 lapic_enable_pmc(void)
474 /* Fail if the local APIC is not present. */
478 /* Fail if the PMC LVT is not present. */
479 maxlvt = (lapic_version() & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
480 if (maxlvt < LVT_PMC)
483 lvts[LVT_PMC].lvt_masked = 0;
487 * If hwpmc was loaded at boot time then the APs may not be
488 * started yet. In that case, don't forward the request to
489 * them as they will program the lvt when they start.
492 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
495 lapic_update_pmc(NULL);
503 lapic_disable_pmc(void)
508 /* Fail if the local APIC is not present. */
512 /* Fail if the PMC LVT is not present. */
513 maxlvt = (lapic_version() & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
514 if (maxlvt < LVT_PMC)
517 lvts[LVT_PMC].lvt_masked = 1;
520 /* The APs should always be started when hwpmc is unloaded. */
521 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early"));
523 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
528 lapic_et_start(struct eventtimer *et,
529 struct bintime *first, struct bintime *period)
534 la = &lapics[PCPU_GET(apic_id)];
535 if (et->et_frequency == 0) {
536 /* Start off with a divisor of 2 (power on reset default). */
537 lapic_timer_divisor = 2;
538 /* Try to calibrate the local APIC timer. */
540 lapic_timer_set_divisor(lapic_timer_divisor);
541 lapic_timer_oneshot(la, APIC_TIMER_MAX_COUNT, 0);
543 value = APIC_TIMER_MAX_COUNT - lapic_ccr_timer();
544 if (value != APIC_TIMER_MAX_COUNT)
546 lapic_timer_divisor <<= 1;
547 } while (lapic_timer_divisor <= 128);
548 if (lapic_timer_divisor > 128)
549 panic("lapic: Divisor too big");
551 printf("lapic: Divisor %lu, Frequency %lu Hz\n",
552 lapic_timer_divisor, value);
553 et->et_frequency = value;
554 et->et_min_period.sec = 0;
555 et->et_min_period.frac =
556 ((0x00000002LLU << 32) / et->et_frequency) << 32;
557 et->et_max_period.sec = 0xfffffffeLLU / et->et_frequency;
558 et->et_max_period.frac =
559 ((0xfffffffeLLU << 32) / et->et_frequency) << 32;
561 if (la->la_timer_mode == 0)
562 lapic_timer_set_divisor(lapic_timer_divisor);
563 if (period != NULL) {
564 la->la_timer_mode = 1;
565 la->la_timer_period =
566 (et->et_frequency * (period->frac >> 32)) >> 32;
567 if (period->sec != 0)
568 la->la_timer_period += et->et_frequency * period->sec;
569 lapic_timer_periodic(la, la->la_timer_period, 1);
571 la->la_timer_mode = 2;
572 la->la_timer_period =
573 (et->et_frequency * (first->frac >> 32)) >> 32;
575 la->la_timer_period += et->et_frequency * first->sec;
576 lapic_timer_oneshot(la, la->la_timer_period, 1);
582 lapic_et_stop(struct eventtimer *et)
584 struct lapic *la = &lapics[PCPU_GET(apic_id)];
586 la->la_timer_mode = 0;
587 lapic_timer_stop(la);
596 /* Software disable the local APIC. */
598 value &= ~APIC_SVR_SWEN;
599 lapic_set_svr(value);
607 /* Program the spurious vector to enable the local APIC. */
609 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
610 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
611 lapic_set_svr(value);
614 /* Reset the local APIC on the BSP during resume. */
616 lapic_resume(struct pic *pic)
627 return (rdmsr(MSR_APIC_VERSION));
629 return (lapic->version);
637 return (rdmsr(MSR_APIC_LDR));
647 return (0xffffffff); /* DFR not available in x2APIC mode */
653 lapic_lvt_lint0(void)
657 return (rdmsr(MSR_APIC_LVT_LINT0));
659 return (lapic->lvt_lint0);
663 lapic_set_lvt_lint0(uint32_t value)
667 wrmsr(MSR_APIC_LVT_LINT0, value);
669 lapic->lvt_lint0 = value;
673 lapic_lvt_lint1(void)
677 return (rdmsr(MSR_APIC_LVT_LINT1));
679 return (lapic->lvt_lint1);
683 lapic_set_lvt_lint1(uint32_t value)
687 wrmsr(MSR_APIC_LVT_LINT1, value);
689 lapic->lvt_lint1 = value;
697 return (rdmsr(MSR_APIC_TPR));
707 return (rdmsr(MSR_APIC_SVR));
713 lapic_set_svr(uint32_t value)
717 wrmsr(MSR_APIC_SVR, value);
723 lapic_lvt_timer(void)
727 return (rdmsr(MSR_APIC_LVT_TIMER));
729 return (lapic->lvt_timer);
733 lapic_set_lvt_timer(uint32_t value)
737 wrmsr(MSR_APIC_LVT_TIMER, value);
739 lapic->lvt_timer = value;
743 lapic_lvt_thermal(void)
747 return (rdmsr(MSR_APIC_LVT_THERMAL));
749 return (lapic->lvt_thermal);
753 lapic_lvt_error(void)
757 return (rdmsr(MSR_APIC_LVT_ERROR));
759 return (lapic->lvt_error);
763 lapic_set_lvt_error(uint32_t value)
767 wrmsr(MSR_APIC_LVT_ERROR, value);
769 lapic->lvt_error = value;
773 lapic_lvt_pcint(void)
777 return (rdmsr(MSR_APIC_LVT_PCINT));
779 return (lapic->lvt_pcint);
783 lapic_set_lvt_pcint(uint32_t value)
787 wrmsr(MSR_APIC_LVT_PCINT, value);
789 lapic->lvt_pcint = value;
797 return (rdmsr(MSR_APIC_LVT_CMCI));
799 return (lapic->lvt_cmci);
803 lapic_set_lvt_cmci(uint32_t value)
807 wrmsr(MSR_APIC_LVT_CMCI, value);
809 lapic->lvt_cmci = value;
817 return (rdmsr(MSR_APIC_ESR));
823 lapic_set_esr(uint32_t value)
827 wrmsr(MSR_APIC_ESR, value);
833 lapic_ccr_timer(void)
837 return (rdmsr(MSR_APIC_CCR_TIMER));
839 return (lapic->ccr_timer);
843 lapic_set_dcr_timer(uint32_t value)
847 wrmsr(MSR_APIC_DCR_TIMER, value);
849 lapic->dcr_timer = value;
853 lapic_set_icr_timer(uint32_t value)
857 wrmsr(MSR_APIC_ICR_TIMER, value);
859 lapic->icr_timer = value;
866 volatile uint32_t *regptr;
868 KASSERT(num >= 0 && num < 8, ("lapic_tmr: invalid num %d", num));
871 msr = MSR_APIC_TMR0 + num;
874 regptr = &lapic->tmr0;
875 return (regptr[num * 4]);
883 volatile uint32_t *regptr;
885 KASSERT(num >= 0 && num < 8, ("lapic_irr: invalid num %d", num));
888 msr = MSR_APIC_IRR0 + num;
891 regptr = &lapic->irr0;
892 return (regptr[num * 4]);
900 volatile uint32_t *regptr;
902 KASSERT(num >= 0 && num < 8, ("lapic_isr: invalid num %d", num));
905 msr = MSR_APIC_ISR0 + num;
908 regptr = &lapic->isr0;
909 return (regptr[num * 4]);
920 return (lapic->icr_lo);
930 return (lapic->icr_hi);
934 lapic_set_icr(uint64_t value)
938 wrmsr(MSR_APIC_ICR, value);
940 lapic->icr_hi = value >> 32;
941 lapic->icr_lo = value;
949 if (x2apic == 0 && lapic == NULL)
960 return (rdmsr(MSR_APIC_ID));
962 return (lapic->id >> APIC_ID_SHIFT);
966 lapic_intr_pending(u_int vector)
969 * The IRR registers are an array of 128-bit registers each of
970 * which only describes 32 interrupts in the low 32 bits.. Thus,
971 * we divide the vector by 32 to get the 128-bit index. We then
972 * multiply that index by 4 to get the equivalent index from
973 * treating the IRR as an array of 32-bit registers. Finally, we
974 * modulus the vector by 32 to determine the individual bit to
977 return (lapic_irr(vector / 32) & 1 << (vector % 32));
981 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
985 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
987 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
989 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
990 ("%s: intra cluster id %u too big", __func__, cluster_id));
991 la = &lapics[apic_id];
992 la->la_cluster = cluster;
993 la->la_cluster_id = cluster_id;
997 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
1002 if (apic_id == APIC_ID_ALL) {
1003 lvts[pin].lvt_masked = masked;
1007 KASSERT(lapics[apic_id].la_present,
1008 ("%s: missing APIC %u", __func__, apic_id));
1009 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
1010 lapics[apic_id].la_lvts[pin].lvt_active = 1;
1012 printf("lapic%u:", apic_id);
1015 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
1020 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
1026 if (apic_id == APIC_ID_ALL) {
1031 KASSERT(lapics[apic_id].la_present,
1032 ("%s: missing APIC %u", __func__, apic_id));
1033 lvt = &lapics[apic_id].la_lvts[pin];
1034 lvt->lvt_active = 1;
1036 printf("lapic%u:", apic_id);
1038 lvt->lvt_mode = mode;
1040 case APIC_LVT_DM_NMI:
1041 case APIC_LVT_DM_SMI:
1042 case APIC_LVT_DM_INIT:
1043 case APIC_LVT_DM_EXTINT:
1044 lvt->lvt_edgetrigger = 1;
1045 lvt->lvt_activehi = 1;
1046 if (mode == APIC_LVT_DM_EXTINT)
1047 lvt->lvt_masked = 1;
1049 lvt->lvt_masked = 0;
1052 panic("Unsupported delivery mode: 0x%x\n", mode);
1055 printf(" Routing ");
1057 case APIC_LVT_DM_NMI:
1060 case APIC_LVT_DM_SMI:
1063 case APIC_LVT_DM_INIT:
1066 case APIC_LVT_DM_EXTINT:
1070 printf(" -> LINT%u\n", pin);
1076 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
1079 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
1081 if (apic_id == APIC_ID_ALL) {
1082 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
1086 KASSERT(lapics[apic_id].la_present,
1087 ("%s: missing APIC %u", __func__, apic_id));
1088 lapics[apic_id].la_lvts[pin].lvt_active = 1;
1089 lapics[apic_id].la_lvts[pin].lvt_activehi =
1090 (pol == INTR_POLARITY_HIGH);
1092 printf("lapic%u:", apic_id);
1095 printf(" LINT%u polarity: %s\n", pin,
1096 pol == INTR_POLARITY_HIGH ? "high" : "low");
1101 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
1104 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
1106 if (apic_id == APIC_ID_ALL) {
1107 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
1111 KASSERT(lapics[apic_id].la_present,
1112 ("%s: missing APIC %u", __func__, apic_id));
1113 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
1114 (trigger == INTR_TRIGGER_EDGE);
1115 lapics[apic_id].la_lvts[pin].lvt_active = 1;
1117 printf("lapic%u:", apic_id);
1120 printf(" LINT%u trigger: %s\n", pin,
1121 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
1126 * Adjust the TPR of the current CPU so that it blocks all interrupts below
1127 * the passed in vector.
1130 lapic_set_tpr(u_int vector)
1134 wrmsr(MSR_APIC_TPR, vector);
1136 lapic->tpr = vector;
1140 tpr = lapic_tpr() & ~APIC_TPR_PRIO;
1143 wrmsr(MSR_APIC_TPR, tpr);
1154 wrmsr(MSR_APIC_EOI, 0);
1160 lapic_handle_intr(int vector, struct trapframe *frame)
1162 struct intsrc *isrc;
1164 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id),
1166 intr_execute_handlers(isrc, frame);
1170 lapic_handle_timer(struct trapframe *frame)
1173 struct trapframe *oldframe;
1176 /* Send EOI first thing. */
1179 #if defined(SMP) && !defined(SCHED_ULE)
1181 * Don't do any accounting for the disabled HTT cores, since it
1182 * will provide misleading numbers for the userland.
1184 * No locking is necessary here, since even if we loose the race
1185 * when hlt_cpus_mask changes it is not a big deal, really.
1187 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
1188 * and unlike other schedulers it actually schedules threads to
1191 if (CPU_ISSET(PCPU_GET(cpuid), &hlt_cpus_mask))
1195 /* Look up our local APIC structure for the tick counters. */
1196 la = &lapics[PCPU_GET(apic_id)];
1197 (*la->la_timer_count)++;
1199 if (lapic_et.et_active) {
1201 td->td_intr_nesting_level++;
1202 oldframe = td->td_intr_frame;
1203 td->td_intr_frame = frame;
1204 lapic_et.et_event_cb(&lapic_et, lapic_et.et_arg);
1205 td->td_intr_frame = oldframe;
1206 td->td_intr_nesting_level--;
1212 lapic_timer_set_divisor(u_int divisor)
1215 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
1216 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
1217 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
1218 lapic_set_dcr_timer(lapic_timer_divisors[ffs(divisor) - 1]);
1222 lapic_timer_oneshot(struct lapic *la, u_int count, int enable_int)
1226 value = la->lvt_timer_cache;
1227 value &= ~APIC_LVTT_TM;
1228 value |= APIC_LVTT_TM_ONE_SHOT;
1230 value &= ~APIC_LVT_M;
1231 lapic_set_lvt_timer(value);
1232 lapic_set_icr_timer(count);
1236 lapic_timer_periodic(struct lapic *la, u_int count, int enable_int)
1240 value = la->lvt_timer_cache;
1241 value &= ~APIC_LVTT_TM;
1242 value |= APIC_LVTT_TM_PERIODIC;
1244 value &= ~APIC_LVT_M;
1245 lapic_set_lvt_timer(value);
1246 lapic_set_icr_timer(count);
1250 lapic_timer_stop(struct lapic *la)
1254 value = la->lvt_timer_cache;
1255 value &= ~APIC_LVTT_TM;
1256 value |= APIC_LVT_M;
1257 lapic_set_lvt_timer(value);
1261 lapic_handle_cmc(void)
1269 * Called from the mca_init() to activate the CMC interrupt if this CPU is
1270 * responsible for monitoring any MC banks for CMC events. Since mca_init()
1271 * is called prior to lapic_setup() during boot, this just needs to unmask
1272 * this CPU's LVT_CMCI entry.
1275 lapic_enable_cmc(void)
1283 apic_id = PCPU_GET(apic_id);
1284 KASSERT(lapics[apic_id].la_present,
1285 ("%s: missing APIC %u", __func__, apic_id));
1286 lapics[apic_id].la_lvts[LVT_CMCI].lvt_masked = 0;
1287 lapics[apic_id].la_lvts[LVT_CMCI].lvt_active = 1;
1289 printf("lapic%u: CMCI unmasked\n", apic_id);
1293 lapic_handle_error(void)
1298 * Read the contents of the error status register. Write to
1299 * the register first before reading from it to force the APIC
1300 * to update its value to indicate any errors that have
1301 * occurred since the previous write to the register.
1306 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr);
1311 apic_cpuid(u_int apic_id)
1314 return apic_cpuids[apic_id];
1320 /* Request a free IDT vector to be used by the specified IRQ. */
1322 apic_alloc_vector(u_int apic_id, u_int irq)
1326 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
1329 * Search for a free vector. Currently we just use a very simple
1330 * algorithm to find the first free vector.
1332 mtx_lock_spin(&icu_lock);
1333 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
1334 if (lapics[apic_id].la_ioint_irqs[vector] != -1)
1336 lapics[apic_id].la_ioint_irqs[vector] = irq;
1337 mtx_unlock_spin(&icu_lock);
1338 return (vector + APIC_IO_INTS);
1340 mtx_unlock_spin(&icu_lock);
1345 * Request 'count' free contiguous IDT vectors to be used by 'count'
1346 * IRQs. 'count' must be a power of two and the vectors will be
1347 * aligned on a boundary of 'align'. If the request cannot be
1348 * satisfied, 0 is returned.
1351 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
1353 u_int first, run, vector;
1355 KASSERT(powerof2(count), ("bad count"));
1356 KASSERT(powerof2(align), ("bad align"));
1357 KASSERT(align >= count, ("align < count"));
1359 for (run = 0; run < count; run++)
1360 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
1365 * Search for 'count' free vectors. As with apic_alloc_vector(),
1366 * this just uses a simple first fit algorithm.
1370 mtx_lock_spin(&icu_lock);
1371 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
1373 /* Vector is in use, end run. */
1374 if (lapics[apic_id].la_ioint_irqs[vector] != -1) {
1380 /* Start a new run if run == 0 and vector is aligned. */
1382 if ((vector & (align - 1)) != 0)
1388 /* Keep looping if the run isn't long enough yet. */
1392 /* Found a run, assign IRQs and return the first vector. */
1393 for (vector = 0; vector < count; vector++)
1394 lapics[apic_id].la_ioint_irqs[first + vector] =
1396 mtx_unlock_spin(&icu_lock);
1397 return (first + APIC_IO_INTS);
1399 mtx_unlock_spin(&icu_lock);
1400 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
1405 * Enable a vector for a particular apic_id. Since all lapics share idt
1406 * entries and ioint_handlers this enables the vector on all lapics. lapics
1407 * which do not have the vector configured would report spurious interrupts
1411 apic_enable_vector(u_int apic_id, u_int vector)
1414 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1415 KASSERT(ioint_handlers[vector / 32] != NULL,
1416 ("No ISR handler for vector %u", vector));
1417 #ifdef KDTRACE_HOOKS
1418 KASSERT(vector != IDT_DTRACE_RET,
1419 ("Attempt to overwrite DTrace entry"));
1421 setidt(vector, ioint_handlers[vector / 32], SDT_APIC, SEL_KPL,
1426 apic_disable_vector(u_int apic_id, u_int vector)
1429 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1430 #ifdef KDTRACE_HOOKS
1431 KASSERT(vector != IDT_DTRACE_RET,
1432 ("Attempt to overwrite DTrace entry"));
1434 KASSERT(ioint_handlers[vector / 32] != NULL,
1435 ("No ISR handler for vector %u", vector));
1438 * We can not currently clear the idt entry because other cpus
1439 * may have a valid vector at this offset.
1441 setidt(vector, &IDTVEC(rsvd), SDT_APICT, SEL_KPL, GSEL_APIC);
1445 /* Release an APIC vector when it's no longer in use. */
1447 apic_free_vector(u_int apic_id, u_int vector, u_int irq)
1451 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1452 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1453 ("Vector %u does not map to an IRQ line", vector));
1454 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
1455 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] ==
1456 irq, ("IRQ mismatch"));
1457 #ifdef KDTRACE_HOOKS
1458 KASSERT(vector != IDT_DTRACE_RET,
1459 ("Attempt to overwrite DTrace entry"));
1463 * Bind us to the cpu that owned the vector before freeing it so
1464 * we don't lose an interrupt delivery race.
1469 if (sched_is_bound(td))
1470 panic("apic_free_vector: Thread already bound.\n");
1471 sched_bind(td, apic_cpuid(apic_id));
1474 mtx_lock_spin(&icu_lock);
1475 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1;
1476 mtx_unlock_spin(&icu_lock);
1484 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
1486 apic_idt_to_irq(u_int apic_id, u_int vector)
1490 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1491 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1492 ("Vector %u does not map to an IRQ line", vector));
1493 #ifdef KDTRACE_HOOKS
1494 KASSERT(vector != IDT_DTRACE_RET,
1495 ("Attempt to overwrite DTrace entry"));
1497 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS];
1505 * Dump data about APIC IDT vector mappings.
1507 DB_SHOW_COMMAND(apic, db_show_apic)
1509 struct intsrc *isrc;
1514 if (strcmp(modif, "vv") == 0)
1516 else if (strcmp(modif, "v") == 0)
1520 for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) {
1521 if (lapics[apic_id].la_present == 0)
1523 db_printf("Interrupts bound to lapic %u\n", apic_id);
1524 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
1525 irq = lapics[apic_id].la_ioint_irqs[i];
1526 if (irq == -1 || irq == IRQ_SYSCALL)
1528 #ifdef KDTRACE_HOOKS
1529 if (irq == IRQ_DTRACE_RET)
1532 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
1533 if (irq == IRQ_TIMER)
1534 db_printf("lapic timer\n");
1535 else if (irq < NUM_IO_INTS) {
1536 isrc = intr_lookup_source(irq);
1537 if (isrc == NULL || verbose == 0)
1538 db_printf("IRQ %u\n", irq);
1540 db_dump_intr_event(isrc->is_event,
1543 db_printf("IRQ %u ???\n", irq);
1549 dump_mask(const char *prefix, uint32_t v, int base)
1554 for (i = 0; i < 32; i++)
1557 db_printf("%s:", prefix);
1560 db_printf(" %02x", base + i);
1566 /* Show info from the lapic regs for this CPU. */
1567 DB_SHOW_COMMAND(lapic, db_show_lapic)
1571 db_printf("lapic ID = %d\n", lapic_id());
1572 v = lapic_version();
1573 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
1575 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
1577 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
1578 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
1579 db_printf("TPR = %02x\n", lapic_tpr());
1581 #define dump_field(prefix, index) \
1582 dump_mask(__XSTRING(prefix ## index), lapic_ ## prefix(index), \
1585 db_printf("In-service Interrupts:\n");
1595 db_printf("TMR Interrupts:\n");
1605 db_printf("IRR Interrupts:\n");
1620 * APIC probing support code. This includes code to manage enumerators.
1623 static SLIST_HEAD(, apic_enumerator) enumerators =
1624 SLIST_HEAD_INITIALIZER(enumerators);
1625 static struct apic_enumerator *best_enum;
1628 apic_register_enumerator(struct apic_enumerator *enumerator)
1631 struct apic_enumerator *apic_enum;
1633 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1634 if (apic_enum == enumerator)
1635 panic("%s: Duplicate register of %s", __func__,
1636 enumerator->apic_name);
1639 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1643 * We have to look for CPU's very, very early because certain subsystems
1644 * want to know how many CPU's we have extremely early on in the boot
1648 apic_init(void *dummy __unused)
1650 struct apic_enumerator *enumerator;
1656 /* We only support built in local APICs. */
1657 if (!(cpu_feature & CPUID_APIC))
1660 /* Don't probe if APIC mode is disabled. */
1661 if (resource_disabled("apic", 0))
1664 /* Probe all the enumerators to find the best match. */
1667 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1668 retval = enumerator->apic_probe();
1671 if (best_enum == NULL || best < retval) {
1672 best_enum = enumerator;
1676 if (best_enum == NULL) {
1678 printf("APIC: Could not find any APICs.\n");
1680 panic("running without device atpic requires a local APIC");
1686 printf("APIC: Using the %s enumerator.\n",
1687 best_enum->apic_name);
1691 * To work around an errata, we disable the local APIC on some
1692 * CPUs during early startup. We need to turn the local APIC back
1693 * on on such CPUs now.
1695 if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL &&
1696 (cpu_id & 0xff0) == 0x610) {
1697 apic_base = rdmsr(MSR_APICBASE);
1698 apic_base |= APICBASE_ENABLED;
1699 wrmsr(MSR_APICBASE, apic_base);
1703 /* Probe the CPU's in the system. */
1704 retval = best_enum->apic_probe_cpus();
1706 printf("%s: Failed to probe CPUs: returned %d\n",
1707 best_enum->apic_name, retval);
1710 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL);
1713 * Setup the local APIC. We have to do this prior to starting up the APs
1717 apic_setup_local(void *dummy __unused)
1721 if (best_enum == NULL)
1724 /* Initialize the local APIC. */
1725 retval = best_enum->apic_setup_local();
1727 printf("%s: Failed to setup the local APIC: returned %d\n",
1728 best_enum->apic_name, retval);
1730 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local, NULL);
1733 * Setup the I/O APICs.
1736 apic_setup_io(void *dummy __unused)
1740 if (best_enum == NULL)
1742 retval = best_enum->apic_setup_io();
1744 printf("%s: Failed to setup I/O APICs: returned %d\n",
1745 best_enum->apic_name, retval);
1751 * Finish setting up the local APIC on the BSP once we know how to
1752 * properly program the LINT pins.
1755 intr_register_pic(&lapic_pic);
1759 /* Enable the MSI "pic". */
1762 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL);
1766 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1767 * private to the MD code. The public interface for the rest of the
1768 * kernel is defined in mp_machdep.c.
1771 lapic_ipi_wait(int delay)
1776 * Wait delay loops for IPI to be sent. This is highly bogus
1777 * since this is sensitive to CPU clock speed. If delay is
1778 * -1, we wait forever.
1785 for (x = 0; x < delay; x += incr) {
1786 if ((lapic_icr_lo() & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1794 lapic_ipi_raw(register_t icrlo, u_int dest)
1796 register_t saveintr;
1799 /* XXX: Need more sanity checking of icrlo? */
1800 KASSERT(!lapic_missing(), ("%s called too early", __func__));
1801 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1802 ("%s: invalid dest field", __func__));
1803 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1804 ("%s: reserved bits set in ICR LO register", __func__));
1806 /* Set destination in ICR HI register if it is being used. */
1807 saveintr = intr_disable();
1808 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1812 hi = lapic_icr_hi();
1813 hi &= ~APIC_ID_MASK;
1814 hi |= dest << APIC_ID_SHIFT;
1819 /* Program the contents of the IPI and dispatch it. */
1820 lo = lapic_icr_lo();
1821 lo &= APIC_ICRLO_RESV_MASK;
1823 lapic_set_icr((uint64_t)hi << 32 | lo);
1824 intr_restore(saveintr);
1827 #define BEFORE_SPIN 1000000
1828 #ifdef DETECT_DEADLOCK
1829 #define AFTER_SPIN 1000
1833 lapic_ipi_vectored(u_int vector, int dest)
1835 register_t icrlo, destfield;
1837 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1838 ("%s: invalid vector %d", __func__, vector));
1840 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE;
1843 * IPI_STOP_HARD is just a "fake" vector used to send a NMI.
1844 * Use special rules regard NMI if passed, otherwise specify
1847 if (vector == IPI_STOP_HARD)
1848 icrlo |= APIC_DELMODE_NMI | APIC_LEVEL_ASSERT;
1850 icrlo |= vector | APIC_DELMODE_FIXED | APIC_LEVEL_DEASSERT;
1853 case APIC_IPI_DEST_SELF:
1854 icrlo |= APIC_DEST_SELF;
1856 case APIC_IPI_DEST_ALL:
1857 icrlo |= APIC_DEST_ALLISELF;
1859 case APIC_IPI_DEST_OTHERS:
1860 icrlo |= APIC_DEST_ALLESELF;
1863 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1864 ("%s: invalid destination 0x%x", __func__, dest));
1868 /* Wait for an earlier IPI to finish. */
1869 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1870 if (panicstr != NULL)
1873 panic("APIC: Previous IPI is stuck");
1876 lapic_ipi_raw(icrlo, destfield);
1878 #ifdef DETECT_DEADLOCK
1879 /* Wait for IPI to be delivered. */
1880 if (!lapic_ipi_wait(AFTER_SPIN)) {
1881 #ifdef needsattention
1885 * The above function waits for the message to actually be
1886 * delivered. It breaks out after an arbitrary timeout
1887 * since the message should eventually be delivered (at
1888 * least in theory) and that if it wasn't we would catch
1889 * the failure with the check above when the next IPI is
1892 * We could skip this wait entirely, EXCEPT it probably
1893 * protects us from other routines that assume that the
1894 * message was delivered and acted upon when this function
1897 printf("APIC: IPI might be stuck\n");
1898 #else /* !needsattention */
1899 /* Wait until mesage is sent without a timeout. */
1900 while (lapic_icr_lo() & APIC_DELSTAT_PEND)
1902 #endif /* needsattention */
1904 #endif /* DETECT_DEADLOCK */