2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Local APIC support on Pentium and later processors.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_atpic.h"
38 #include "opt_hwpmc_hooks.h"
42 #include <sys/param.h>
43 #include <sys/systm.h>
45 #include <sys/kernel.h>
47 #include <sys/mutex.h>
50 #include <sys/sched.h>
52 #include <sys/sysctl.h>
53 #include <sys/timeet.h>
58 #include <x86/apicreg.h>
59 #include <machine/cpufunc.h>
60 #include <machine/cputypes.h>
61 #include <machine/frame.h>
62 #include <machine/intr_machdep.h>
63 #include <x86/apicvar.h>
65 #include <machine/md_var.h>
66 #include <machine/smp.h>
67 #include <machine/specialreg.h>
71 #include <sys/interrupt.h>
76 #define SDT_APIC SDT_SYSIGT
77 #define SDT_APICT SDT_SYSIGT
80 #define SDT_APIC SDT_SYS386IGT
81 #define SDT_APICT SDT_SYS386TGT
82 #define GSEL_APIC GSEL(GCODE_SEL, SEL_KPL)
85 /* Sanity checks on IDT vectors. */
86 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
87 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
88 CTASSERT(APIC_LOCAL_INTS == 240);
89 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
91 /* Magic IRQ values for the timer and syscalls. */
92 #define IRQ_TIMER (NUM_IO_INTS + 1)
93 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
94 #define IRQ_DTRACE_RET (NUM_IO_INTS + 3)
95 #define IRQ_EVTCHN (NUM_IO_INTS + 4)
98 * Support for local APICs. Local APICs manage interrupts on each
99 * individual processor as opposed to I/O APICs which receive interrupts
100 * from I/O devices and then forward them on to the local APICs.
102 * Local APICs can also send interrupts to each other thus providing the
103 * mechanism for IPIs.
107 u_int lvt_edgetrigger:1;
108 u_int lvt_activehi:1;
116 struct lvt la_lvts[APIC_LVT_MAX + 1];
119 u_int la_cluster_id:2;
121 u_long *la_timer_count;
122 u_long la_timer_period;
124 uint32_t lvt_timer_cache;
125 /* Include IDT_SYSCALL to make indexing easier. */
126 int la_ioint_irqs[APIC_NUM_IOINTS + 1];
127 } static lapics[MAX_APIC_ID + 1];
129 /* Global defaults for local APIC LVT entries. */
130 static struct lvt lvts[APIC_LVT_MAX + 1] = {
131 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
132 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
133 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
134 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
135 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
136 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
137 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_CMC_INT }, /* CMCI */
140 static inthand_t *ioint_handlers[] = {
142 IDTVEC(apic_isr1), /* 32 - 63 */
143 IDTVEC(apic_isr2), /* 64 - 95 */
144 IDTVEC(apic_isr3), /* 96 - 127 */
145 IDTVEC(apic_isr4), /* 128 - 159 */
146 IDTVEC(apic_isr5), /* 160 - 191 */
147 IDTVEC(apic_isr6), /* 192 - 223 */
148 IDTVEC(apic_isr7), /* 224 - 255 */
152 static u_int32_t lapic_timer_divisors[] = {
153 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
154 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
157 extern inthand_t IDTVEC(rsvd);
159 volatile char *lapic_map;
160 vm_paddr_t lapic_paddr;
162 int lapic_eoi_suppression;
163 static u_long lapic_timer_divisor;
164 static struct eventtimer lapic_et;
166 SYSCTL_NODE(_hw, OID_AUTO, apic, CTLFLAG_RD, 0, "APIC options");
167 SYSCTL_INT(_hw_apic, OID_AUTO, x2apic_mode, CTLFLAG_RD, &x2apic_mode, 0, "");
168 SYSCTL_INT(_hw_apic, OID_AUTO, eoi_suppression, CTLFLAG_RD,
169 &lapic_eoi_suppression, 0, "");
172 lapic_read32(enum LAPIC_REGISTERS reg)
177 res = rdmsr32(MSR_APIC_000 + reg);
179 res = *(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL);
185 lapic_write32(enum LAPIC_REGISTERS reg, uint32_t val)
190 wrmsr(MSR_APIC_000 + reg, val);
192 *(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL) = val;
197 lapic_write32_nofence(enum LAPIC_REGISTERS reg, uint32_t val)
201 wrmsr(MSR_APIC_000 + reg, val);
203 *(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL) = val;
215 v = rdmsr(MSR_APIC_000 + LAPIC_ICR_LO);
217 vhi = lapic_read32(LAPIC_ICR_HI);
218 vlo = lapic_read32(LAPIC_ICR_LO);
219 v = ((uint64_t)vhi << 32) | vlo;
225 lapic_read_icr_lo(void)
228 return (lapic_read32(LAPIC_ICR_LO));
232 lapic_write_icr(uint32_t vhi, uint32_t vlo)
237 v = ((uint64_t)vhi << 32) | vlo;
239 wrmsr(MSR_APIC_000 + LAPIC_ICR_LO, v);
241 lapic_write32(LAPIC_ICR_HI, vhi);
242 lapic_write32(LAPIC_ICR_LO, vlo);
248 native_lapic_enable_x2apic(void)
252 apic_base = rdmsr(MSR_APICBASE);
253 apic_base |= APICBASE_X2APIC | APICBASE_ENABLED;
254 wrmsr(MSR_APICBASE, apic_base);
257 static void lapic_enable(void);
258 static void lapic_resume(struct pic *pic, bool suspend_cancelled);
259 static void lapic_timer_oneshot(struct lapic *,
260 u_int count, int enable_int);
261 static void lapic_timer_periodic(struct lapic *,
262 u_int count, int enable_int);
263 static void lapic_timer_stop(struct lapic *);
264 static void lapic_timer_set_divisor(u_int divisor);
265 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
266 static int lapic_et_start(struct eventtimer *et,
267 sbintime_t first, sbintime_t period);
268 static int lapic_et_stop(struct eventtimer *et);
269 static u_int apic_idt_to_irq(u_int apic_id, u_int vector);
270 static void lapic_set_tpr(u_int vector);
272 struct pic lapic_pic = { .pic_resume = lapic_resume };
274 /* Forward declarations for apic_ops */
275 static void native_lapic_create(u_int apic_id, int boot_cpu);
276 static void native_lapic_init(vm_paddr_t addr);
277 static void native_lapic_xapic_mode(void);
278 static void native_lapic_setup(int boot);
279 static void native_lapic_dump(const char *str);
280 static void native_lapic_disable(void);
281 static void native_lapic_eoi(void);
282 static int native_lapic_id(void);
283 static int native_lapic_intr_pending(u_int vector);
284 static u_int native_apic_cpuid(u_int apic_id);
285 static u_int native_apic_alloc_vector(u_int apic_id, u_int irq);
286 static u_int native_apic_alloc_vectors(u_int apic_id, u_int *irqs,
287 u_int count, u_int align);
288 static void native_apic_disable_vector(u_int apic_id, u_int vector);
289 static void native_apic_enable_vector(u_int apic_id, u_int vector);
290 static void native_apic_free_vector(u_int apic_id, u_int vector, u_int irq);
291 static void native_lapic_set_logical_id(u_int apic_id, u_int cluster,
293 static int native_lapic_enable_pmc(void);
294 static void native_lapic_disable_pmc(void);
295 static void native_lapic_reenable_pmc(void);
296 static void native_lapic_enable_cmc(void);
297 static int native_lapic_set_lvt_mask(u_int apic_id, u_int lvt,
299 static int native_lapic_set_lvt_mode(u_int apic_id, u_int lvt,
301 static int native_lapic_set_lvt_polarity(u_int apic_id, u_int lvt,
302 enum intr_polarity pol);
303 static int native_lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
304 enum intr_trigger trigger);
306 static void native_lapic_ipi_raw(register_t icrlo, u_int dest);
307 static void native_lapic_ipi_vectored(u_int vector, int dest);
308 static int native_lapic_ipi_wait(int delay);
309 static int native_lapic_ipi_alloc(inthand_t *ipifunc);
310 static void native_lapic_ipi_free(int vector);
313 struct apic_ops apic_ops = {
314 .create = native_lapic_create,
315 .init = native_lapic_init,
316 .xapic_mode = native_lapic_xapic_mode,
317 .setup = native_lapic_setup,
318 .dump = native_lapic_dump,
319 .disable = native_lapic_disable,
320 .eoi = native_lapic_eoi,
321 .id = native_lapic_id,
322 .intr_pending = native_lapic_intr_pending,
323 .set_logical_id = native_lapic_set_logical_id,
324 .cpuid = native_apic_cpuid,
325 .alloc_vector = native_apic_alloc_vector,
326 .alloc_vectors = native_apic_alloc_vectors,
327 .enable_vector = native_apic_enable_vector,
328 .disable_vector = native_apic_disable_vector,
329 .free_vector = native_apic_free_vector,
330 .enable_pmc = native_lapic_enable_pmc,
331 .disable_pmc = native_lapic_disable_pmc,
332 .reenable_pmc = native_lapic_reenable_pmc,
333 .enable_cmc = native_lapic_enable_cmc,
335 .ipi_raw = native_lapic_ipi_raw,
336 .ipi_vectored = native_lapic_ipi_vectored,
337 .ipi_wait = native_lapic_ipi_wait,
338 .ipi_alloc = native_lapic_ipi_alloc,
339 .ipi_free = native_lapic_ipi_free,
341 .set_lvt_mask = native_lapic_set_lvt_mask,
342 .set_lvt_mode = native_lapic_set_lvt_mode,
343 .set_lvt_polarity = native_lapic_set_lvt_polarity,
344 .set_lvt_triggermode = native_lapic_set_lvt_triggermode,
348 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
352 KASSERT(pin <= APIC_LVT_MAX, ("%s: pin %u out of range", __func__, pin));
353 if (la->la_lvts[pin].lvt_active)
354 lvt = &la->la_lvts[pin];
358 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
360 if (lvt->lvt_edgetrigger == 0)
361 value |= APIC_LVT_TM;
362 if (lvt->lvt_activehi == 0)
363 value |= APIC_LVT_IIPP_INTALO;
366 value |= lvt->lvt_mode;
367 switch (lvt->lvt_mode) {
368 case APIC_LVT_DM_NMI:
369 case APIC_LVT_DM_SMI:
370 case APIC_LVT_DM_INIT:
371 case APIC_LVT_DM_EXTINT:
372 if (!lvt->lvt_edgetrigger && bootverbose) {
373 printf("lapic%u: Forcing LINT%u to edge trigger\n",
375 value |= APIC_LVT_TM;
377 /* Use a vector of 0. */
379 case APIC_LVT_DM_FIXED:
380 value |= lvt->lvt_vector;
383 panic("bad APIC LVT delivery mode: %#x\n", value);
389 * Map the local APIC and setup necessary interrupt vectors.
392 native_lapic_init(vm_paddr_t addr)
399 * Enable x2APIC mode if possible. Map the local APIC
402 * Keep the LAPIC registers page mapped uncached for x2APIC
403 * mode too, to have direct map page attribute set to
404 * uncached. This is needed to work around CPU errata present
405 * on all Intel processors.
407 KASSERT(trunc_page(addr) == addr,
408 ("local APIC not aligned on a page boundary"));
410 lapic_map = pmap_mapdev(addr, PAGE_SIZE);
412 native_lapic_enable_x2apic();
416 /* Setup the spurious interrupt handler. */
417 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_APIC, SEL_KPL,
420 /* Perform basic initialization of the BSP's local APIC. */
423 /* Set BSP's per-CPU local APIC ID. */
424 PCPU_SET(apic_id, lapic_id());
426 /* Local APIC timer interrupt. */
427 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_APIC, SEL_KPL, GSEL_APIC);
429 /* Local APIC error interrupt. */
430 setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_APIC, SEL_KPL, GSEL_APIC);
432 /* XXX: Thermal interrupt */
434 /* Local APIC CMCI. */
435 setidt(APIC_CMC_INT, IDTVEC(cmcint), SDT_APICT, SEL_KPL, GSEL_APIC);
437 if ((resource_int_value("apic", 0, "clock", &i) != 0 || i != 0)) {
439 /* Intel CPUID 0x06 EAX[2] set if APIC timer runs in C3. */
440 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high >= 6) {
441 do_cpuid(0x06, regs);
442 if ((regs[0] & CPUTPM1_ARAT) != 0)
445 bzero(&lapic_et, sizeof(lapic_et));
446 lapic_et.et_name = "LAPIC";
447 lapic_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
449 lapic_et.et_quality = 600;
451 lapic_et.et_flags |= ET_FLAGS_C3STOP;
452 lapic_et.et_quality -= 200;
454 lapic_et.et_frequency = 0;
455 /* We don't know frequency yet, so trying to guess. */
456 lapic_et.et_min_period = 0x00001000LL;
457 lapic_et.et_max_period = SBT_1S;
458 lapic_et.et_start = lapic_et_start;
459 lapic_et.et_stop = lapic_et_stop;
460 lapic_et.et_priv = NULL;
461 et_register(&lapic_et);
465 * Set lapic_eoi_suppression after lapic_enable(), to not
466 * enable suppression in the hardware prematurely. Note that
467 * we by default enable suppression even when system only has
468 * one IO-APIC, since EOI is broadcasted to all APIC agents,
469 * including CPUs, otherwise.
471 * It seems that at least some KVM versions report
472 * EOI_SUPPRESSION bit, but auto-EOI does not work.
474 ver = lapic_read32(LAPIC_VERSION);
475 if ((ver & APIC_VER_EOI_SUPPRESSION) != 0) {
476 lapic_eoi_suppression = 1;
477 if (vm_guest == VM_GUEST_VM &&
478 !strcmp(hv_vendor, "KVMKVMKVM")) {
481 "KVM -- disabling lapic eoi suppression\n");
482 lapic_eoi_suppression = 0;
484 TUNABLE_INT_FETCH("hw.lapic_eoi_suppression",
485 &lapic_eoi_suppression);
490 * Create a local APIC instance.
493 native_lapic_create(u_int apic_id, int boot_cpu)
497 if (apic_id > MAX_APIC_ID) {
498 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
500 panic("Can't ignore BSP");
503 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
507 * Assume no local LVT overrides and a cluster of 0 and
508 * intra-cluster ID of 0.
510 lapics[apic_id].la_present = 1;
511 lapics[apic_id].la_id = apic_id;
512 for (i = 0; i <= APIC_LVT_MAX; i++) {
513 lapics[apic_id].la_lvts[i] = lvts[i];
514 lapics[apic_id].la_lvts[i].lvt_active = 0;
516 for (i = 0; i <= APIC_NUM_IOINTS; i++)
517 lapics[apic_id].la_ioint_irqs[i] = -1;
518 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
519 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] =
522 lapics[apic_id].la_ioint_irqs[IDT_DTRACE_RET - APIC_IO_INTS] =
526 lapics[apic_id].la_ioint_irqs[IDT_EVTCHN - APIC_IO_INTS] = IRQ_EVTCHN;
531 cpu_add(apic_id, boot_cpu);
536 * Dump contents of local APIC registers
539 native_lapic_dump(const char* str)
543 maxlvt = (lapic_read32(LAPIC_VERSION) & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
544 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
545 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x",
546 lapic_read32(LAPIC_ID), lapic_read32(LAPIC_VERSION),
547 lapic_read32(LAPIC_LDR), x2apic_mode ? 0 : lapic_read32(LAPIC_DFR));
548 if ((cpu_feature2 & CPUID2_X2APIC) != 0)
549 printf(" x2APIC: %d", x2apic_mode);
550 printf("\n lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
551 lapic_read32(LAPIC_LVT_LINT0), lapic_read32(LAPIC_LVT_LINT1),
552 lapic_read32(LAPIC_TPR), lapic_read32(LAPIC_SVR));
553 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x",
554 lapic_read32(LAPIC_LVT_TIMER), lapic_read32(LAPIC_LVT_THERMAL),
555 lapic_read32(LAPIC_LVT_ERROR));
556 if (maxlvt >= APIC_LVT_PMC)
557 printf(" pmc: 0x%08x", lapic_read32(LAPIC_LVT_PCINT));
559 if (maxlvt >= APIC_LVT_CMCI)
560 printf(" cmci: 0x%08x\n", lapic_read32(LAPIC_LVT_CMCI));
564 native_lapic_xapic_mode(void)
568 saveintr = intr_disable();
570 native_lapic_enable_x2apic();
571 intr_restore(saveintr);
575 native_lapic_setup(int boot)
580 char buf[MAXCOMLEN + 1];
582 saveintr = intr_disable();
584 la = &lapics[lapic_id()];
585 KASSERT(la->la_present, ("missing APIC structure"));
586 maxlvt = (lapic_read32(LAPIC_VERSION) & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
588 /* Initialize the TPR to allow all interrupts. */
591 /* Setup spurious vector and enable the local APIC. */
594 /* Program LINT[01] LVT entries. */
595 lapic_write32(LAPIC_LVT_LINT0, lvt_mode(la, APIC_LVT_LINT0,
596 lapic_read32(LAPIC_LVT_LINT0)));
597 lapic_write32(LAPIC_LVT_LINT1, lvt_mode(la, APIC_LVT_LINT1,
598 lapic_read32(LAPIC_LVT_LINT1)));
600 /* Program the PMC LVT entry if present. */
601 if (maxlvt >= APIC_LVT_PMC) {
602 lapic_write32(LAPIC_LVT_PCINT, lvt_mode(la, APIC_LVT_PMC,
606 /* Program timer LVT and setup handler. */
607 la->lvt_timer_cache = lvt_mode(la, APIC_LVT_TIMER,
608 lapic_read32(LAPIC_LVT_TIMER));
609 lapic_write32(LAPIC_LVT_TIMER, la->lvt_timer_cache);
611 snprintf(buf, sizeof(buf), "cpu%d:timer", PCPU_GET(cpuid));
612 intrcnt_add(buf, &la->la_timer_count);
615 /* Setup the timer if configured. */
616 if (la->la_timer_mode != 0) {
617 KASSERT(la->la_timer_period != 0, ("lapic%u: zero divisor",
619 lapic_timer_set_divisor(lapic_timer_divisor);
620 if (la->la_timer_mode == 1)
621 lapic_timer_periodic(la, la->la_timer_period, 1);
623 lapic_timer_oneshot(la, la->la_timer_period, 1);
626 /* Program error LVT and clear any existing errors. */
627 lapic_write32(LAPIC_LVT_ERROR, lvt_mode(la, APIC_LVT_ERROR,
628 lapic_read32(LAPIC_LVT_ERROR)));
629 lapic_write32(LAPIC_ESR, 0);
631 /* XXX: Thermal LVT */
633 /* Program the CMCI LVT entry if present. */
634 if (maxlvt >= APIC_LVT_CMCI) {
635 lapic_write32(LAPIC_LVT_CMCI, lvt_mode(la, APIC_LVT_CMCI,
636 lapic_read32(LAPIC_LVT_CMCI)));
639 intr_restore(saveintr);
643 native_lapic_reenable_pmc(void)
648 value = lapic_read32(LAPIC_LVT_PCINT);
649 value &= ~APIC_LVT_M;
650 lapic_write32(LAPIC_LVT_PCINT, value);
656 lapic_update_pmc(void *dummy)
660 la = &lapics[lapic_id()];
661 lapic_write32(LAPIC_LVT_PCINT, lvt_mode(la, APIC_LVT_PMC,
662 lapic_read32(LAPIC_LVT_PCINT)));
667 native_lapic_enable_pmc(void)
672 /* Fail if the local APIC is not present. */
673 if (!x2apic_mode && lapic_map == NULL)
676 /* Fail if the PMC LVT is not present. */
677 maxlvt = (lapic_read32(LAPIC_VERSION) & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
678 if (maxlvt < APIC_LVT_PMC)
681 lvts[APIC_LVT_PMC].lvt_masked = 0;
685 * If hwpmc was loaded at boot time then the APs may not be
686 * started yet. In that case, don't forward the request to
687 * them as they will program the lvt when they start.
690 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
693 lapic_update_pmc(NULL);
701 native_lapic_disable_pmc(void)
706 /* Fail if the local APIC is not present. */
707 if (!x2apic_mode && lapic_map == NULL)
710 /* Fail if the PMC LVT is not present. */
711 maxlvt = (lapic_read32(LAPIC_VERSION) & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
712 if (maxlvt < APIC_LVT_PMC)
715 lvts[APIC_LVT_PMC].lvt_masked = 1;
718 /* The APs should always be started when hwpmc is unloaded. */
719 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early"));
721 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
726 lapic_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
731 la = &lapics[PCPU_GET(apic_id)];
732 if (et->et_frequency == 0) {
733 /* Start off with a divisor of 2 (power on reset default). */
734 lapic_timer_divisor = 2;
735 /* Try to calibrate the local APIC timer. */
737 lapic_timer_set_divisor(lapic_timer_divisor);
738 lapic_timer_oneshot(la, APIC_TIMER_MAX_COUNT, 0);
740 value = APIC_TIMER_MAX_COUNT -
741 lapic_read32(LAPIC_CCR_TIMER);
742 if (value != APIC_TIMER_MAX_COUNT)
744 lapic_timer_divisor <<= 1;
745 } while (lapic_timer_divisor <= 128);
746 if (lapic_timer_divisor > 128)
747 panic("lapic: Divisor too big");
749 printf("lapic: Divisor %lu, Frequency %lu Hz\n",
750 lapic_timer_divisor, value);
751 et->et_frequency = value;
752 et->et_min_period = (0x00000002LLU << 32) / et->et_frequency;
753 et->et_max_period = (0xfffffffeLLU << 32) / et->et_frequency;
755 if (la->la_timer_mode == 0)
756 lapic_timer_set_divisor(lapic_timer_divisor);
758 la->la_timer_mode = 1;
759 la->la_timer_period = ((uint32_t)et->et_frequency * period) >> 32;
760 lapic_timer_periodic(la, la->la_timer_period, 1);
762 la->la_timer_mode = 2;
763 la->la_timer_period = ((uint32_t)et->et_frequency * first) >> 32;
764 lapic_timer_oneshot(la, la->la_timer_period, 1);
770 lapic_et_stop(struct eventtimer *et)
772 struct lapic *la = &lapics[PCPU_GET(apic_id)];
774 la->la_timer_mode = 0;
775 lapic_timer_stop(la);
780 native_lapic_disable(void)
784 /* Software disable the local APIC. */
785 value = lapic_read32(LAPIC_SVR);
786 value &= ~APIC_SVR_SWEN;
787 lapic_write32(LAPIC_SVR, value);
795 /* Program the spurious vector to enable the local APIC. */
796 value = lapic_read32(LAPIC_SVR);
797 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
798 value |= APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT;
799 if (lapic_eoi_suppression)
800 value |= APIC_SVR_EOI_SUPPRESSION;
801 lapic_write32(LAPIC_SVR, value);
804 /* Reset the local APIC on the BSP during resume. */
806 lapic_resume(struct pic *pic, bool suspend_cancelled)
813 native_lapic_id(void)
817 KASSERT(x2apic_mode || lapic_map != NULL, ("local APIC is not mapped"));
818 v = lapic_read32(LAPIC_ID);
825 native_lapic_intr_pending(u_int vector)
830 * The IRR registers are an array of registers each of which
831 * only describes 32 interrupts in the low 32 bits. Thus, we
832 * divide the vector by 32 to get the register index.
833 * Finally, we modulus the vector by 32 to determine the
834 * individual bit to test.
836 irr = lapic_read32(LAPIC_IRR0 + vector / 32);
837 return (irr & 1 << (vector % 32));
841 native_lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
845 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
847 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
849 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
850 ("%s: intra cluster id %u too big", __func__, cluster_id));
851 la = &lapics[apic_id];
852 la->la_cluster = cluster;
853 la->la_cluster_id = cluster_id;
857 native_lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
860 if (pin > APIC_LVT_MAX)
862 if (apic_id == APIC_ID_ALL) {
863 lvts[pin].lvt_masked = masked;
867 KASSERT(lapics[apic_id].la_present,
868 ("%s: missing APIC %u", __func__, apic_id));
869 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
870 lapics[apic_id].la_lvts[pin].lvt_active = 1;
872 printf("lapic%u:", apic_id);
875 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
880 native_lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
884 if (pin > APIC_LVT_MAX)
886 if (apic_id == APIC_ID_ALL) {
891 KASSERT(lapics[apic_id].la_present,
892 ("%s: missing APIC %u", __func__, apic_id));
893 lvt = &lapics[apic_id].la_lvts[pin];
896 printf("lapic%u:", apic_id);
898 lvt->lvt_mode = mode;
900 case APIC_LVT_DM_NMI:
901 case APIC_LVT_DM_SMI:
902 case APIC_LVT_DM_INIT:
903 case APIC_LVT_DM_EXTINT:
904 lvt->lvt_edgetrigger = 1;
905 lvt->lvt_activehi = 1;
906 if (mode == APIC_LVT_DM_EXTINT)
912 panic("Unsupported delivery mode: 0x%x\n", mode);
917 case APIC_LVT_DM_NMI:
920 case APIC_LVT_DM_SMI:
923 case APIC_LVT_DM_INIT:
926 case APIC_LVT_DM_EXTINT:
930 printf(" -> LINT%u\n", pin);
936 native_lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
939 if (pin > APIC_LVT_MAX || pol == INTR_POLARITY_CONFORM)
941 if (apic_id == APIC_ID_ALL) {
942 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
946 KASSERT(lapics[apic_id].la_present,
947 ("%s: missing APIC %u", __func__, apic_id));
948 lapics[apic_id].la_lvts[pin].lvt_active = 1;
949 lapics[apic_id].la_lvts[pin].lvt_activehi =
950 (pol == INTR_POLARITY_HIGH);
952 printf("lapic%u:", apic_id);
955 printf(" LINT%u polarity: %s\n", pin,
956 pol == INTR_POLARITY_HIGH ? "high" : "low");
961 native_lapic_set_lvt_triggermode(u_int apic_id, u_int pin,
962 enum intr_trigger trigger)
965 if (pin > APIC_LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
967 if (apic_id == APIC_ID_ALL) {
968 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
972 KASSERT(lapics[apic_id].la_present,
973 ("%s: missing APIC %u", __func__, apic_id));
974 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
975 (trigger == INTR_TRIGGER_EDGE);
976 lapics[apic_id].la_lvts[pin].lvt_active = 1;
978 printf("lapic%u:", apic_id);
981 printf(" LINT%u trigger: %s\n", pin,
982 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
987 * Adjust the TPR of the current CPU so that it blocks all interrupts below
988 * the passed in vector.
991 lapic_set_tpr(u_int vector)
994 lapic_write32(LAPIC_TPR, vector);
998 tpr = lapic_read32(LAPIC_TPR) & ~APIC_TPR_PRIO;
1000 lapic_write32(LAPIC_TPR, tpr);
1005 native_lapic_eoi(void)
1008 lapic_write32_nofence(LAPIC_EOI, 0);
1012 lapic_handle_intr(int vector, struct trapframe *frame)
1014 struct intsrc *isrc;
1016 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id),
1018 intr_execute_handlers(isrc, frame);
1022 lapic_handle_timer(struct trapframe *frame)
1025 struct trapframe *oldframe;
1028 /* Send EOI first thing. */
1031 #if defined(SMP) && !defined(SCHED_ULE)
1033 * Don't do any accounting for the disabled HTT cores, since it
1034 * will provide misleading numbers for the userland.
1036 * No locking is necessary here, since even if we lose the race
1037 * when hlt_cpus_mask changes it is not a big deal, really.
1039 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
1040 * and unlike other schedulers it actually schedules threads to
1043 if (CPU_ISSET(PCPU_GET(cpuid), &hlt_cpus_mask))
1047 /* Look up our local APIC structure for the tick counters. */
1048 la = &lapics[PCPU_GET(apic_id)];
1049 (*la->la_timer_count)++;
1051 if (lapic_et.et_active) {
1053 td->td_intr_nesting_level++;
1054 oldframe = td->td_intr_frame;
1055 td->td_intr_frame = frame;
1056 lapic_et.et_event_cb(&lapic_et, lapic_et.et_arg);
1057 td->td_intr_frame = oldframe;
1058 td->td_intr_nesting_level--;
1064 lapic_timer_set_divisor(u_int divisor)
1067 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
1068 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
1069 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
1070 lapic_write32(LAPIC_DCR_TIMER, lapic_timer_divisors[ffs(divisor) - 1]);
1074 lapic_timer_oneshot(struct lapic *la, u_int count, int enable_int)
1078 value = la->lvt_timer_cache;
1079 value &= ~APIC_LVTT_TM;
1080 value |= APIC_LVTT_TM_ONE_SHOT;
1082 value &= ~APIC_LVT_M;
1083 lapic_write32(LAPIC_LVT_TIMER, value);
1084 lapic_write32(LAPIC_ICR_TIMER, count);
1088 lapic_timer_periodic(struct lapic *la, u_int count, int enable_int)
1092 value = la->lvt_timer_cache;
1093 value &= ~APIC_LVTT_TM;
1094 value |= APIC_LVTT_TM_PERIODIC;
1096 value &= ~APIC_LVT_M;
1097 lapic_write32(LAPIC_LVT_TIMER, value);
1098 lapic_write32(LAPIC_ICR_TIMER, count);
1102 lapic_timer_stop(struct lapic *la)
1106 value = la->lvt_timer_cache;
1107 value &= ~APIC_LVTT_TM;
1108 value |= APIC_LVT_M;
1109 lapic_write32(LAPIC_LVT_TIMER, value);
1113 lapic_handle_cmc(void)
1121 * Called from the mca_init() to activate the CMC interrupt if this CPU is
1122 * responsible for monitoring any MC banks for CMC events. Since mca_init()
1123 * is called prior to lapic_setup() during boot, this just needs to unmask
1124 * this CPU's LVT_CMCI entry.
1127 native_lapic_enable_cmc(void)
1132 if (!x2apic_mode && lapic_map == NULL)
1135 apic_id = PCPU_GET(apic_id);
1136 KASSERT(lapics[apic_id].la_present,
1137 ("%s: missing APIC %u", __func__, apic_id));
1138 lapics[apic_id].la_lvts[APIC_LVT_CMCI].lvt_masked = 0;
1139 lapics[apic_id].la_lvts[APIC_LVT_CMCI].lvt_active = 1;
1141 printf("lapic%u: CMCI unmasked\n", apic_id);
1145 lapic_handle_error(void)
1150 * Read the contents of the error status register. Write to
1151 * the register first before reading from it to force the APIC
1152 * to update its value to indicate any errors that have
1153 * occurred since the previous write to the register.
1155 lapic_write32(LAPIC_ESR, 0);
1156 esr = lapic_read32(LAPIC_ESR);
1158 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr);
1163 native_apic_cpuid(u_int apic_id)
1166 return apic_cpuids[apic_id];
1172 /* Request a free IDT vector to be used by the specified IRQ. */
1174 native_apic_alloc_vector(u_int apic_id, u_int irq)
1178 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
1181 * Search for a free vector. Currently we just use a very simple
1182 * algorithm to find the first free vector.
1184 mtx_lock_spin(&icu_lock);
1185 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
1186 if (lapics[apic_id].la_ioint_irqs[vector] != -1)
1188 lapics[apic_id].la_ioint_irqs[vector] = irq;
1189 mtx_unlock_spin(&icu_lock);
1190 return (vector + APIC_IO_INTS);
1192 mtx_unlock_spin(&icu_lock);
1197 * Request 'count' free contiguous IDT vectors to be used by 'count'
1198 * IRQs. 'count' must be a power of two and the vectors will be
1199 * aligned on a boundary of 'align'. If the request cannot be
1200 * satisfied, 0 is returned.
1203 native_apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
1205 u_int first, run, vector;
1207 KASSERT(powerof2(count), ("bad count"));
1208 KASSERT(powerof2(align), ("bad align"));
1209 KASSERT(align >= count, ("align < count"));
1211 for (run = 0; run < count; run++)
1212 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
1217 * Search for 'count' free vectors. As with apic_alloc_vector(),
1218 * this just uses a simple first fit algorithm.
1222 mtx_lock_spin(&icu_lock);
1223 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
1225 /* Vector is in use, end run. */
1226 if (lapics[apic_id].la_ioint_irqs[vector] != -1) {
1232 /* Start a new run if run == 0 and vector is aligned. */
1234 if ((vector & (align - 1)) != 0)
1240 /* Keep looping if the run isn't long enough yet. */
1244 /* Found a run, assign IRQs and return the first vector. */
1245 for (vector = 0; vector < count; vector++)
1246 lapics[apic_id].la_ioint_irqs[first + vector] =
1248 mtx_unlock_spin(&icu_lock);
1249 return (first + APIC_IO_INTS);
1251 mtx_unlock_spin(&icu_lock);
1252 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
1257 * Enable a vector for a particular apic_id. Since all lapics share idt
1258 * entries and ioint_handlers this enables the vector on all lapics. lapics
1259 * which do not have the vector configured would report spurious interrupts
1263 native_apic_enable_vector(u_int apic_id, u_int vector)
1266 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1267 KASSERT(ioint_handlers[vector / 32] != NULL,
1268 ("No ISR handler for vector %u", vector));
1269 #ifdef KDTRACE_HOOKS
1270 KASSERT(vector != IDT_DTRACE_RET,
1271 ("Attempt to overwrite DTrace entry"));
1273 setidt(vector, ioint_handlers[vector / 32], SDT_APIC, SEL_KPL,
1278 native_apic_disable_vector(u_int apic_id, u_int vector)
1281 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1282 #ifdef KDTRACE_HOOKS
1283 KASSERT(vector != IDT_DTRACE_RET,
1284 ("Attempt to overwrite DTrace entry"));
1286 KASSERT(ioint_handlers[vector / 32] != NULL,
1287 ("No ISR handler for vector %u", vector));
1290 * We can not currently clear the idt entry because other cpus
1291 * may have a valid vector at this offset.
1293 setidt(vector, &IDTVEC(rsvd), SDT_APICT, SEL_KPL, GSEL_APIC);
1297 /* Release an APIC vector when it's no longer in use. */
1299 native_apic_free_vector(u_int apic_id, u_int vector, u_int irq)
1303 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1304 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1305 ("Vector %u does not map to an IRQ line", vector));
1306 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
1307 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] ==
1308 irq, ("IRQ mismatch"));
1309 #ifdef KDTRACE_HOOKS
1310 KASSERT(vector != IDT_DTRACE_RET,
1311 ("Attempt to overwrite DTrace entry"));
1315 * Bind us to the cpu that owned the vector before freeing it so
1316 * we don't lose an interrupt delivery race.
1321 if (sched_is_bound(td))
1322 panic("apic_free_vector: Thread already bound.\n");
1323 sched_bind(td, apic_cpuid(apic_id));
1326 mtx_lock_spin(&icu_lock);
1327 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1;
1328 mtx_unlock_spin(&icu_lock);
1336 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
1338 apic_idt_to_irq(u_int apic_id, u_int vector)
1342 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1343 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1344 ("Vector %u does not map to an IRQ line", vector));
1345 #ifdef KDTRACE_HOOKS
1346 KASSERT(vector != IDT_DTRACE_RET,
1347 ("Attempt to overwrite DTrace entry"));
1349 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS];
1357 * Dump data about APIC IDT vector mappings.
1359 DB_SHOW_COMMAND(apic, db_show_apic)
1361 struct intsrc *isrc;
1366 if (strcmp(modif, "vv") == 0)
1368 else if (strcmp(modif, "v") == 0)
1372 for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) {
1373 if (lapics[apic_id].la_present == 0)
1375 db_printf("Interrupts bound to lapic %u\n", apic_id);
1376 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
1377 irq = lapics[apic_id].la_ioint_irqs[i];
1378 if (irq == -1 || irq == IRQ_SYSCALL)
1380 #ifdef KDTRACE_HOOKS
1381 if (irq == IRQ_DTRACE_RET)
1385 if (irq == IRQ_EVTCHN)
1388 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
1389 if (irq == IRQ_TIMER)
1390 db_printf("lapic timer\n");
1391 else if (irq < NUM_IO_INTS) {
1392 isrc = intr_lookup_source(irq);
1393 if (isrc == NULL || verbose == 0)
1394 db_printf("IRQ %u\n", irq);
1396 db_dump_intr_event(isrc->is_event,
1399 db_printf("IRQ %u ???\n", irq);
1405 dump_mask(const char *prefix, uint32_t v, int base)
1410 for (i = 0; i < 32; i++)
1413 db_printf("%s:", prefix);
1416 db_printf(" %02x", base + i);
1422 /* Show info from the lapic regs for this CPU. */
1423 DB_SHOW_COMMAND(lapic, db_show_lapic)
1427 db_printf("lapic ID = %d\n", lapic_id());
1428 v = lapic_read32(LAPIC_VERSION);
1429 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
1431 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
1432 v = lapic_read32(LAPIC_SVR);
1433 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
1434 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
1435 db_printf("TPR = %02x\n", lapic_read32(LAPIC_TPR));
1437 #define dump_field(prefix, regn, index) \
1438 dump_mask(__XSTRING(prefix ## index), \
1439 lapic_read32(LAPIC_ ## regn ## index), \
1442 db_printf("In-service Interrupts:\n");
1443 dump_field(isr, ISR, 0);
1444 dump_field(isr, ISR, 1);
1445 dump_field(isr, ISR, 2);
1446 dump_field(isr, ISR, 3);
1447 dump_field(isr, ISR, 4);
1448 dump_field(isr, ISR, 5);
1449 dump_field(isr, ISR, 6);
1450 dump_field(isr, ISR, 7);
1452 db_printf("TMR Interrupts:\n");
1453 dump_field(tmr, TMR, 0);
1454 dump_field(tmr, TMR, 1);
1455 dump_field(tmr, TMR, 2);
1456 dump_field(tmr, TMR, 3);
1457 dump_field(tmr, TMR, 4);
1458 dump_field(tmr, TMR, 5);
1459 dump_field(tmr, TMR, 6);
1460 dump_field(tmr, TMR, 7);
1462 db_printf("IRR Interrupts:\n");
1463 dump_field(irr, IRR, 0);
1464 dump_field(irr, IRR, 1);
1465 dump_field(irr, IRR, 2);
1466 dump_field(irr, IRR, 3);
1467 dump_field(irr, IRR, 4);
1468 dump_field(irr, IRR, 5);
1469 dump_field(irr, IRR, 6);
1470 dump_field(irr, IRR, 7);
1477 * APIC probing support code. This includes code to manage enumerators.
1480 static SLIST_HEAD(, apic_enumerator) enumerators =
1481 SLIST_HEAD_INITIALIZER(enumerators);
1482 static struct apic_enumerator *best_enum;
1485 apic_register_enumerator(struct apic_enumerator *enumerator)
1488 struct apic_enumerator *apic_enum;
1490 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1491 if (apic_enum == enumerator)
1492 panic("%s: Duplicate register of %s", __func__,
1493 enumerator->apic_name);
1496 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1500 * We have to look for CPU's very, very early because certain subsystems
1501 * want to know how many CPU's we have extremely early on in the boot
1505 apic_init(void *dummy __unused)
1507 struct apic_enumerator *enumerator;
1510 /* We only support built in local APICs. */
1511 if (!(cpu_feature & CPUID_APIC))
1514 /* Don't probe if APIC mode is disabled. */
1515 if (resource_disabled("apic", 0))
1518 /* Probe all the enumerators to find the best match. */
1521 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1522 retval = enumerator->apic_probe();
1525 if (best_enum == NULL || best < retval) {
1526 best_enum = enumerator;
1530 if (best_enum == NULL) {
1532 printf("APIC: Could not find any APICs.\n");
1534 panic("running without device atpic requires a local APIC");
1540 printf("APIC: Using the %s enumerator.\n",
1541 best_enum->apic_name);
1545 * To work around an errata, we disable the local APIC on some
1546 * CPUs during early startup. We need to turn the local APIC back
1547 * on on such CPUs now.
1549 ppro_reenable_apic();
1552 /* Probe the CPU's in the system. */
1553 retval = best_enum->apic_probe_cpus();
1555 printf("%s: Failed to probe CPUs: returned %d\n",
1556 best_enum->apic_name, retval);
1559 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL);
1562 * Setup the local APIC. We have to do this prior to starting up the APs
1566 apic_setup_local(void *dummy __unused)
1570 if (best_enum == NULL)
1573 /* Initialize the local APIC. */
1574 retval = best_enum->apic_setup_local();
1576 printf("%s: Failed to setup the local APIC: returned %d\n",
1577 best_enum->apic_name, retval);
1579 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local, NULL);
1582 * Setup the I/O APICs.
1585 apic_setup_io(void *dummy __unused)
1589 if (best_enum == NULL)
1593 * Local APIC must be registered before other PICs and pseudo PICs
1594 * for proper suspend/resume order.
1596 intr_register_pic(&lapic_pic);
1598 retval = best_enum->apic_setup_io();
1600 printf("%s: Failed to setup I/O APICs: returned %d\n",
1601 best_enum->apic_name, retval);
1604 * Finish setting up the local APIC on the BSP once we know
1605 * how to properly program the LINT pins. In particular, this
1606 * enables the EOI suppression mode, if LAPIC support it and
1607 * user did not disabled the mode.
1613 /* Enable the MSI "pic". */
1614 init_ops.msi_init();
1616 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_THIRD, apic_setup_io, NULL);
1620 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1621 * private to the MD code. The public interface for the rest of the
1622 * kernel is defined in mp_machdep.c.
1625 native_lapic_ipi_wait(int delay)
1629 /* LAPIC_ICR.APIC_DELSTAT_MASK is undefined in x2APIC mode */
1634 * Wait delay microseconds for IPI to be sent. If delay is
1635 * -1, we wait forever.
1638 while ((lapic_read_icr_lo() & APIC_DELSTAT_MASK) !=
1644 for (x = 0; x < delay; x += 5) {
1645 if ((lapic_read_icr_lo() & APIC_DELSTAT_MASK) ==
1654 native_lapic_ipi_raw(register_t icrlo, u_int dest)
1658 register_t saveintr;
1660 /* XXX: Need more sanity checking of icrlo? */
1661 KASSERT(x2apic_mode || lapic_map != NULL,
1662 ("%s called too early", __func__));
1663 KASSERT(x2apic_mode ||
1664 (dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1665 ("%s: invalid dest field", __func__));
1666 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1667 ("%s: reserved bits set in ICR LO register", __func__));
1669 /* Set destination in ICR HI register if it is being used. */
1671 saveintr = intr_disable();
1672 icr = lapic_read_icr();
1675 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1680 vhi &= ~APIC_ID_MASK;
1681 vhi |= dest << APIC_ID_SHIFT;
1687 /* Program the contents of the IPI and dispatch it. */
1692 vlo &= APIC_ICRLO_RESV_MASK;
1695 lapic_write_icr(vhi, vlo);
1697 intr_restore(saveintr);
1700 #define BEFORE_SPIN 50000
1701 #ifdef DETECT_DEADLOCK
1702 #define AFTER_SPIN 50
1706 native_lapic_ipi_vectored(u_int vector, int dest)
1708 register_t icrlo, destfield;
1710 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1711 ("%s: invalid vector %d", __func__, vector));
1713 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE | APIC_LEVEL_ASSERT;
1716 * NMI IPIs are just fake vectors used to send a NMI. Use special rules
1717 * regarding NMIs if passed, otherwise specify the vector.
1719 if (vector >= IPI_NMI_FIRST)
1720 icrlo |= APIC_DELMODE_NMI;
1722 icrlo |= vector | APIC_DELMODE_FIXED;
1725 case APIC_IPI_DEST_SELF:
1726 icrlo |= APIC_DEST_SELF;
1728 case APIC_IPI_DEST_ALL:
1729 icrlo |= APIC_DEST_ALLISELF;
1731 case APIC_IPI_DEST_OTHERS:
1732 icrlo |= APIC_DEST_ALLESELF;
1735 KASSERT(x2apic_mode ||
1736 (dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1737 ("%s: invalid destination 0x%x", __func__, dest));
1741 /* Wait for an earlier IPI to finish. */
1742 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1743 if (panicstr != NULL)
1746 panic("APIC: Previous IPI is stuck");
1749 lapic_ipi_raw(icrlo, destfield);
1751 #ifdef DETECT_DEADLOCK
1752 /* Wait for IPI to be delivered. */
1753 if (!lapic_ipi_wait(AFTER_SPIN)) {
1754 #ifdef needsattention
1758 * The above function waits for the message to actually be
1759 * delivered. It breaks out after an arbitrary timeout
1760 * since the message should eventually be delivered (at
1761 * least in theory) and that if it wasn't we would catch
1762 * the failure with the check above when the next IPI is
1765 * We could skip this wait entirely, EXCEPT it probably
1766 * protects us from other routines that assume that the
1767 * message was delivered and acted upon when this function
1770 printf("APIC: IPI might be stuck\n");
1771 #else /* !needsattention */
1772 /* Wait until mesage is sent without a timeout. */
1773 while (lapic_read_icr_lo() & APIC_DELSTAT_PEND)
1775 #endif /* needsattention */
1777 #endif /* DETECT_DEADLOCK */
1781 * Since the IDT is shared by all CPUs the IPI slot update needs to be globally
1784 * Consider the case where an IPI is generated immediately after allocation:
1785 * vector = lapic_ipi_alloc(ipifunc);
1786 * ipi_selected(other_cpus, vector);
1788 * In xAPIC mode a write to ICR_LO has serializing semantics because the
1789 * APIC page is mapped as an uncached region. In x2APIC mode there is an
1790 * explicit 'mfence' before the ICR MSR is written. Therefore in both cases
1791 * the IDT slot update is globally visible before the IPI is delivered.
1794 native_lapic_ipi_alloc(inthand_t *ipifunc)
1796 struct gate_descriptor *ip;
1800 KASSERT(ipifunc != &IDTVEC(rsvd), ("invalid ipifunc %p", ipifunc));
1803 mtx_lock_spin(&icu_lock);
1804 for (idx = IPI_DYN_FIRST; idx <= IPI_DYN_LAST; idx++) {
1806 func = (ip->gd_hioffset << 16) | ip->gd_looffset;
1807 if (func == (uintptr_t)&IDTVEC(rsvd)) {
1809 setidt(vector, ipifunc, SDT_APIC, SEL_KPL, GSEL_APIC);
1813 mtx_unlock_spin(&icu_lock);
1818 native_lapic_ipi_free(int vector)
1820 struct gate_descriptor *ip;
1823 KASSERT(vector >= IPI_DYN_FIRST && vector <= IPI_DYN_LAST,
1824 ("%s: invalid vector %d", __func__, vector));
1826 mtx_lock_spin(&icu_lock);
1828 func = (ip->gd_hioffset << 16) | ip->gd_looffset;
1829 KASSERT(func != (uintptr_t)&IDTVEC(rsvd),
1830 ("invalid idtfunc %#lx", func));
1831 setidt(vector, &IDTVEC(rsvd), SDT_APICT, SEL_KPL, GSEL_APIC);
1832 mtx_unlock_spin(&icu_lock);