2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1996, by Steve Passe
6 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. The name of the developer may NOT be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 * 3. Neither the name of the author nor the names of any co-contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Local APIC support on Pentium and later processors.
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include "opt_atpic.h"
40 #include "opt_hwpmc_hooks.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/kernel.h>
49 #include <sys/malloc.h>
50 #include <sys/mutex.h>
53 #include <sys/sched.h>
55 #include <sys/sysctl.h>
56 #include <sys/timeet.h>
61 #include <x86/apicreg.h>
62 #include <machine/clock.h>
63 #include <machine/cpufunc.h>
64 #include <machine/cputypes.h>
65 #include <machine/frame.h>
66 #include <machine/intr_machdep.h>
67 #include <x86/apicvar.h>
69 #include <machine/md_var.h>
70 #include <machine/smp.h>
71 #include <machine/specialreg.h>
75 #include <sys/interrupt.h>
80 #define SDT_APIC SDT_SYSIGT
83 #define SDT_APIC SDT_SYS386IGT
84 #define GSEL_APIC GSEL(GCODE_SEL, SEL_KPL)
87 static MALLOC_DEFINE(M_LAPIC, "local_apic", "Local APIC items");
89 /* Sanity checks on IDT vectors. */
90 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
91 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
92 CTASSERT(APIC_LOCAL_INTS == 240);
93 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
96 * I/O interrupts use non-negative IRQ values. These values are used
97 * to mark unused IDT entries or IDT entries reserved for a non-I/O
102 #define IRQ_SYSCALL -3
103 #define IRQ_DTRACE_RET -4
104 #define IRQ_EVTCHN -5
106 enum lat_timer_mode {
108 LAT_MODE_PERIODIC = 1,
109 LAT_MODE_ONESHOT = 2,
110 LAT_MODE_DEADLINE = 3,
114 * Support for local APICs. Local APICs manage interrupts on each
115 * individual processor as opposed to I/O APICs which receive interrupts
116 * from I/O devices and then forward them on to the local APICs.
118 * Local APICs can also send interrupts to each other thus providing the
119 * mechanism for IPIs.
123 u_int lvt_edgetrigger:1;
124 u_int lvt_activehi:1;
132 struct lvt la_lvts[APIC_LVT_MAX + 1];
133 struct lvt la_elvts[APIC_ELVT_MAX + 1];
136 u_int la_cluster_id:2;
138 u_long *la_timer_count;
139 uint64_t la_timer_period;
140 enum lat_timer_mode la_timer_mode;
141 uint32_t lvt_timer_base;
142 uint32_t lvt_timer_last;
143 /* Include IDT_SYSCALL to make indexing easier. */
144 int la_ioint_irqs[APIC_NUM_IOINTS + 1];
147 /* Global defaults for local APIC LVT entries. */
148 static struct lvt lvts[APIC_LVT_MAX + 1] = {
149 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
150 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
151 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
152 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
153 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
154 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
155 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_CMC_INT }, /* CMCI */
158 /* Global defaults for AMD local APIC ELVT entries. */
159 static struct lvt elvts[APIC_ELVT_MAX + 1] = {
160 { 1, 1, 1, 0, APIC_LVT_DM_FIXED, 0 },
161 { 1, 1, 1, 0, APIC_LVT_DM_FIXED, APIC_CMC_INT },
162 { 1, 1, 1, 0, APIC_LVT_DM_FIXED, 0 },
163 { 1, 1, 1, 0, APIC_LVT_DM_FIXED, 0 },
166 static inthand_t *ioint_handlers[] = {
168 IDTVEC(apic_isr1), /* 32 - 63 */
169 IDTVEC(apic_isr2), /* 64 - 95 */
170 IDTVEC(apic_isr3), /* 96 - 127 */
171 IDTVEC(apic_isr4), /* 128 - 159 */
172 IDTVEC(apic_isr5), /* 160 - 191 */
173 IDTVEC(apic_isr6), /* 192 - 223 */
174 IDTVEC(apic_isr7), /* 224 - 255 */
177 static inthand_t *ioint_pti_handlers[] = {
179 IDTVEC(apic_isr1_pti), /* 32 - 63 */
180 IDTVEC(apic_isr2_pti), /* 64 - 95 */
181 IDTVEC(apic_isr3_pti), /* 96 - 127 */
182 IDTVEC(apic_isr4_pti), /* 128 - 159 */
183 IDTVEC(apic_isr5_pti), /* 160 - 191 */
184 IDTVEC(apic_isr6_pti), /* 192 - 223 */
185 IDTVEC(apic_isr7_pti), /* 224 - 255 */
188 static u_int32_t lapic_timer_divisors[] = {
189 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
190 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
193 extern inthand_t IDTVEC(rsvd_pti), IDTVEC(rsvd);
195 volatile char *lapic_map;
196 vm_paddr_t lapic_paddr;
198 int lapic_eoi_suppression;
199 static int lapic_timer_tsc_deadline;
200 static u_long lapic_timer_divisor, count_freq;
201 static struct eventtimer lapic_et;
203 static uint64_t lapic_ipi_wait_mult;
205 unsigned int max_apic_id;
207 SYSCTL_NODE(_hw, OID_AUTO, apic, CTLFLAG_RD, 0, "APIC options");
208 SYSCTL_INT(_hw_apic, OID_AUTO, x2apic_mode, CTLFLAG_RD, &x2apic_mode, 0, "");
209 SYSCTL_INT(_hw_apic, OID_AUTO, eoi_suppression, CTLFLAG_RD,
210 &lapic_eoi_suppression, 0, "");
211 SYSCTL_INT(_hw_apic, OID_AUTO, timer_tsc_deadline, CTLFLAG_RD,
212 &lapic_timer_tsc_deadline, 0, "");
214 static void lapic_calibrate_initcount(struct lapic *la);
215 static void lapic_calibrate_deadline(struct lapic *la);
218 lapic_read32(enum LAPIC_REGISTERS reg)
223 res = rdmsr32(MSR_APIC_000 + reg);
225 res = *(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL);
231 lapic_write32(enum LAPIC_REGISTERS reg, uint32_t val)
237 wrmsr(MSR_APIC_000 + reg, val);
239 *(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL) = val;
244 lapic_write32_nofence(enum LAPIC_REGISTERS reg, uint32_t val)
248 wrmsr(MSR_APIC_000 + reg, val);
250 *(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL) = val;
262 v = rdmsr(MSR_APIC_000 + LAPIC_ICR_LO);
264 vhi = lapic_read32(LAPIC_ICR_HI);
265 vlo = lapic_read32(LAPIC_ICR_LO);
266 v = ((uint64_t)vhi << 32) | vlo;
272 lapic_read_icr_lo(void)
275 return (lapic_read32(LAPIC_ICR_LO));
279 lapic_write_icr(uint32_t vhi, uint32_t vlo)
284 v = ((uint64_t)vhi << 32) | vlo;
286 wrmsr(MSR_APIC_000 + LAPIC_ICR_LO, v);
288 lapic_write32(LAPIC_ICR_HI, vhi);
289 lapic_write32(LAPIC_ICR_LO, vlo);
295 native_lapic_enable_x2apic(void)
299 apic_base = rdmsr(MSR_APICBASE);
300 apic_base |= APICBASE_X2APIC | APICBASE_ENABLED;
301 wrmsr(MSR_APICBASE, apic_base);
305 native_lapic_is_x2apic(void)
309 apic_base = rdmsr(MSR_APICBASE);
310 return ((apic_base & (APICBASE_X2APIC | APICBASE_ENABLED)) ==
311 (APICBASE_X2APIC | APICBASE_ENABLED));
314 static void lapic_enable(void);
315 static void lapic_resume(struct pic *pic, bool suspend_cancelled);
316 static void lapic_timer_oneshot(struct lapic *);
317 static void lapic_timer_oneshot_nointr(struct lapic *, uint32_t);
318 static void lapic_timer_periodic(struct lapic *);
319 static void lapic_timer_deadline(struct lapic *);
320 static void lapic_timer_stop(struct lapic *);
321 static void lapic_timer_set_divisor(u_int divisor);
322 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
323 static int lapic_et_start(struct eventtimer *et,
324 sbintime_t first, sbintime_t period);
325 static int lapic_et_stop(struct eventtimer *et);
326 static u_int apic_idt_to_irq(u_int apic_id, u_int vector);
327 static void lapic_set_tpr(u_int vector);
329 struct pic lapic_pic = { .pic_resume = lapic_resume };
331 /* Forward declarations for apic_ops */
332 static void native_lapic_create(u_int apic_id, int boot_cpu);
333 static void native_lapic_init(vm_paddr_t addr);
334 static void native_lapic_xapic_mode(void);
335 static void native_lapic_setup(int boot);
336 static void native_lapic_dump(const char *str);
337 static void native_lapic_disable(void);
338 static void native_lapic_eoi(void);
339 static int native_lapic_id(void);
340 static int native_lapic_intr_pending(u_int vector);
341 static u_int native_apic_cpuid(u_int apic_id);
342 static u_int native_apic_alloc_vector(u_int apic_id, u_int irq);
343 static u_int native_apic_alloc_vectors(u_int apic_id, u_int *irqs,
344 u_int count, u_int align);
345 static void native_apic_disable_vector(u_int apic_id, u_int vector);
346 static void native_apic_enable_vector(u_int apic_id, u_int vector);
347 static void native_apic_free_vector(u_int apic_id, u_int vector, u_int irq);
348 static void native_lapic_set_logical_id(u_int apic_id, u_int cluster,
350 static int native_lapic_enable_pmc(void);
351 static void native_lapic_disable_pmc(void);
352 static void native_lapic_reenable_pmc(void);
353 static void native_lapic_enable_cmc(void);
354 static int native_lapic_enable_mca_elvt(void);
355 static int native_lapic_set_lvt_mask(u_int apic_id, u_int lvt,
357 static int native_lapic_set_lvt_mode(u_int apic_id, u_int lvt,
359 static int native_lapic_set_lvt_polarity(u_int apic_id, u_int lvt,
360 enum intr_polarity pol);
361 static int native_lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
362 enum intr_trigger trigger);
364 static void native_lapic_ipi_raw(register_t icrlo, u_int dest);
365 static void native_lapic_ipi_vectored(u_int vector, int dest);
366 static int native_lapic_ipi_wait(int delay);
368 static int native_lapic_ipi_alloc(inthand_t *ipifunc);
369 static void native_lapic_ipi_free(int vector);
371 struct apic_ops apic_ops = {
372 .create = native_lapic_create,
373 .init = native_lapic_init,
374 .xapic_mode = native_lapic_xapic_mode,
375 .is_x2apic = native_lapic_is_x2apic,
376 .setup = native_lapic_setup,
377 .dump = native_lapic_dump,
378 .disable = native_lapic_disable,
379 .eoi = native_lapic_eoi,
380 .id = native_lapic_id,
381 .intr_pending = native_lapic_intr_pending,
382 .set_logical_id = native_lapic_set_logical_id,
383 .cpuid = native_apic_cpuid,
384 .alloc_vector = native_apic_alloc_vector,
385 .alloc_vectors = native_apic_alloc_vectors,
386 .enable_vector = native_apic_enable_vector,
387 .disable_vector = native_apic_disable_vector,
388 .free_vector = native_apic_free_vector,
389 .enable_pmc = native_lapic_enable_pmc,
390 .disable_pmc = native_lapic_disable_pmc,
391 .reenable_pmc = native_lapic_reenable_pmc,
392 .enable_cmc = native_lapic_enable_cmc,
393 .enable_mca_elvt = native_lapic_enable_mca_elvt,
395 .ipi_raw = native_lapic_ipi_raw,
396 .ipi_vectored = native_lapic_ipi_vectored,
397 .ipi_wait = native_lapic_ipi_wait,
399 .ipi_alloc = native_lapic_ipi_alloc,
400 .ipi_free = native_lapic_ipi_free,
401 .set_lvt_mask = native_lapic_set_lvt_mask,
402 .set_lvt_mode = native_lapic_set_lvt_mode,
403 .set_lvt_polarity = native_lapic_set_lvt_polarity,
404 .set_lvt_triggermode = native_lapic_set_lvt_triggermode,
408 lvt_mode_impl(struct lapic *la, struct lvt *lvt, u_int pin, uint32_t value)
411 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
413 if (lvt->lvt_edgetrigger == 0)
414 value |= APIC_LVT_TM;
415 if (lvt->lvt_activehi == 0)
416 value |= APIC_LVT_IIPP_INTALO;
419 value |= lvt->lvt_mode;
420 switch (lvt->lvt_mode) {
421 case APIC_LVT_DM_NMI:
422 case APIC_LVT_DM_SMI:
423 case APIC_LVT_DM_INIT:
424 case APIC_LVT_DM_EXTINT:
425 if (!lvt->lvt_edgetrigger && bootverbose) {
426 printf("lapic%u: Forcing LINT%u to edge trigger\n",
428 value &= ~APIC_LVT_TM;
430 /* Use a vector of 0. */
432 case APIC_LVT_DM_FIXED:
433 value |= lvt->lvt_vector;
436 panic("bad APIC LVT delivery mode: %#x\n", value);
442 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
446 KASSERT(pin <= APIC_LVT_MAX,
447 ("%s: pin %u out of range", __func__, pin));
448 if (la->la_lvts[pin].lvt_active)
449 lvt = &la->la_lvts[pin];
453 return (lvt_mode_impl(la, lvt, pin, value));
457 elvt_mode(struct lapic *la, u_int idx, uint32_t value)
461 KASSERT(idx <= APIC_ELVT_MAX,
462 ("%s: idx %u out of range", __func__, idx));
464 elvt = &la->la_elvts[idx];
465 KASSERT(elvt->lvt_active, ("%s: ELVT%u is not active", __func__, idx));
466 KASSERT(elvt->lvt_edgetrigger,
467 ("%s: ELVT%u is not edge triggered", __func__, idx));
468 KASSERT(elvt->lvt_activehi,
469 ("%s: ELVT%u is not active high", __func__, idx));
470 return (lvt_mode_impl(la, elvt, idx, value));
474 * Map the local APIC and setup necessary interrupt vectors.
477 native_lapic_init(vm_paddr_t addr)
480 uint64_t r, r1, r2, rx;
487 * Enable x2APIC mode if possible. Map the local APIC
490 * Keep the LAPIC registers page mapped uncached for x2APIC
491 * mode too, to have direct map page attribute set to
492 * uncached. This is needed to work around CPU errata present
493 * on all Intel processors.
495 KASSERT(trunc_page(addr) == addr,
496 ("local APIC not aligned on a page boundary"));
498 lapic_map = pmap_mapdev(addr, PAGE_SIZE);
500 native_lapic_enable_x2apic();
504 /* Setup the spurious interrupt handler. */
505 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_APIC, SEL_KPL,
508 /* Perform basic initialization of the BSP's local APIC. */
511 /* Set BSP's per-CPU local APIC ID. */
512 PCPU_SET(apic_id, lapic_id());
514 /* Local APIC timer interrupt. */
515 setidt(APIC_TIMER_INT, pti ? IDTVEC(timerint_pti) : IDTVEC(timerint),
516 SDT_APIC, SEL_KPL, GSEL_APIC);
518 /* Local APIC error interrupt. */
519 setidt(APIC_ERROR_INT, pti ? IDTVEC(errorint_pti) : IDTVEC(errorint),
520 SDT_APIC, SEL_KPL, GSEL_APIC);
522 /* XXX: Thermal interrupt */
524 /* Local APIC CMCI. */
525 setidt(APIC_CMC_INT, pti ? IDTVEC(cmcint_pti) : IDTVEC(cmcint),
526 SDT_APIC, SEL_KPL, GSEL_APIC);
528 if ((resource_int_value("apic", 0, "clock", &i) != 0 || i != 0)) {
530 /* Intel CPUID 0x06 EAX[2] set if APIC timer runs in C3. */
531 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high >= 6) {
532 do_cpuid(0x06, regs);
533 if ((regs[0] & CPUTPM1_ARAT) != 0)
535 } else if (cpu_vendor_id == CPU_VENDOR_AMD &&
536 CPUID_TO_FAMILY(cpu_id) >= 0x12) {
539 bzero(&lapic_et, sizeof(lapic_et));
540 lapic_et.et_name = "LAPIC";
541 lapic_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
543 lapic_et.et_quality = 600;
545 lapic_et.et_flags |= ET_FLAGS_C3STOP;
546 lapic_et.et_quality = 100;
548 if ((cpu_feature & CPUID_TSC) != 0 &&
549 (cpu_feature2 & CPUID2_TSCDLT) != 0 &&
550 tsc_is_invariant && tsc_freq != 0) {
551 lapic_timer_tsc_deadline = 1;
552 TUNABLE_INT_FETCH("hw.lapic_tsc_deadline",
553 &lapic_timer_tsc_deadline);
556 lapic_et.et_frequency = 0;
557 /* We don't know frequency yet, so trying to guess. */
558 lapic_et.et_min_period = 0x00001000LL;
559 lapic_et.et_max_period = SBT_1S;
560 lapic_et.et_start = lapic_et_start;
561 lapic_et.et_stop = lapic_et_stop;
562 lapic_et.et_priv = NULL;
563 et_register(&lapic_et);
567 * Set lapic_eoi_suppression after lapic_enable(), to not
568 * enable suppression in the hardware prematurely. Note that
569 * we by default enable suppression even when system only has
570 * one IO-APIC, since EOI is broadcasted to all APIC agents,
571 * including CPUs, otherwise.
573 * It seems that at least some KVM versions report
574 * EOI_SUPPRESSION bit, but auto-EOI does not work.
576 ver = lapic_read32(LAPIC_VERSION);
577 if ((ver & APIC_VER_EOI_SUPPRESSION) != 0) {
578 lapic_eoi_suppression = 1;
579 if (vm_guest == VM_GUEST_KVM) {
582 "KVM -- disabling lapic eoi suppression\n");
583 lapic_eoi_suppression = 0;
585 TUNABLE_INT_FETCH("hw.lapic_eoi_suppression",
586 &lapic_eoi_suppression);
592 * Calibrate the busy loop waiting for IPI ack in xAPIC mode.
593 * lapic_ipi_wait_mult contains the number of iterations which
594 * approximately delay execution for 1 microsecond (the
595 * argument to native_lapic_ipi_wait() is in microseconds).
597 * We assume that TSC is present and already measured.
598 * Possible TSC frequency jumps are irrelevant to the
599 * calibration loop below, the CPU clock management code is
600 * not yet started, and we do not enter sleep states.
602 KASSERT((cpu_feature & CPUID_TSC) != 0 && tsc_freq != 0,
603 ("TSC not initialized"));
606 for (rx = 0; rx < LOOPS; rx++) {
607 (void)lapic_read_icr_lo();
611 r1 = tsc_freq * LOOPS;
613 lapic_ipi_wait_mult = r1 >= r2 ? r1 / r2 : 1;
615 printf("LAPIC: ipi_wait() us multiplier %ju (r %ju "
616 "tsc %ju)\n", (uintmax_t)lapic_ipi_wait_mult,
617 (uintmax_t)r, (uintmax_t)tsc_freq);
625 * Create a local APIC instance.
628 native_lapic_create(u_int apic_id, int boot_cpu)
632 if (apic_id > max_apic_id) {
633 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
635 panic("Can't ignore BSP");
638 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
642 * Assume no local LVT overrides and a cluster of 0 and
643 * intra-cluster ID of 0.
645 lapics[apic_id].la_present = 1;
646 lapics[apic_id].la_id = apic_id;
647 for (i = 0; i <= APIC_LVT_MAX; i++) {
648 lapics[apic_id].la_lvts[i] = lvts[i];
649 lapics[apic_id].la_lvts[i].lvt_active = 0;
651 for (i = 0; i <= APIC_ELVT_MAX; i++) {
652 lapics[apic_id].la_elvts[i] = elvts[i];
653 lapics[apic_id].la_elvts[i].lvt_active = 0;
655 for (i = 0; i <= APIC_NUM_IOINTS; i++)
656 lapics[apic_id].la_ioint_irqs[i] = IRQ_FREE;
657 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
658 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] =
661 lapics[apic_id].la_ioint_irqs[IDT_DTRACE_RET - APIC_IO_INTS] =
665 lapics[apic_id].la_ioint_irqs[IDT_EVTCHN - APIC_IO_INTS] = IRQ_EVTCHN;
670 cpu_add(apic_id, boot_cpu);
674 static inline uint32_t
675 amd_read_ext_features(void)
679 if (cpu_vendor_id != CPU_VENDOR_AMD)
681 version = lapic_read32(LAPIC_VERSION);
682 if ((version & APIC_VER_AMD_EXT_SPACE) != 0)
683 return (lapic_read32(LAPIC_EXT_FEATURES));
688 static inline uint32_t
689 amd_read_elvt_count(void)
694 extf = amd_read_ext_features();
695 count = (extf & APIC_EXTF_ELVT_MASK) >> APIC_EXTF_ELVT_SHIFT;
696 count = min(count, APIC_ELVT_MAX + 1);
701 * Dump contents of local APIC registers
704 native_lapic_dump(const char* str)
712 version = lapic_read32(LAPIC_VERSION);
713 maxlvt = (version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
714 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
715 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x",
716 lapic_read32(LAPIC_ID), version,
717 lapic_read32(LAPIC_LDR), x2apic_mode ? 0 : lapic_read32(LAPIC_DFR));
718 if ((cpu_feature2 & CPUID2_X2APIC) != 0)
719 printf(" x2APIC: %d", x2apic_mode);
720 printf("\n lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
721 lapic_read32(LAPIC_LVT_LINT0), lapic_read32(LAPIC_LVT_LINT1),
722 lapic_read32(LAPIC_TPR), lapic_read32(LAPIC_SVR));
723 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x",
724 lapic_read32(LAPIC_LVT_TIMER), lapic_read32(LAPIC_LVT_THERMAL),
725 lapic_read32(LAPIC_LVT_ERROR));
726 if (maxlvt >= APIC_LVT_PMC)
727 printf(" pmc: 0x%08x", lapic_read32(LAPIC_LVT_PCINT));
729 if (maxlvt >= APIC_LVT_CMCI)
730 printf(" cmci: 0x%08x\n", lapic_read32(LAPIC_LVT_CMCI));
731 extf = amd_read_ext_features();
733 printf(" AMD ext features: 0x%08x\n", extf);
734 elvt_count = amd_read_elvt_count();
735 for (i = 0; i < elvt_count; i++)
736 printf(" AMD elvt%d: 0x%08x\n", i,
737 lapic_read32(LAPIC_EXT_LVT0 + i));
742 native_lapic_xapic_mode(void)
746 saveintr = intr_disable();
748 native_lapic_enable_x2apic();
749 intr_restore(saveintr);
753 native_lapic_setup(int boot)
762 saveintr = intr_disable();
764 la = &lapics[lapic_id()];
765 KASSERT(la->la_present, ("missing APIC structure"));
766 version = lapic_read32(LAPIC_VERSION);
767 maxlvt = (version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
769 /* Initialize the TPR to allow all interrupts. */
772 /* Setup spurious vector and enable the local APIC. */
775 /* Program LINT[01] LVT entries. */
776 lapic_write32(LAPIC_LVT_LINT0, lvt_mode(la, APIC_LVT_LINT0,
777 lapic_read32(LAPIC_LVT_LINT0)));
778 lapic_write32(LAPIC_LVT_LINT1, lvt_mode(la, APIC_LVT_LINT1,
779 lapic_read32(LAPIC_LVT_LINT1)));
781 /* Program the PMC LVT entry if present. */
782 if (maxlvt >= APIC_LVT_PMC) {
783 lapic_write32(LAPIC_LVT_PCINT, lvt_mode(la, APIC_LVT_PMC,
787 /* Program timer LVT. */
788 la->lvt_timer_base = lvt_mode(la, APIC_LVT_TIMER,
789 lapic_read32(LAPIC_LVT_TIMER));
790 la->lvt_timer_last = la->lvt_timer_base;
791 lapic_write32(LAPIC_LVT_TIMER, la->lvt_timer_base);
793 /* Calibrate the timer parameters using BSP. */
794 if (boot && IS_BSP()) {
795 lapic_calibrate_initcount(la);
796 if (lapic_timer_tsc_deadline)
797 lapic_calibrate_deadline(la);
800 /* Setup the timer if configured. */
801 if (la->la_timer_mode != LAT_MODE_UNDEF) {
802 KASSERT(la->la_timer_period != 0, ("lapic%u: zero divisor",
804 switch (la->la_timer_mode) {
805 case LAT_MODE_PERIODIC:
806 lapic_timer_set_divisor(lapic_timer_divisor);
807 lapic_timer_periodic(la);
809 case LAT_MODE_ONESHOT:
810 lapic_timer_set_divisor(lapic_timer_divisor);
811 lapic_timer_oneshot(la);
813 case LAT_MODE_DEADLINE:
814 lapic_timer_deadline(la);
817 panic("corrupted la_timer_mode %p %d", la,
822 /* Program error LVT and clear any existing errors. */
823 lapic_write32(LAPIC_LVT_ERROR, lvt_mode(la, APIC_LVT_ERROR,
824 lapic_read32(LAPIC_LVT_ERROR)));
825 lapic_write32(LAPIC_ESR, 0);
827 /* XXX: Thermal LVT */
829 /* Program the CMCI LVT entry if present. */
830 if (maxlvt >= APIC_LVT_CMCI) {
831 lapic_write32(LAPIC_LVT_CMCI, lvt_mode(la, APIC_LVT_CMCI,
832 lapic_read32(LAPIC_LVT_CMCI)));
835 elvt_count = amd_read_elvt_count();
836 for (i = 0; i < elvt_count; i++) {
837 if (la->la_elvts[i].lvt_active)
838 lapic_write32(LAPIC_EXT_LVT0 + i,
839 elvt_mode(la, i, lapic_read32(LAPIC_EXT_LVT0 + i)));
842 intr_restore(saveintr);
846 native_lapic_intrcnt(void *dummy __unused)
850 char buf[MAXCOMLEN + 1];
852 /* If there are no APICs, skip this function. */
856 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
857 la = &lapics[pc->pc_apic_id];
861 snprintf(buf, sizeof(buf), "cpu%d:timer", pc->pc_cpuid);
862 intrcnt_add(buf, &la->la_timer_count);
865 SYSINIT(native_lapic_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, native_lapic_intrcnt,
869 native_lapic_reenable_pmc(void)
874 value = lapic_read32(LAPIC_LVT_PCINT);
875 value &= ~APIC_LVT_M;
876 lapic_write32(LAPIC_LVT_PCINT, value);
882 lapic_update_pmc(void *dummy)
886 la = &lapics[lapic_id()];
887 lapic_write32(LAPIC_LVT_PCINT, lvt_mode(la, APIC_LVT_PMC,
888 lapic_read32(LAPIC_LVT_PCINT)));
893 native_lapic_enable_pmc(void)
898 /* Fail if the local APIC is not present. */
899 if (!x2apic_mode && lapic_map == NULL)
902 /* Fail if the PMC LVT is not present. */
903 maxlvt = (lapic_read32(LAPIC_VERSION) & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
904 if (maxlvt < APIC_LVT_PMC)
907 lvts[APIC_LVT_PMC].lvt_masked = 0;
909 #ifdef EARLY_AP_STARTUP
910 MPASS(mp_ncpus == 1 || smp_started);
911 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
915 * If hwpmc was loaded at boot time then the APs may not be
916 * started yet. In that case, don't forward the request to
917 * them as they will program the lvt when they start.
920 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
923 lapic_update_pmc(NULL);
932 native_lapic_disable_pmc(void)
937 /* Fail if the local APIC is not present. */
938 if (!x2apic_mode && lapic_map == NULL)
941 /* Fail if the PMC LVT is not present. */
942 maxlvt = (lapic_read32(LAPIC_VERSION) & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
943 if (maxlvt < APIC_LVT_PMC)
946 lvts[APIC_LVT_PMC].lvt_masked = 1;
949 /* The APs should always be started when hwpmc is unloaded. */
950 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early"));
952 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
957 lapic_calibrate_initcount(struct lapic *la)
961 /* Start off with a divisor of 2 (power on reset default). */
962 lapic_timer_divisor = 2;
963 /* Try to calibrate the local APIC timer. */
965 lapic_timer_set_divisor(lapic_timer_divisor);
966 lapic_timer_oneshot_nointr(la, APIC_TIMER_MAX_COUNT);
968 value = APIC_TIMER_MAX_COUNT - lapic_read32(LAPIC_CCR_TIMER);
969 if (value != APIC_TIMER_MAX_COUNT)
971 lapic_timer_divisor <<= 1;
972 } while (lapic_timer_divisor <= 128);
973 if (lapic_timer_divisor > 128)
974 panic("lapic: Divisor too big");
976 printf("lapic: Divisor %lu, Frequency %lu Hz\n",
977 lapic_timer_divisor, value);
983 lapic_calibrate_deadline(struct lapic *la __unused)
987 printf("lapic: deadline tsc mode, Frequency %ju Hz\n",
988 (uintmax_t)tsc_freq);
993 lapic_change_mode(struct eventtimer *et, struct lapic *la,
994 enum lat_timer_mode newmode)
997 if (la->la_timer_mode == newmode)
1000 case LAT_MODE_PERIODIC:
1001 lapic_timer_set_divisor(lapic_timer_divisor);
1002 et->et_frequency = count_freq;
1004 case LAT_MODE_DEADLINE:
1005 et->et_frequency = tsc_freq;
1007 case LAT_MODE_ONESHOT:
1008 lapic_timer_set_divisor(lapic_timer_divisor);
1009 et->et_frequency = count_freq;
1012 panic("lapic_change_mode %d", newmode);
1014 la->la_timer_mode = newmode;
1015 et->et_min_period = (0x00000002LLU << 32) / et->et_frequency;
1016 et->et_max_period = (0xfffffffeLLU << 32) / et->et_frequency;
1020 lapic_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
1024 la = &lapics[PCPU_GET(apic_id)];
1026 lapic_change_mode(et, la, LAT_MODE_PERIODIC);
1027 la->la_timer_period = ((uint32_t)et->et_frequency * period) >>
1029 lapic_timer_periodic(la);
1030 } else if (lapic_timer_tsc_deadline) {
1031 lapic_change_mode(et, la, LAT_MODE_DEADLINE);
1032 la->la_timer_period = (et->et_frequency * first) >> 32;
1033 lapic_timer_deadline(la);
1035 lapic_change_mode(et, la, LAT_MODE_ONESHOT);
1036 la->la_timer_period = ((uint32_t)et->et_frequency * first) >>
1038 lapic_timer_oneshot(la);
1044 lapic_et_stop(struct eventtimer *et)
1048 la = &lapics[PCPU_GET(apic_id)];
1049 lapic_timer_stop(la);
1050 la->la_timer_mode = LAT_MODE_UNDEF;
1055 native_lapic_disable(void)
1059 /* Software disable the local APIC. */
1060 value = lapic_read32(LAPIC_SVR);
1061 value &= ~APIC_SVR_SWEN;
1062 lapic_write32(LAPIC_SVR, value);
1070 /* Program the spurious vector to enable the local APIC. */
1071 value = lapic_read32(LAPIC_SVR);
1072 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
1073 value |= APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT;
1074 if (lapic_eoi_suppression)
1075 value |= APIC_SVR_EOI_SUPPRESSION;
1076 lapic_write32(LAPIC_SVR, value);
1079 /* Reset the local APIC on the BSP during resume. */
1081 lapic_resume(struct pic *pic, bool suspend_cancelled)
1088 native_lapic_id(void)
1092 KASSERT(x2apic_mode || lapic_map != NULL, ("local APIC is not mapped"));
1093 v = lapic_read32(LAPIC_ID);
1095 v >>= APIC_ID_SHIFT;
1100 native_lapic_intr_pending(u_int vector)
1105 * The IRR registers are an array of registers each of which
1106 * only describes 32 interrupts in the low 32 bits. Thus, we
1107 * divide the vector by 32 to get the register index.
1108 * Finally, we modulus the vector by 32 to determine the
1109 * individual bit to test.
1111 irr = lapic_read32(LAPIC_IRR0 + vector / 32);
1112 return (irr & 1 << (vector % 32));
1116 native_lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
1120 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
1121 __func__, apic_id));
1122 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
1123 __func__, cluster));
1124 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
1125 ("%s: intra cluster id %u too big", __func__, cluster_id));
1126 la = &lapics[apic_id];
1127 la->la_cluster = cluster;
1128 la->la_cluster_id = cluster_id;
1132 native_lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
1135 if (pin > APIC_LVT_MAX)
1137 if (apic_id == APIC_ID_ALL) {
1138 lvts[pin].lvt_masked = masked;
1142 KASSERT(lapics[apic_id].la_present,
1143 ("%s: missing APIC %u", __func__, apic_id));
1144 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
1145 lapics[apic_id].la_lvts[pin].lvt_active = 1;
1147 printf("lapic%u:", apic_id);
1150 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
1155 native_lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
1159 if (pin > APIC_LVT_MAX)
1161 if (apic_id == APIC_ID_ALL) {
1166 KASSERT(lapics[apic_id].la_present,
1167 ("%s: missing APIC %u", __func__, apic_id));
1168 lvt = &lapics[apic_id].la_lvts[pin];
1169 lvt->lvt_active = 1;
1171 printf("lapic%u:", apic_id);
1173 lvt->lvt_mode = mode;
1175 case APIC_LVT_DM_NMI:
1176 case APIC_LVT_DM_SMI:
1177 case APIC_LVT_DM_INIT:
1178 case APIC_LVT_DM_EXTINT:
1179 lvt->lvt_edgetrigger = 1;
1180 lvt->lvt_activehi = 1;
1181 if (mode == APIC_LVT_DM_EXTINT)
1182 lvt->lvt_masked = 1;
1184 lvt->lvt_masked = 0;
1187 panic("Unsupported delivery mode: 0x%x\n", mode);
1190 printf(" Routing ");
1192 case APIC_LVT_DM_NMI:
1195 case APIC_LVT_DM_SMI:
1198 case APIC_LVT_DM_INIT:
1201 case APIC_LVT_DM_EXTINT:
1205 printf(" -> LINT%u\n", pin);
1211 native_lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
1214 if (pin > APIC_LVT_MAX || pol == INTR_POLARITY_CONFORM)
1216 if (apic_id == APIC_ID_ALL) {
1217 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
1221 KASSERT(lapics[apic_id].la_present,
1222 ("%s: missing APIC %u", __func__, apic_id));
1223 lapics[apic_id].la_lvts[pin].lvt_active = 1;
1224 lapics[apic_id].la_lvts[pin].lvt_activehi =
1225 (pol == INTR_POLARITY_HIGH);
1227 printf("lapic%u:", apic_id);
1230 printf(" LINT%u polarity: %s\n", pin,
1231 pol == INTR_POLARITY_HIGH ? "high" : "low");
1236 native_lapic_set_lvt_triggermode(u_int apic_id, u_int pin,
1237 enum intr_trigger trigger)
1240 if (pin > APIC_LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
1242 if (apic_id == APIC_ID_ALL) {
1243 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
1247 KASSERT(lapics[apic_id].la_present,
1248 ("%s: missing APIC %u", __func__, apic_id));
1249 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
1250 (trigger == INTR_TRIGGER_EDGE);
1251 lapics[apic_id].la_lvts[pin].lvt_active = 1;
1253 printf("lapic%u:", apic_id);
1256 printf(" LINT%u trigger: %s\n", pin,
1257 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
1262 * Adjust the TPR of the current CPU so that it blocks all interrupts below
1263 * the passed in vector.
1266 lapic_set_tpr(u_int vector)
1269 lapic_write32(LAPIC_TPR, vector);
1273 tpr = lapic_read32(LAPIC_TPR) & ~APIC_TPR_PRIO;
1275 lapic_write32(LAPIC_TPR, tpr);
1280 native_lapic_eoi(void)
1283 lapic_write32_nofence(LAPIC_EOI, 0);
1287 lapic_handle_intr(int vector, struct trapframe *frame)
1289 struct intsrc *isrc;
1291 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id),
1293 intr_execute_handlers(isrc, frame);
1297 lapic_handle_timer(struct trapframe *frame)
1300 struct trapframe *oldframe;
1303 /* Send EOI first thing. */
1306 #if defined(SMP) && !defined(SCHED_ULE)
1308 * Don't do any accounting for the disabled HTT cores, since it
1309 * will provide misleading numbers for the userland.
1311 * No locking is necessary here, since even if we lose the race
1312 * when hlt_cpus_mask changes it is not a big deal, really.
1314 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
1315 * and unlike other schedulers it actually schedules threads to
1318 if (CPU_ISSET(PCPU_GET(cpuid), &hlt_cpus_mask))
1322 /* Look up our local APIC structure for the tick counters. */
1323 la = &lapics[PCPU_GET(apic_id)];
1324 (*la->la_timer_count)++;
1326 if (lapic_et.et_active) {
1328 td->td_intr_nesting_level++;
1329 oldframe = td->td_intr_frame;
1330 td->td_intr_frame = frame;
1331 lapic_et.et_event_cb(&lapic_et, lapic_et.et_arg);
1332 td->td_intr_frame = oldframe;
1333 td->td_intr_nesting_level--;
1339 lapic_timer_set_divisor(u_int divisor)
1342 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
1343 KASSERT(ffs(divisor) <= nitems(lapic_timer_divisors),
1344 ("lapic: invalid divisor %u", divisor));
1345 lapic_write32(LAPIC_DCR_TIMER, lapic_timer_divisors[ffs(divisor) - 1]);
1349 lapic_timer_oneshot(struct lapic *la)
1353 value = la->lvt_timer_base;
1354 value &= ~(APIC_LVTT_TM | APIC_LVT_M);
1355 value |= APIC_LVTT_TM_ONE_SHOT;
1356 la->lvt_timer_last = value;
1357 lapic_write32(LAPIC_LVT_TIMER, value);
1358 lapic_write32(LAPIC_ICR_TIMER, la->la_timer_period);
1362 lapic_timer_oneshot_nointr(struct lapic *la, uint32_t count)
1366 value = la->lvt_timer_base;
1367 value &= ~APIC_LVTT_TM;
1368 value |= APIC_LVTT_TM_ONE_SHOT | APIC_LVT_M;
1369 la->lvt_timer_last = value;
1370 lapic_write32(LAPIC_LVT_TIMER, value);
1371 lapic_write32(LAPIC_ICR_TIMER, count);
1375 lapic_timer_periodic(struct lapic *la)
1379 value = la->lvt_timer_base;
1380 value &= ~(APIC_LVTT_TM | APIC_LVT_M);
1381 value |= APIC_LVTT_TM_PERIODIC;
1382 la->lvt_timer_last = value;
1383 lapic_write32(LAPIC_LVT_TIMER, value);
1384 lapic_write32(LAPIC_ICR_TIMER, la->la_timer_period);
1388 lapic_timer_deadline(struct lapic *la)
1392 value = la->lvt_timer_base;
1393 value &= ~(APIC_LVTT_TM | APIC_LVT_M);
1394 value |= APIC_LVTT_TM_TSCDLT;
1395 if (value != la->lvt_timer_last) {
1396 la->lvt_timer_last = value;
1397 lapic_write32_nofence(LAPIC_LVT_TIMER, value);
1401 wrmsr(MSR_TSC_DEADLINE, la->la_timer_period + rdtsc());
1405 lapic_timer_stop(struct lapic *la)
1409 if (la->la_timer_mode == LAT_MODE_DEADLINE) {
1410 wrmsr(MSR_TSC_DEADLINE, 0);
1413 value = la->lvt_timer_base;
1414 value &= ~APIC_LVTT_TM;
1415 value |= APIC_LVT_M;
1416 la->lvt_timer_last = value;
1417 lapic_write32(LAPIC_LVT_TIMER, value);
1422 lapic_handle_cmc(void)
1430 * Called from the mca_init() to activate the CMC interrupt if this CPU is
1431 * responsible for monitoring any MC banks for CMC events. Since mca_init()
1432 * is called prior to lapic_setup() during boot, this just needs to unmask
1433 * this CPU's LVT_CMCI entry.
1436 native_lapic_enable_cmc(void)
1441 if (!x2apic_mode && lapic_map == NULL)
1444 apic_id = PCPU_GET(apic_id);
1445 KASSERT(lapics[apic_id].la_present,
1446 ("%s: missing APIC %u", __func__, apic_id));
1447 lapics[apic_id].la_lvts[APIC_LVT_CMCI].lvt_masked = 0;
1448 lapics[apic_id].la_lvts[APIC_LVT_CMCI].lvt_active = 1;
1450 printf("lapic%u: CMCI unmasked\n", apic_id);
1454 native_lapic_enable_mca_elvt(void)
1461 if (lapic_map == NULL)
1465 apic_id = PCPU_GET(apic_id);
1466 KASSERT(lapics[apic_id].la_present,
1467 ("%s: missing APIC %u", __func__, apic_id));
1468 elvt_count = amd_read_elvt_count();
1469 if (elvt_count <= APIC_ELVT_MCA)
1472 value = lapic_read32(LAPIC_EXT_LVT0 + APIC_ELVT_MCA);
1473 if ((value & APIC_LVT_M) == 0) {
1475 printf("AMD MCE Thresholding Extended LVT is already active\n");
1476 return (APIC_ELVT_MCA);
1478 lapics[apic_id].la_elvts[APIC_ELVT_MCA].lvt_masked = 0;
1479 lapics[apic_id].la_elvts[APIC_ELVT_MCA].lvt_active = 1;
1481 printf("lapic%u: MCE Thresholding ELVT unmasked\n", apic_id);
1482 return (APIC_ELVT_MCA);
1486 lapic_handle_error(void)
1491 * Read the contents of the error status register. Write to
1492 * the register first before reading from it to force the APIC
1493 * to update its value to indicate any errors that have
1494 * occurred since the previous write to the register.
1496 lapic_write32(LAPIC_ESR, 0);
1497 esr = lapic_read32(LAPIC_ESR);
1499 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr);
1504 native_apic_cpuid(u_int apic_id)
1507 return apic_cpuids[apic_id];
1513 /* Request a free IDT vector to be used by the specified IRQ. */
1515 native_apic_alloc_vector(u_int apic_id, u_int irq)
1519 KASSERT(irq < num_io_irqs, ("Invalid IRQ %u", irq));
1522 * Search for a free vector. Currently we just use a very simple
1523 * algorithm to find the first free vector.
1525 mtx_lock_spin(&icu_lock);
1526 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
1527 if (lapics[apic_id].la_ioint_irqs[vector] != IRQ_FREE)
1529 lapics[apic_id].la_ioint_irqs[vector] = irq;
1530 mtx_unlock_spin(&icu_lock);
1531 return (vector + APIC_IO_INTS);
1533 mtx_unlock_spin(&icu_lock);
1538 * Request 'count' free contiguous IDT vectors to be used by 'count'
1539 * IRQs. 'count' must be a power of two and the vectors will be
1540 * aligned on a boundary of 'align'. If the request cannot be
1541 * satisfied, 0 is returned.
1544 native_apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
1546 u_int first, run, vector;
1548 KASSERT(powerof2(count), ("bad count"));
1549 KASSERT(powerof2(align), ("bad align"));
1550 KASSERT(align >= count, ("align < count"));
1552 for (run = 0; run < count; run++)
1553 KASSERT(irqs[run] < num_io_irqs, ("Invalid IRQ %u at index %u",
1558 * Search for 'count' free vectors. As with apic_alloc_vector(),
1559 * this just uses a simple first fit algorithm.
1563 mtx_lock_spin(&icu_lock);
1564 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
1566 /* Vector is in use, end run. */
1567 if (lapics[apic_id].la_ioint_irqs[vector] != IRQ_FREE) {
1573 /* Start a new run if run == 0 and vector is aligned. */
1575 if ((vector & (align - 1)) != 0)
1581 /* Keep looping if the run isn't long enough yet. */
1585 /* Found a run, assign IRQs and return the first vector. */
1586 for (vector = 0; vector < count; vector++)
1587 lapics[apic_id].la_ioint_irqs[first + vector] =
1589 mtx_unlock_spin(&icu_lock);
1590 return (first + APIC_IO_INTS);
1592 mtx_unlock_spin(&icu_lock);
1593 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
1598 * Enable a vector for a particular apic_id. Since all lapics share idt
1599 * entries and ioint_handlers this enables the vector on all lapics. lapics
1600 * which do not have the vector configured would report spurious interrupts
1604 native_apic_enable_vector(u_int apic_id, u_int vector)
1607 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1608 KASSERT(ioint_handlers[vector / 32] != NULL,
1609 ("No ISR handler for vector %u", vector));
1610 #ifdef KDTRACE_HOOKS
1611 KASSERT(vector != IDT_DTRACE_RET,
1612 ("Attempt to overwrite DTrace entry"));
1614 setidt(vector, (pti ? ioint_pti_handlers : ioint_handlers)[vector / 32],
1615 SDT_APIC, SEL_KPL, GSEL_APIC);
1619 native_apic_disable_vector(u_int apic_id, u_int vector)
1622 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1623 #ifdef KDTRACE_HOOKS
1624 KASSERT(vector != IDT_DTRACE_RET,
1625 ("Attempt to overwrite DTrace entry"));
1627 KASSERT(ioint_handlers[vector / 32] != NULL,
1628 ("No ISR handler for vector %u", vector));
1631 * We can not currently clear the idt entry because other cpus
1632 * may have a valid vector at this offset.
1634 setidt(vector, pti ? &IDTVEC(rsvd_pti) : &IDTVEC(rsvd), SDT_APIC,
1635 SEL_KPL, GSEL_APIC);
1639 /* Release an APIC vector when it's no longer in use. */
1641 native_apic_free_vector(u_int apic_id, u_int vector, u_int irq)
1645 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1646 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1647 ("Vector %u does not map to an IRQ line", vector));
1648 KASSERT(irq < num_io_irqs, ("Invalid IRQ %u", irq));
1649 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] ==
1650 irq, ("IRQ mismatch"));
1651 #ifdef KDTRACE_HOOKS
1652 KASSERT(vector != IDT_DTRACE_RET,
1653 ("Attempt to overwrite DTrace entry"));
1657 * Bind us to the cpu that owned the vector before freeing it so
1658 * we don't lose an interrupt delivery race.
1663 if (sched_is_bound(td))
1664 panic("apic_free_vector: Thread already bound.\n");
1665 sched_bind(td, apic_cpuid(apic_id));
1668 mtx_lock_spin(&icu_lock);
1669 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = IRQ_FREE;
1670 mtx_unlock_spin(&icu_lock);
1678 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
1680 apic_idt_to_irq(u_int apic_id, u_int vector)
1684 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1685 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1686 ("Vector %u does not map to an IRQ line", vector));
1687 #ifdef KDTRACE_HOOKS
1688 KASSERT(vector != IDT_DTRACE_RET,
1689 ("Attempt to overwrite DTrace entry"));
1691 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS];
1699 * Dump data about APIC IDT vector mappings.
1701 DB_SHOW_COMMAND(apic, db_show_apic)
1703 struct intsrc *isrc;
1708 if (strcmp(modif, "vv") == 0)
1710 else if (strcmp(modif, "v") == 0)
1714 for (apic_id = 0; apic_id <= max_apic_id; apic_id++) {
1715 if (lapics[apic_id].la_present == 0)
1717 db_printf("Interrupts bound to lapic %u\n", apic_id);
1718 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
1719 irq = lapics[apic_id].la_ioint_irqs[i];
1720 if (irq == IRQ_FREE || irq == IRQ_SYSCALL)
1722 #ifdef KDTRACE_HOOKS
1723 if (irq == IRQ_DTRACE_RET)
1727 if (irq == IRQ_EVTCHN)
1730 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
1731 if (irq == IRQ_TIMER)
1732 db_printf("lapic timer\n");
1733 else if (irq < num_io_irqs) {
1734 isrc = intr_lookup_source(irq);
1735 if (isrc == NULL || verbose == 0)
1736 db_printf("IRQ %u\n", irq);
1738 db_dump_intr_event(isrc->is_event,
1741 db_printf("IRQ %u ???\n", irq);
1747 dump_mask(const char *prefix, uint32_t v, int base)
1752 for (i = 0; i < 32; i++)
1755 db_printf("%s:", prefix);
1758 db_printf(" %02x", base + i);
1764 /* Show info from the lapic regs for this CPU. */
1765 DB_SHOW_COMMAND(lapic, db_show_lapic)
1769 db_printf("lapic ID = %d\n", lapic_id());
1770 v = lapic_read32(LAPIC_VERSION);
1771 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
1773 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
1774 v = lapic_read32(LAPIC_SVR);
1775 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
1776 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
1777 db_printf("TPR = %02x\n", lapic_read32(LAPIC_TPR));
1779 #define dump_field(prefix, regn, index) \
1780 dump_mask(__XSTRING(prefix ## index), \
1781 lapic_read32(LAPIC_ ## regn ## index), \
1784 db_printf("In-service Interrupts:\n");
1785 dump_field(isr, ISR, 0);
1786 dump_field(isr, ISR, 1);
1787 dump_field(isr, ISR, 2);
1788 dump_field(isr, ISR, 3);
1789 dump_field(isr, ISR, 4);
1790 dump_field(isr, ISR, 5);
1791 dump_field(isr, ISR, 6);
1792 dump_field(isr, ISR, 7);
1794 db_printf("TMR Interrupts:\n");
1795 dump_field(tmr, TMR, 0);
1796 dump_field(tmr, TMR, 1);
1797 dump_field(tmr, TMR, 2);
1798 dump_field(tmr, TMR, 3);
1799 dump_field(tmr, TMR, 4);
1800 dump_field(tmr, TMR, 5);
1801 dump_field(tmr, TMR, 6);
1802 dump_field(tmr, TMR, 7);
1804 db_printf("IRR Interrupts:\n");
1805 dump_field(irr, IRR, 0);
1806 dump_field(irr, IRR, 1);
1807 dump_field(irr, IRR, 2);
1808 dump_field(irr, IRR, 3);
1809 dump_field(irr, IRR, 4);
1810 dump_field(irr, IRR, 5);
1811 dump_field(irr, IRR, 6);
1812 dump_field(irr, IRR, 7);
1819 * APIC probing support code. This includes code to manage enumerators.
1822 static SLIST_HEAD(, apic_enumerator) enumerators =
1823 SLIST_HEAD_INITIALIZER(enumerators);
1824 static struct apic_enumerator *best_enum;
1827 apic_register_enumerator(struct apic_enumerator *enumerator)
1830 struct apic_enumerator *apic_enum;
1832 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1833 if (apic_enum == enumerator)
1834 panic("%s: Duplicate register of %s", __func__,
1835 enumerator->apic_name);
1838 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1842 * We have to look for CPU's very, very early because certain subsystems
1843 * want to know how many CPU's we have extremely early on in the boot
1847 apic_init(void *dummy __unused)
1849 struct apic_enumerator *enumerator;
1852 /* We only support built in local APICs. */
1853 if (!(cpu_feature & CPUID_APIC))
1856 /* Don't probe if APIC mode is disabled. */
1857 if (resource_disabled("apic", 0))
1860 /* Probe all the enumerators to find the best match. */
1863 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1864 retval = enumerator->apic_probe();
1867 if (best_enum == NULL || best < retval) {
1868 best_enum = enumerator;
1872 if (best_enum == NULL) {
1874 printf("APIC: Could not find any APICs.\n");
1876 panic("running without device atpic requires a local APIC");
1882 printf("APIC: Using the %s enumerator.\n",
1883 best_enum->apic_name);
1887 * To work around an errata, we disable the local APIC on some
1888 * CPUs during early startup. We need to turn the local APIC back
1889 * on on such CPUs now.
1891 ppro_reenable_apic();
1894 /* Probe the CPU's in the system. */
1895 retval = best_enum->apic_probe_cpus();
1897 printf("%s: Failed to probe CPUs: returned %d\n",
1898 best_enum->apic_name, retval);
1901 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL);
1904 * Setup the local APIC. We have to do this prior to starting up the APs
1908 apic_setup_local(void *dummy __unused)
1912 if (best_enum == NULL)
1915 lapics = malloc(sizeof(*lapics) * (max_apic_id + 1), M_LAPIC,
1918 /* Initialize the local APIC. */
1919 retval = best_enum->apic_setup_local();
1921 printf("%s: Failed to setup the local APIC: returned %d\n",
1922 best_enum->apic_name, retval);
1924 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local, NULL);
1927 * Setup the I/O APICs.
1930 apic_setup_io(void *dummy __unused)
1934 if (best_enum == NULL)
1938 * Local APIC must be registered before other PICs and pseudo PICs
1939 * for proper suspend/resume order.
1941 intr_register_pic(&lapic_pic);
1943 retval = best_enum->apic_setup_io();
1945 printf("%s: Failed to setup I/O APICs: returned %d\n",
1946 best_enum->apic_name, retval);
1949 * Finish setting up the local APIC on the BSP once we know
1950 * how to properly program the LINT pins. In particular, this
1951 * enables the EOI suppression mode, if LAPIC supports it and
1952 * user did not disable the mode.
1958 /* Enable the MSI "pic". */
1959 init_ops.msi_init();
1962 xen_intr_alloc_irqs();
1965 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_THIRD, apic_setup_io, NULL);
1969 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1970 * private to the MD code. The public interface for the rest of the
1971 * kernel is defined in mp_machdep.c.
1975 * Wait delay microseconds for IPI to be sent. If delay is -1, we
1979 native_lapic_ipi_wait(int delay)
1983 /* LAPIC_ICR.APIC_DELSTAT_MASK is undefined in x2APIC mode */
1987 for (rx = 0; delay == -1 || rx < lapic_ipi_wait_mult * delay; rx++) {
1988 if ((lapic_read_icr_lo() & APIC_DELSTAT_MASK) ==
1997 native_lapic_ipi_raw(register_t icrlo, u_int dest)
2001 register_t saveintr;
2003 /* XXX: Need more sanity checking of icrlo? */
2004 KASSERT(x2apic_mode || lapic_map != NULL,
2005 ("%s called too early", __func__));
2006 KASSERT(x2apic_mode ||
2007 (dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
2008 ("%s: invalid dest field", __func__));
2009 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
2010 ("%s: reserved bits set in ICR LO register", __func__));
2012 /* Set destination in ICR HI register if it is being used. */
2014 saveintr = intr_disable();
2015 icr = lapic_read_icr();
2018 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
2023 vhi &= ~APIC_ID_MASK;
2024 vhi |= dest << APIC_ID_SHIFT;
2030 /* Program the contents of the IPI and dispatch it. */
2035 vlo &= APIC_ICRLO_RESV_MASK;
2038 lapic_write_icr(vhi, vlo);
2040 intr_restore(saveintr);
2043 #define BEFORE_SPIN 50000
2044 #ifdef DETECT_DEADLOCK
2045 #define AFTER_SPIN 50
2049 native_lapic_ipi_vectored(u_int vector, int dest)
2051 register_t icrlo, destfield;
2053 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
2054 ("%s: invalid vector %d", __func__, vector));
2056 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE | APIC_LEVEL_ASSERT;
2059 * NMI IPIs are just fake vectors used to send a NMI. Use special rules
2060 * regarding NMIs if passed, otherwise specify the vector.
2062 if (vector >= IPI_NMI_FIRST)
2063 icrlo |= APIC_DELMODE_NMI;
2065 icrlo |= vector | APIC_DELMODE_FIXED;
2068 case APIC_IPI_DEST_SELF:
2069 icrlo |= APIC_DEST_SELF;
2071 case APIC_IPI_DEST_ALL:
2072 icrlo |= APIC_DEST_ALLISELF;
2074 case APIC_IPI_DEST_OTHERS:
2075 icrlo |= APIC_DEST_ALLESELF;
2078 KASSERT(x2apic_mode ||
2079 (dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
2080 ("%s: invalid destination 0x%x", __func__, dest));
2084 /* Wait for an earlier IPI to finish. */
2085 if (!lapic_ipi_wait(BEFORE_SPIN)) {
2086 if (panicstr != NULL)
2089 panic("APIC: Previous IPI is stuck");
2092 lapic_ipi_raw(icrlo, destfield);
2094 #ifdef DETECT_DEADLOCK
2095 /* Wait for IPI to be delivered. */
2096 if (!lapic_ipi_wait(AFTER_SPIN)) {
2097 #ifdef needsattention
2101 * The above function waits for the message to actually be
2102 * delivered. It breaks out after an arbitrary timeout
2103 * since the message should eventually be delivered (at
2104 * least in theory) and that if it wasn't we would catch
2105 * the failure with the check above when the next IPI is
2108 * We could skip this wait entirely, EXCEPT it probably
2109 * protects us from other routines that assume that the
2110 * message was delivered and acted upon when this function
2113 printf("APIC: IPI might be stuck\n");
2114 #else /* !needsattention */
2115 /* Wait until mesage is sent without a timeout. */
2116 while (lapic_read_icr_lo() & APIC_DELSTAT_PEND)
2118 #endif /* needsattention */
2120 #endif /* DETECT_DEADLOCK */
2126 * Since the IDT is shared by all CPUs the IPI slot update needs to be globally
2129 * Consider the case where an IPI is generated immediately after allocation:
2130 * vector = lapic_ipi_alloc(ipifunc);
2131 * ipi_selected(other_cpus, vector);
2133 * In xAPIC mode a write to ICR_LO has serializing semantics because the
2134 * APIC page is mapped as an uncached region. In x2APIC mode there is an
2135 * explicit 'mfence' before the ICR MSR is written. Therefore in both cases
2136 * the IDT slot update is globally visible before the IPI is delivered.
2139 native_lapic_ipi_alloc(inthand_t *ipifunc)
2141 struct gate_descriptor *ip;
2145 KASSERT(ipifunc != &IDTVEC(rsvd) && ipifunc != &IDTVEC(rsvd_pti),
2146 ("invalid ipifunc %p", ipifunc));
2149 mtx_lock_spin(&icu_lock);
2150 for (idx = IPI_DYN_FIRST; idx <= IPI_DYN_LAST; idx++) {
2152 func = (ip->gd_hioffset << 16) | ip->gd_looffset;
2153 if ((!pti && func == (uintptr_t)&IDTVEC(rsvd)) ||
2154 (pti && func == (uintptr_t)&IDTVEC(rsvd_pti))) {
2156 setidt(vector, ipifunc, SDT_APIC, SEL_KPL, GSEL_APIC);
2160 mtx_unlock_spin(&icu_lock);
2165 native_lapic_ipi_free(int vector)
2167 struct gate_descriptor *ip;
2170 KASSERT(vector >= IPI_DYN_FIRST && vector <= IPI_DYN_LAST,
2171 ("%s: invalid vector %d", __func__, vector));
2173 mtx_lock_spin(&icu_lock);
2175 func = (ip->gd_hioffset << 16) | ip->gd_looffset;
2176 KASSERT(func != (uintptr_t)&IDTVEC(rsvd) &&
2177 func != (uintptr_t)&IDTVEC(rsvd_pti),
2178 ("invalid idtfunc %#lx", func));
2179 setidt(vector, pti ? &IDTVEC(rsvd_pti) : &IDTVEC(rsvd), SDT_APIC,
2180 SEL_KPL, GSEL_APIC);
2181 mtx_unlock_spin(&icu_lock);