2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1996, by Steve Passe
6 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. The name of the developer may NOT be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 * 3. Neither the name of the author nor the names of any co-contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Local APIC support on Pentium and later processors.
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include "opt_atpic.h"
40 #include "opt_hwpmc_hooks.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/kernel.h>
49 #include <sys/malloc.h>
50 #include <sys/mutex.h>
53 #include <sys/sched.h>
55 #include <sys/sysctl.h>
56 #include <sys/timeet.h>
61 #include <x86/apicreg.h>
62 #include <machine/clock.h>
63 #include <machine/cpufunc.h>
64 #include <machine/cputypes.h>
65 #include <machine/frame.h>
66 #include <machine/intr_machdep.h>
67 #include <x86/apicvar.h>
69 #include <machine/md_var.h>
70 #include <machine/smp.h>
71 #include <machine/specialreg.h>
75 #include <sys/interrupt.h>
80 #define SDT_APIC SDT_SYSIGT
83 #define SDT_APIC SDT_SYS386IGT
84 #define GSEL_APIC GSEL(GCODE_SEL, SEL_KPL)
87 static MALLOC_DEFINE(M_LAPIC, "local_apic", "Local APIC items");
89 /* Sanity checks on IDT vectors. */
90 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
91 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
92 CTASSERT(APIC_LOCAL_INTS == 240);
93 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
96 * I/O interrupts use non-negative IRQ values. These values are used
97 * to mark unused IDT entries or IDT entries reserved for a non-I/O
102 #define IRQ_SYSCALL -3
103 #define IRQ_DTRACE_RET -4
104 #define IRQ_EVTCHN -5
106 enum lat_timer_mode {
108 LAT_MODE_PERIODIC = 1,
109 LAT_MODE_ONESHOT = 2,
110 LAT_MODE_DEADLINE = 3,
114 * Support for local APICs. Local APICs manage interrupts on each
115 * individual processor as opposed to I/O APICs which receive interrupts
116 * from I/O devices and then forward them on to the local APICs.
118 * Local APICs can also send interrupts to each other thus providing the
119 * mechanism for IPIs.
123 u_int lvt_edgetrigger:1;
124 u_int lvt_activehi:1;
132 struct lvt la_lvts[APIC_LVT_MAX + 1];
133 struct lvt la_elvts[APIC_ELVT_MAX + 1];
136 u_int la_cluster_id:2;
138 u_long *la_timer_count;
139 uint64_t la_timer_period;
140 enum lat_timer_mode la_timer_mode;
141 uint32_t lvt_timer_base;
142 uint32_t lvt_timer_last;
143 /* Include IDT_SYSCALL to make indexing easier. */
144 int la_ioint_irqs[APIC_NUM_IOINTS + 1];
147 /* Global defaults for local APIC LVT entries. */
148 static struct lvt lvts[APIC_LVT_MAX + 1] = {
149 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
150 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
151 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
152 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
153 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
154 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
155 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_CMC_INT }, /* CMCI */
158 /* Global defaults for AMD local APIC ELVT entries. */
159 static struct lvt elvts[APIC_ELVT_MAX + 1] = {
160 { 1, 1, 1, 0, APIC_LVT_DM_FIXED, 0 },
161 { 1, 1, 1, 0, APIC_LVT_DM_FIXED, APIC_CMC_INT },
162 { 1, 1, 1, 0, APIC_LVT_DM_FIXED, 0 },
163 { 1, 1, 1, 0, APIC_LVT_DM_FIXED, 0 },
166 static inthand_t *ioint_handlers[] = {
168 IDTVEC(apic_isr1), /* 32 - 63 */
169 IDTVEC(apic_isr2), /* 64 - 95 */
170 IDTVEC(apic_isr3), /* 96 - 127 */
171 IDTVEC(apic_isr4), /* 128 - 159 */
172 IDTVEC(apic_isr5), /* 160 - 191 */
173 IDTVEC(apic_isr6), /* 192 - 223 */
174 IDTVEC(apic_isr7), /* 224 - 255 */
177 static inthand_t *ioint_pti_handlers[] = {
179 IDTVEC(apic_isr1_pti), /* 32 - 63 */
180 IDTVEC(apic_isr2_pti), /* 64 - 95 */
181 IDTVEC(apic_isr3_pti), /* 96 - 127 */
182 IDTVEC(apic_isr4_pti), /* 128 - 159 */
183 IDTVEC(apic_isr5_pti), /* 160 - 191 */
184 IDTVEC(apic_isr6_pti), /* 192 - 223 */
185 IDTVEC(apic_isr7_pti), /* 224 - 255 */
188 static u_int32_t lapic_timer_divisors[] = {
189 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
190 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
193 extern inthand_t IDTVEC(rsvd_pti), IDTVEC(rsvd);
195 volatile char *lapic_map;
196 vm_paddr_t lapic_paddr;
198 int lapic_eoi_suppression;
199 static int lapic_timer_tsc_deadline;
200 static u_long lapic_timer_divisor, count_freq;
201 static struct eventtimer lapic_et;
203 static uint64_t lapic_ipi_wait_mult;
205 unsigned int max_apic_id;
207 SYSCTL_NODE(_hw, OID_AUTO, apic, CTLFLAG_RD, 0, "APIC options");
208 SYSCTL_INT(_hw_apic, OID_AUTO, x2apic_mode, CTLFLAG_RD, &x2apic_mode, 0, "");
209 SYSCTL_INT(_hw_apic, OID_AUTO, eoi_suppression, CTLFLAG_RD,
210 &lapic_eoi_suppression, 0, "");
211 SYSCTL_INT(_hw_apic, OID_AUTO, timer_tsc_deadline, CTLFLAG_RD,
212 &lapic_timer_tsc_deadline, 0, "");
214 static void lapic_calibrate_initcount(struct lapic *la);
215 static void lapic_calibrate_deadline(struct lapic *la);
218 lapic_read32(enum LAPIC_REGISTERS reg)
223 res = rdmsr32(MSR_APIC_000 + reg);
225 res = *(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL);
231 lapic_write32(enum LAPIC_REGISTERS reg, uint32_t val)
237 wrmsr(MSR_APIC_000 + reg, val);
239 *(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL) = val;
244 lapic_write32_nofence(enum LAPIC_REGISTERS reg, uint32_t val)
248 wrmsr(MSR_APIC_000 + reg, val);
250 *(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL) = val;
262 v = rdmsr(MSR_APIC_000 + LAPIC_ICR_LO);
264 vhi = lapic_read32(LAPIC_ICR_HI);
265 vlo = lapic_read32(LAPIC_ICR_LO);
266 v = ((uint64_t)vhi << 32) | vlo;
272 lapic_read_icr_lo(void)
275 return (lapic_read32(LAPIC_ICR_LO));
279 lapic_write_icr(uint32_t vhi, uint32_t vlo)
284 v = ((uint64_t)vhi << 32) | vlo;
286 wrmsr(MSR_APIC_000 + LAPIC_ICR_LO, v);
288 lapic_write32(LAPIC_ICR_HI, vhi);
289 lapic_write32(LAPIC_ICR_LO, vlo);
295 native_lapic_enable_x2apic(void)
299 apic_base = rdmsr(MSR_APICBASE);
300 apic_base |= APICBASE_X2APIC | APICBASE_ENABLED;
301 wrmsr(MSR_APICBASE, apic_base);
305 native_lapic_is_x2apic(void)
309 apic_base = rdmsr(MSR_APICBASE);
310 return ((apic_base & (APICBASE_X2APIC | APICBASE_ENABLED)) ==
311 (APICBASE_X2APIC | APICBASE_ENABLED));
314 static void lapic_enable(void);
315 static void lapic_resume(struct pic *pic, bool suspend_cancelled);
316 static void lapic_timer_oneshot(struct lapic *);
317 static void lapic_timer_oneshot_nointr(struct lapic *, uint32_t);
318 static void lapic_timer_periodic(struct lapic *);
319 static void lapic_timer_deadline(struct lapic *);
320 static void lapic_timer_stop(struct lapic *);
321 static void lapic_timer_set_divisor(u_int divisor);
322 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
323 static int lapic_et_start(struct eventtimer *et,
324 sbintime_t first, sbintime_t period);
325 static int lapic_et_stop(struct eventtimer *et);
326 static u_int apic_idt_to_irq(u_int apic_id, u_int vector);
327 static void lapic_set_tpr(u_int vector);
329 struct pic lapic_pic = { .pic_resume = lapic_resume };
331 /* Forward declarations for apic_ops */
332 static void native_lapic_create(u_int apic_id, int boot_cpu);
333 static void native_lapic_init(vm_paddr_t addr);
334 static void native_lapic_xapic_mode(void);
335 static void native_lapic_setup(int boot);
336 static void native_lapic_dump(const char *str);
337 static void native_lapic_disable(void);
338 static void native_lapic_eoi(void);
339 static int native_lapic_id(void);
340 static int native_lapic_intr_pending(u_int vector);
341 static u_int native_apic_cpuid(u_int apic_id);
342 static u_int native_apic_alloc_vector(u_int apic_id, u_int irq);
343 static u_int native_apic_alloc_vectors(u_int apic_id, u_int *irqs,
344 u_int count, u_int align);
345 static void native_apic_disable_vector(u_int apic_id, u_int vector);
346 static void native_apic_enable_vector(u_int apic_id, u_int vector);
347 static void native_apic_free_vector(u_int apic_id, u_int vector, u_int irq);
348 static void native_lapic_set_logical_id(u_int apic_id, u_int cluster,
350 static int native_lapic_enable_pmc(void);
351 static void native_lapic_disable_pmc(void);
352 static void native_lapic_reenable_pmc(void);
353 static void native_lapic_enable_cmc(void);
354 static int native_lapic_enable_mca_elvt(void);
355 static int native_lapic_set_lvt_mask(u_int apic_id, u_int lvt,
357 static int native_lapic_set_lvt_mode(u_int apic_id, u_int lvt,
359 static int native_lapic_set_lvt_polarity(u_int apic_id, u_int lvt,
360 enum intr_polarity pol);
361 static int native_lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
362 enum intr_trigger trigger);
364 static void native_lapic_ipi_raw(register_t icrlo, u_int dest);
365 static void native_lapic_ipi_vectored(u_int vector, int dest);
366 static int native_lapic_ipi_wait(int delay);
368 static int native_lapic_ipi_alloc(inthand_t *ipifunc);
369 static void native_lapic_ipi_free(int vector);
371 struct apic_ops apic_ops = {
372 .create = native_lapic_create,
373 .init = native_lapic_init,
374 .xapic_mode = native_lapic_xapic_mode,
375 .is_x2apic = native_lapic_is_x2apic,
376 .setup = native_lapic_setup,
377 .dump = native_lapic_dump,
378 .disable = native_lapic_disable,
379 .eoi = native_lapic_eoi,
380 .id = native_lapic_id,
381 .intr_pending = native_lapic_intr_pending,
382 .set_logical_id = native_lapic_set_logical_id,
383 .cpuid = native_apic_cpuid,
384 .alloc_vector = native_apic_alloc_vector,
385 .alloc_vectors = native_apic_alloc_vectors,
386 .enable_vector = native_apic_enable_vector,
387 .disable_vector = native_apic_disable_vector,
388 .free_vector = native_apic_free_vector,
389 .enable_pmc = native_lapic_enable_pmc,
390 .disable_pmc = native_lapic_disable_pmc,
391 .reenable_pmc = native_lapic_reenable_pmc,
392 .enable_cmc = native_lapic_enable_cmc,
393 .enable_mca_elvt = native_lapic_enable_mca_elvt,
395 .ipi_raw = native_lapic_ipi_raw,
396 .ipi_vectored = native_lapic_ipi_vectored,
397 .ipi_wait = native_lapic_ipi_wait,
399 .ipi_alloc = native_lapic_ipi_alloc,
400 .ipi_free = native_lapic_ipi_free,
401 .set_lvt_mask = native_lapic_set_lvt_mask,
402 .set_lvt_mode = native_lapic_set_lvt_mode,
403 .set_lvt_polarity = native_lapic_set_lvt_polarity,
404 .set_lvt_triggermode = native_lapic_set_lvt_triggermode,
408 lvt_mode_impl(struct lapic *la, struct lvt *lvt, u_int pin, uint32_t value)
411 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
413 if (lvt->lvt_edgetrigger == 0)
414 value |= APIC_LVT_TM;
415 if (lvt->lvt_activehi == 0)
416 value |= APIC_LVT_IIPP_INTALO;
419 value |= lvt->lvt_mode;
420 switch (lvt->lvt_mode) {
421 case APIC_LVT_DM_NMI:
422 case APIC_LVT_DM_SMI:
423 case APIC_LVT_DM_INIT:
424 case APIC_LVT_DM_EXTINT:
425 if (!lvt->lvt_edgetrigger && bootverbose) {
426 printf("lapic%u: Forcing LINT%u to edge trigger\n",
428 value &= ~APIC_LVT_TM;
430 /* Use a vector of 0. */
432 case APIC_LVT_DM_FIXED:
433 value |= lvt->lvt_vector;
436 panic("bad APIC LVT delivery mode: %#x\n", value);
442 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
446 KASSERT(pin <= APIC_LVT_MAX,
447 ("%s: pin %u out of range", __func__, pin));
448 if (la->la_lvts[pin].lvt_active)
449 lvt = &la->la_lvts[pin];
453 return (lvt_mode_impl(la, lvt, pin, value));
457 elvt_mode(struct lapic *la, u_int idx, uint32_t value)
461 KASSERT(idx <= APIC_ELVT_MAX,
462 ("%s: idx %u out of range", __func__, idx));
464 elvt = &la->la_elvts[idx];
465 KASSERT(elvt->lvt_active, ("%s: ELVT%u is not active", __func__, idx));
466 KASSERT(elvt->lvt_edgetrigger,
467 ("%s: ELVT%u is not edge triggered", __func__, idx));
468 KASSERT(elvt->lvt_activehi,
469 ("%s: ELVT%u is not active high", __func__, idx));
470 return (lvt_mode_impl(la, elvt, idx, value));
474 * Map the local APIC and setup necessary interrupt vectors.
477 native_lapic_init(vm_paddr_t addr)
480 uint64_t r, r1, r2, rx;
487 * Enable x2APIC mode if possible. Map the local APIC
490 * Keep the LAPIC registers page mapped uncached for x2APIC
491 * mode too, to have direct map page attribute set to
492 * uncached. This is needed to work around CPU errata present
493 * on all Intel processors.
495 KASSERT(trunc_page(addr) == addr,
496 ("local APIC not aligned on a page boundary"));
498 lapic_map = pmap_mapdev(addr, PAGE_SIZE);
500 native_lapic_enable_x2apic();
504 /* Setup the spurious interrupt handler. */
505 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_APIC, SEL_KPL,
508 /* Perform basic initialization of the BSP's local APIC. */
511 /* Set BSP's per-CPU local APIC ID. */
512 PCPU_SET(apic_id, lapic_id());
514 /* Local APIC timer interrupt. */
515 setidt(APIC_TIMER_INT, pti ? IDTVEC(timerint_pti) : IDTVEC(timerint),
516 SDT_APIC, SEL_KPL, GSEL_APIC);
518 /* Local APIC error interrupt. */
519 setidt(APIC_ERROR_INT, pti ? IDTVEC(errorint_pti) : IDTVEC(errorint),
520 SDT_APIC, SEL_KPL, GSEL_APIC);
522 /* XXX: Thermal interrupt */
524 /* Local APIC CMCI. */
525 setidt(APIC_CMC_INT, pti ? IDTVEC(cmcint_pti) : IDTVEC(cmcint),
526 SDT_APIC, SEL_KPL, GSEL_APIC);
528 if ((resource_int_value("apic", 0, "clock", &i) != 0 || i != 0)) {
529 /* Set if APIC timer runs in C3. */
530 arat = (cpu_power_eax & CPUTPM1_ARAT);
532 bzero(&lapic_et, sizeof(lapic_et));
533 lapic_et.et_name = "LAPIC";
534 lapic_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
536 lapic_et.et_quality = 600;
538 lapic_et.et_flags |= ET_FLAGS_C3STOP;
539 lapic_et.et_quality = 100;
541 if ((cpu_feature & CPUID_TSC) != 0 &&
542 (cpu_feature2 & CPUID2_TSCDLT) != 0 &&
543 tsc_is_invariant && tsc_freq != 0) {
544 lapic_timer_tsc_deadline = 1;
545 TUNABLE_INT_FETCH("hw.lapic_tsc_deadline",
546 &lapic_timer_tsc_deadline);
549 lapic_et.et_frequency = 0;
550 /* We don't know frequency yet, so trying to guess. */
551 lapic_et.et_min_period = 0x00001000LL;
552 lapic_et.et_max_period = SBT_1S;
553 lapic_et.et_start = lapic_et_start;
554 lapic_et.et_stop = lapic_et_stop;
555 lapic_et.et_priv = NULL;
556 et_register(&lapic_et);
560 * Set lapic_eoi_suppression after lapic_enable(), to not
561 * enable suppression in the hardware prematurely. Note that
562 * we by default enable suppression even when system only has
563 * one IO-APIC, since EOI is broadcasted to all APIC agents,
564 * including CPUs, otherwise.
566 * It seems that at least some KVM versions report
567 * EOI_SUPPRESSION bit, but auto-EOI does not work.
569 ver = lapic_read32(LAPIC_VERSION);
570 if ((ver & APIC_VER_EOI_SUPPRESSION) != 0) {
571 lapic_eoi_suppression = 1;
572 if (vm_guest == VM_GUEST_KVM) {
575 "KVM -- disabling lapic eoi suppression\n");
576 lapic_eoi_suppression = 0;
578 TUNABLE_INT_FETCH("hw.lapic_eoi_suppression",
579 &lapic_eoi_suppression);
585 * Calibrate the busy loop waiting for IPI ack in xAPIC mode.
586 * lapic_ipi_wait_mult contains the number of iterations which
587 * approximately delay execution for 1 microsecond (the
588 * argument to native_lapic_ipi_wait() is in microseconds).
590 * We assume that TSC is present and already measured.
591 * Possible TSC frequency jumps are irrelevant to the
592 * calibration loop below, the CPU clock management code is
593 * not yet started, and we do not enter sleep states.
595 KASSERT((cpu_feature & CPUID_TSC) != 0 && tsc_freq != 0,
596 ("TSC not initialized"));
599 for (rx = 0; rx < LOOPS; rx++) {
600 (void)lapic_read_icr_lo();
604 r1 = tsc_freq * LOOPS;
606 lapic_ipi_wait_mult = r1 >= r2 ? r1 / r2 : 1;
608 printf("LAPIC: ipi_wait() us multiplier %ju (r %ju "
609 "tsc %ju)\n", (uintmax_t)lapic_ipi_wait_mult,
610 (uintmax_t)r, (uintmax_t)tsc_freq);
618 * Create a local APIC instance.
621 native_lapic_create(u_int apic_id, int boot_cpu)
625 if (apic_id > max_apic_id) {
626 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
628 panic("Can't ignore BSP");
631 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
635 * Assume no local LVT overrides and a cluster of 0 and
636 * intra-cluster ID of 0.
638 lapics[apic_id].la_present = 1;
639 lapics[apic_id].la_id = apic_id;
640 for (i = 0; i <= APIC_LVT_MAX; i++) {
641 lapics[apic_id].la_lvts[i] = lvts[i];
642 lapics[apic_id].la_lvts[i].lvt_active = 0;
644 for (i = 0; i <= APIC_ELVT_MAX; i++) {
645 lapics[apic_id].la_elvts[i] = elvts[i];
646 lapics[apic_id].la_elvts[i].lvt_active = 0;
648 for (i = 0; i <= APIC_NUM_IOINTS; i++)
649 lapics[apic_id].la_ioint_irqs[i] = IRQ_FREE;
650 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
651 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] =
654 lapics[apic_id].la_ioint_irqs[IDT_DTRACE_RET - APIC_IO_INTS] =
658 lapics[apic_id].la_ioint_irqs[IDT_EVTCHN - APIC_IO_INTS] = IRQ_EVTCHN;
663 cpu_add(apic_id, boot_cpu);
667 static inline uint32_t
668 amd_read_ext_features(void)
672 if (cpu_vendor_id != CPU_VENDOR_AMD)
674 version = lapic_read32(LAPIC_VERSION);
675 if ((version & APIC_VER_AMD_EXT_SPACE) != 0)
676 return (lapic_read32(LAPIC_EXT_FEATURES));
681 static inline uint32_t
682 amd_read_elvt_count(void)
687 extf = amd_read_ext_features();
688 count = (extf & APIC_EXTF_ELVT_MASK) >> APIC_EXTF_ELVT_SHIFT;
689 count = min(count, APIC_ELVT_MAX + 1);
694 * Dump contents of local APIC registers
697 native_lapic_dump(const char* str)
705 version = lapic_read32(LAPIC_VERSION);
706 maxlvt = (version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
707 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
708 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x",
709 lapic_read32(LAPIC_ID), version,
710 lapic_read32(LAPIC_LDR), x2apic_mode ? 0 : lapic_read32(LAPIC_DFR));
711 if ((cpu_feature2 & CPUID2_X2APIC) != 0)
712 printf(" x2APIC: %d", x2apic_mode);
713 printf("\n lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
714 lapic_read32(LAPIC_LVT_LINT0), lapic_read32(LAPIC_LVT_LINT1),
715 lapic_read32(LAPIC_TPR), lapic_read32(LAPIC_SVR));
716 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x",
717 lapic_read32(LAPIC_LVT_TIMER), lapic_read32(LAPIC_LVT_THERMAL),
718 lapic_read32(LAPIC_LVT_ERROR));
719 if (maxlvt >= APIC_LVT_PMC)
720 printf(" pmc: 0x%08x", lapic_read32(LAPIC_LVT_PCINT));
722 if (maxlvt >= APIC_LVT_CMCI)
723 printf(" cmci: 0x%08x\n", lapic_read32(LAPIC_LVT_CMCI));
724 extf = amd_read_ext_features();
726 printf(" AMD ext features: 0x%08x\n", extf);
727 elvt_count = amd_read_elvt_count();
728 for (i = 0; i < elvt_count; i++)
729 printf(" AMD elvt%d: 0x%08x\n", i,
730 lapic_read32(LAPIC_EXT_LVT0 + i));
735 native_lapic_xapic_mode(void)
739 saveintr = intr_disable();
741 native_lapic_enable_x2apic();
742 intr_restore(saveintr);
746 native_lapic_setup(int boot)
755 saveintr = intr_disable();
757 la = &lapics[lapic_id()];
758 KASSERT(la->la_present, ("missing APIC structure"));
759 version = lapic_read32(LAPIC_VERSION);
760 maxlvt = (version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
762 /* Initialize the TPR to allow all interrupts. */
765 /* Setup spurious vector and enable the local APIC. */
768 /* Program LINT[01] LVT entries. */
769 lapic_write32(LAPIC_LVT_LINT0, lvt_mode(la, APIC_LVT_LINT0,
770 lapic_read32(LAPIC_LVT_LINT0)));
771 lapic_write32(LAPIC_LVT_LINT1, lvt_mode(la, APIC_LVT_LINT1,
772 lapic_read32(LAPIC_LVT_LINT1)));
774 /* Program the PMC LVT entry if present. */
775 if (maxlvt >= APIC_LVT_PMC) {
776 lapic_write32(LAPIC_LVT_PCINT, lvt_mode(la, APIC_LVT_PMC,
780 /* Program timer LVT. */
781 la->lvt_timer_base = lvt_mode(la, APIC_LVT_TIMER,
782 lapic_read32(LAPIC_LVT_TIMER));
783 la->lvt_timer_last = la->lvt_timer_base;
784 lapic_write32(LAPIC_LVT_TIMER, la->lvt_timer_base);
786 /* Calibrate the timer parameters using BSP. */
787 if (boot && IS_BSP()) {
788 lapic_calibrate_initcount(la);
789 if (lapic_timer_tsc_deadline)
790 lapic_calibrate_deadline(la);
793 /* Setup the timer if configured. */
794 if (la->la_timer_mode != LAT_MODE_UNDEF) {
795 KASSERT(la->la_timer_period != 0, ("lapic%u: zero divisor",
797 switch (la->la_timer_mode) {
798 case LAT_MODE_PERIODIC:
799 lapic_timer_set_divisor(lapic_timer_divisor);
800 lapic_timer_periodic(la);
802 case LAT_MODE_ONESHOT:
803 lapic_timer_set_divisor(lapic_timer_divisor);
804 lapic_timer_oneshot(la);
806 case LAT_MODE_DEADLINE:
807 lapic_timer_deadline(la);
810 panic("corrupted la_timer_mode %p %d", la,
815 /* Program error LVT and clear any existing errors. */
816 lapic_write32(LAPIC_LVT_ERROR, lvt_mode(la, APIC_LVT_ERROR,
817 lapic_read32(LAPIC_LVT_ERROR)));
818 lapic_write32(LAPIC_ESR, 0);
820 /* XXX: Thermal LVT */
822 /* Program the CMCI LVT entry if present. */
823 if (maxlvt >= APIC_LVT_CMCI) {
824 lapic_write32(LAPIC_LVT_CMCI, lvt_mode(la, APIC_LVT_CMCI,
825 lapic_read32(LAPIC_LVT_CMCI)));
828 elvt_count = amd_read_elvt_count();
829 for (i = 0; i < elvt_count; i++) {
830 if (la->la_elvts[i].lvt_active)
831 lapic_write32(LAPIC_EXT_LVT0 + i,
832 elvt_mode(la, i, lapic_read32(LAPIC_EXT_LVT0 + i)));
835 intr_restore(saveintr);
839 native_lapic_intrcnt(void *dummy __unused)
843 char buf[MAXCOMLEN + 1];
845 /* If there are no APICs, skip this function. */
849 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
850 la = &lapics[pc->pc_apic_id];
854 snprintf(buf, sizeof(buf), "cpu%d:timer", pc->pc_cpuid);
855 intrcnt_add(buf, &la->la_timer_count);
858 SYSINIT(native_lapic_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, native_lapic_intrcnt,
862 native_lapic_reenable_pmc(void)
867 value = lapic_read32(LAPIC_LVT_PCINT);
868 value &= ~APIC_LVT_M;
869 lapic_write32(LAPIC_LVT_PCINT, value);
875 lapic_update_pmc(void *dummy)
879 la = &lapics[lapic_id()];
880 lapic_write32(LAPIC_LVT_PCINT, lvt_mode(la, APIC_LVT_PMC,
881 lapic_read32(LAPIC_LVT_PCINT)));
886 native_lapic_enable_pmc(void)
891 /* Fail if the local APIC is not present. */
892 if (!x2apic_mode && lapic_map == NULL)
895 /* Fail if the PMC LVT is not present. */
896 maxlvt = (lapic_read32(LAPIC_VERSION) & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
897 if (maxlvt < APIC_LVT_PMC)
900 lvts[APIC_LVT_PMC].lvt_masked = 0;
902 #ifdef EARLY_AP_STARTUP
903 MPASS(mp_ncpus == 1 || smp_started);
904 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
908 * If hwpmc was loaded at boot time then the APs may not be
909 * started yet. In that case, don't forward the request to
910 * them as they will program the lvt when they start.
913 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
916 lapic_update_pmc(NULL);
925 native_lapic_disable_pmc(void)
930 /* Fail if the local APIC is not present. */
931 if (!x2apic_mode && lapic_map == NULL)
934 /* Fail if the PMC LVT is not present. */
935 maxlvt = (lapic_read32(LAPIC_VERSION) & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
936 if (maxlvt < APIC_LVT_PMC)
939 lvts[APIC_LVT_PMC].lvt_masked = 1;
942 /* The APs should always be started when hwpmc is unloaded. */
943 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early"));
945 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
950 lapic_calibrate_initcount(struct lapic *la)
954 /* Start off with a divisor of 2 (power on reset default). */
955 lapic_timer_divisor = 2;
956 /* Try to calibrate the local APIC timer. */
958 lapic_timer_set_divisor(lapic_timer_divisor);
959 lapic_timer_oneshot_nointr(la, APIC_TIMER_MAX_COUNT);
961 value = APIC_TIMER_MAX_COUNT - lapic_read32(LAPIC_CCR_TIMER);
962 if (value != APIC_TIMER_MAX_COUNT)
964 lapic_timer_divisor <<= 1;
965 } while (lapic_timer_divisor <= 128);
966 if (lapic_timer_divisor > 128)
967 panic("lapic: Divisor too big");
969 printf("lapic: Divisor %lu, Frequency %lu Hz\n",
970 lapic_timer_divisor, value);
976 lapic_calibrate_deadline(struct lapic *la __unused)
980 printf("lapic: deadline tsc mode, Frequency %ju Hz\n",
981 (uintmax_t)tsc_freq);
986 lapic_change_mode(struct eventtimer *et, struct lapic *la,
987 enum lat_timer_mode newmode)
990 if (la->la_timer_mode == newmode)
993 case LAT_MODE_PERIODIC:
994 lapic_timer_set_divisor(lapic_timer_divisor);
995 et->et_frequency = count_freq;
997 case LAT_MODE_DEADLINE:
998 et->et_frequency = tsc_freq;
1000 case LAT_MODE_ONESHOT:
1001 lapic_timer_set_divisor(lapic_timer_divisor);
1002 et->et_frequency = count_freq;
1005 panic("lapic_change_mode %d", newmode);
1007 la->la_timer_mode = newmode;
1008 et->et_min_period = (0x00000002LLU << 32) / et->et_frequency;
1009 et->et_max_period = (0xfffffffeLLU << 32) / et->et_frequency;
1013 lapic_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
1017 la = &lapics[PCPU_GET(apic_id)];
1019 lapic_change_mode(et, la, LAT_MODE_PERIODIC);
1020 la->la_timer_period = ((uint32_t)et->et_frequency * period) >>
1022 lapic_timer_periodic(la);
1023 } else if (lapic_timer_tsc_deadline) {
1024 lapic_change_mode(et, la, LAT_MODE_DEADLINE);
1025 la->la_timer_period = (et->et_frequency * first) >> 32;
1026 lapic_timer_deadline(la);
1028 lapic_change_mode(et, la, LAT_MODE_ONESHOT);
1029 la->la_timer_period = ((uint32_t)et->et_frequency * first) >>
1031 lapic_timer_oneshot(la);
1037 lapic_et_stop(struct eventtimer *et)
1041 la = &lapics[PCPU_GET(apic_id)];
1042 lapic_timer_stop(la);
1043 la->la_timer_mode = LAT_MODE_UNDEF;
1048 native_lapic_disable(void)
1052 /* Software disable the local APIC. */
1053 value = lapic_read32(LAPIC_SVR);
1054 value &= ~APIC_SVR_SWEN;
1055 lapic_write32(LAPIC_SVR, value);
1063 /* Program the spurious vector to enable the local APIC. */
1064 value = lapic_read32(LAPIC_SVR);
1065 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
1066 value |= APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT;
1067 if (lapic_eoi_suppression)
1068 value |= APIC_SVR_EOI_SUPPRESSION;
1069 lapic_write32(LAPIC_SVR, value);
1072 /* Reset the local APIC on the BSP during resume. */
1074 lapic_resume(struct pic *pic, bool suspend_cancelled)
1081 native_lapic_id(void)
1085 KASSERT(x2apic_mode || lapic_map != NULL, ("local APIC is not mapped"));
1086 v = lapic_read32(LAPIC_ID);
1088 v >>= APIC_ID_SHIFT;
1093 native_lapic_intr_pending(u_int vector)
1098 * The IRR registers are an array of registers each of which
1099 * only describes 32 interrupts in the low 32 bits. Thus, we
1100 * divide the vector by 32 to get the register index.
1101 * Finally, we modulus the vector by 32 to determine the
1102 * individual bit to test.
1104 irr = lapic_read32(LAPIC_IRR0 + vector / 32);
1105 return (irr & 1 << (vector % 32));
1109 native_lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
1113 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
1114 __func__, apic_id));
1115 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
1116 __func__, cluster));
1117 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
1118 ("%s: intra cluster id %u too big", __func__, cluster_id));
1119 la = &lapics[apic_id];
1120 la->la_cluster = cluster;
1121 la->la_cluster_id = cluster_id;
1125 native_lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
1128 if (pin > APIC_LVT_MAX)
1130 if (apic_id == APIC_ID_ALL) {
1131 lvts[pin].lvt_masked = masked;
1135 KASSERT(lapics[apic_id].la_present,
1136 ("%s: missing APIC %u", __func__, apic_id));
1137 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
1138 lapics[apic_id].la_lvts[pin].lvt_active = 1;
1140 printf("lapic%u:", apic_id);
1143 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
1148 native_lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
1152 if (pin > APIC_LVT_MAX)
1154 if (apic_id == APIC_ID_ALL) {
1159 KASSERT(lapics[apic_id].la_present,
1160 ("%s: missing APIC %u", __func__, apic_id));
1161 lvt = &lapics[apic_id].la_lvts[pin];
1162 lvt->lvt_active = 1;
1164 printf("lapic%u:", apic_id);
1166 lvt->lvt_mode = mode;
1168 case APIC_LVT_DM_NMI:
1169 case APIC_LVT_DM_SMI:
1170 case APIC_LVT_DM_INIT:
1171 case APIC_LVT_DM_EXTINT:
1172 lvt->lvt_edgetrigger = 1;
1173 lvt->lvt_activehi = 1;
1174 if (mode == APIC_LVT_DM_EXTINT)
1175 lvt->lvt_masked = 1;
1177 lvt->lvt_masked = 0;
1180 panic("Unsupported delivery mode: 0x%x\n", mode);
1183 printf(" Routing ");
1185 case APIC_LVT_DM_NMI:
1188 case APIC_LVT_DM_SMI:
1191 case APIC_LVT_DM_INIT:
1194 case APIC_LVT_DM_EXTINT:
1198 printf(" -> LINT%u\n", pin);
1204 native_lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
1207 if (pin > APIC_LVT_MAX || pol == INTR_POLARITY_CONFORM)
1209 if (apic_id == APIC_ID_ALL) {
1210 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
1214 KASSERT(lapics[apic_id].la_present,
1215 ("%s: missing APIC %u", __func__, apic_id));
1216 lapics[apic_id].la_lvts[pin].lvt_active = 1;
1217 lapics[apic_id].la_lvts[pin].lvt_activehi =
1218 (pol == INTR_POLARITY_HIGH);
1220 printf("lapic%u:", apic_id);
1223 printf(" LINT%u polarity: %s\n", pin,
1224 pol == INTR_POLARITY_HIGH ? "high" : "low");
1229 native_lapic_set_lvt_triggermode(u_int apic_id, u_int pin,
1230 enum intr_trigger trigger)
1233 if (pin > APIC_LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
1235 if (apic_id == APIC_ID_ALL) {
1236 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
1240 KASSERT(lapics[apic_id].la_present,
1241 ("%s: missing APIC %u", __func__, apic_id));
1242 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
1243 (trigger == INTR_TRIGGER_EDGE);
1244 lapics[apic_id].la_lvts[pin].lvt_active = 1;
1246 printf("lapic%u:", apic_id);
1249 printf(" LINT%u trigger: %s\n", pin,
1250 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
1255 * Adjust the TPR of the current CPU so that it blocks all interrupts below
1256 * the passed in vector.
1259 lapic_set_tpr(u_int vector)
1262 lapic_write32(LAPIC_TPR, vector);
1266 tpr = lapic_read32(LAPIC_TPR) & ~APIC_TPR_PRIO;
1268 lapic_write32(LAPIC_TPR, tpr);
1273 native_lapic_eoi(void)
1276 lapic_write32_nofence(LAPIC_EOI, 0);
1280 lapic_handle_intr(int vector, struct trapframe *frame)
1282 struct intsrc *isrc;
1284 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id),
1286 intr_execute_handlers(isrc, frame);
1290 lapic_handle_timer(struct trapframe *frame)
1293 struct trapframe *oldframe;
1296 /* Send EOI first thing. */
1299 #if defined(SMP) && !defined(SCHED_ULE)
1301 * Don't do any accounting for the disabled HTT cores, since it
1302 * will provide misleading numbers for the userland.
1304 * No locking is necessary here, since even if we lose the race
1305 * when hlt_cpus_mask changes it is not a big deal, really.
1307 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
1308 * and unlike other schedulers it actually schedules threads to
1311 if (CPU_ISSET(PCPU_GET(cpuid), &hlt_cpus_mask))
1315 /* Look up our local APIC structure for the tick counters. */
1316 la = &lapics[PCPU_GET(apic_id)];
1317 (*la->la_timer_count)++;
1319 if (lapic_et.et_active) {
1321 td->td_intr_nesting_level++;
1322 oldframe = td->td_intr_frame;
1323 td->td_intr_frame = frame;
1324 lapic_et.et_event_cb(&lapic_et, lapic_et.et_arg);
1325 td->td_intr_frame = oldframe;
1326 td->td_intr_nesting_level--;
1332 lapic_timer_set_divisor(u_int divisor)
1335 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
1336 KASSERT(ffs(divisor) <= nitems(lapic_timer_divisors),
1337 ("lapic: invalid divisor %u", divisor));
1338 lapic_write32(LAPIC_DCR_TIMER, lapic_timer_divisors[ffs(divisor) - 1]);
1342 lapic_timer_oneshot(struct lapic *la)
1346 value = la->lvt_timer_base;
1347 value &= ~(APIC_LVTT_TM | APIC_LVT_M);
1348 value |= APIC_LVTT_TM_ONE_SHOT;
1349 la->lvt_timer_last = value;
1350 lapic_write32(LAPIC_LVT_TIMER, value);
1351 lapic_write32(LAPIC_ICR_TIMER, la->la_timer_period);
1355 lapic_timer_oneshot_nointr(struct lapic *la, uint32_t count)
1359 value = la->lvt_timer_base;
1360 value &= ~APIC_LVTT_TM;
1361 value |= APIC_LVTT_TM_ONE_SHOT | APIC_LVT_M;
1362 la->lvt_timer_last = value;
1363 lapic_write32(LAPIC_LVT_TIMER, value);
1364 lapic_write32(LAPIC_ICR_TIMER, count);
1368 lapic_timer_periodic(struct lapic *la)
1372 value = la->lvt_timer_base;
1373 value &= ~(APIC_LVTT_TM | APIC_LVT_M);
1374 value |= APIC_LVTT_TM_PERIODIC;
1375 la->lvt_timer_last = value;
1376 lapic_write32(LAPIC_LVT_TIMER, value);
1377 lapic_write32(LAPIC_ICR_TIMER, la->la_timer_period);
1381 lapic_timer_deadline(struct lapic *la)
1385 value = la->lvt_timer_base;
1386 value &= ~(APIC_LVTT_TM | APIC_LVT_M);
1387 value |= APIC_LVTT_TM_TSCDLT;
1388 if (value != la->lvt_timer_last) {
1389 la->lvt_timer_last = value;
1390 lapic_write32_nofence(LAPIC_LVT_TIMER, value);
1394 wrmsr(MSR_TSC_DEADLINE, la->la_timer_period + rdtsc());
1398 lapic_timer_stop(struct lapic *la)
1402 if (la->la_timer_mode == LAT_MODE_DEADLINE) {
1403 wrmsr(MSR_TSC_DEADLINE, 0);
1406 value = la->lvt_timer_base;
1407 value &= ~APIC_LVTT_TM;
1408 value |= APIC_LVT_M;
1409 la->lvt_timer_last = value;
1410 lapic_write32(LAPIC_LVT_TIMER, value);
1415 lapic_handle_cmc(void)
1423 * Called from the mca_init() to activate the CMC interrupt if this CPU is
1424 * responsible for monitoring any MC banks for CMC events. Since mca_init()
1425 * is called prior to lapic_setup() during boot, this just needs to unmask
1426 * this CPU's LVT_CMCI entry.
1429 native_lapic_enable_cmc(void)
1434 if (!x2apic_mode && lapic_map == NULL)
1437 apic_id = PCPU_GET(apic_id);
1438 KASSERT(lapics[apic_id].la_present,
1439 ("%s: missing APIC %u", __func__, apic_id));
1440 lapics[apic_id].la_lvts[APIC_LVT_CMCI].lvt_masked = 0;
1441 lapics[apic_id].la_lvts[APIC_LVT_CMCI].lvt_active = 1;
1443 printf("lapic%u: CMCI unmasked\n", apic_id);
1447 native_lapic_enable_mca_elvt(void)
1454 if (lapic_map == NULL)
1458 apic_id = PCPU_GET(apic_id);
1459 KASSERT(lapics[apic_id].la_present,
1460 ("%s: missing APIC %u", __func__, apic_id));
1461 elvt_count = amd_read_elvt_count();
1462 if (elvt_count <= APIC_ELVT_MCA)
1465 value = lapic_read32(LAPIC_EXT_LVT0 + APIC_ELVT_MCA);
1466 if ((value & APIC_LVT_M) == 0) {
1468 printf("AMD MCE Thresholding Extended LVT is already active\n");
1469 return (APIC_ELVT_MCA);
1471 lapics[apic_id].la_elvts[APIC_ELVT_MCA].lvt_masked = 0;
1472 lapics[apic_id].la_elvts[APIC_ELVT_MCA].lvt_active = 1;
1474 printf("lapic%u: MCE Thresholding ELVT unmasked\n", apic_id);
1475 return (APIC_ELVT_MCA);
1479 lapic_handle_error(void)
1484 * Read the contents of the error status register. Write to
1485 * the register first before reading from it to force the APIC
1486 * to update its value to indicate any errors that have
1487 * occurred since the previous write to the register.
1489 lapic_write32(LAPIC_ESR, 0);
1490 esr = lapic_read32(LAPIC_ESR);
1492 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr);
1497 native_apic_cpuid(u_int apic_id)
1500 return apic_cpuids[apic_id];
1506 /* Request a free IDT vector to be used by the specified IRQ. */
1508 native_apic_alloc_vector(u_int apic_id, u_int irq)
1512 KASSERT(irq < num_io_irqs, ("Invalid IRQ %u", irq));
1515 * Search for a free vector. Currently we just use a very simple
1516 * algorithm to find the first free vector.
1518 mtx_lock_spin(&icu_lock);
1519 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
1520 if (lapics[apic_id].la_ioint_irqs[vector] != IRQ_FREE)
1522 lapics[apic_id].la_ioint_irqs[vector] = irq;
1523 mtx_unlock_spin(&icu_lock);
1524 return (vector + APIC_IO_INTS);
1526 mtx_unlock_spin(&icu_lock);
1531 * Request 'count' free contiguous IDT vectors to be used by 'count'
1532 * IRQs. 'count' must be a power of two and the vectors will be
1533 * aligned on a boundary of 'align'. If the request cannot be
1534 * satisfied, 0 is returned.
1537 native_apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
1539 u_int first, run, vector;
1541 KASSERT(powerof2(count), ("bad count"));
1542 KASSERT(powerof2(align), ("bad align"));
1543 KASSERT(align >= count, ("align < count"));
1545 for (run = 0; run < count; run++)
1546 KASSERT(irqs[run] < num_io_irqs, ("Invalid IRQ %u at index %u",
1551 * Search for 'count' free vectors. As with apic_alloc_vector(),
1552 * this just uses a simple first fit algorithm.
1556 mtx_lock_spin(&icu_lock);
1557 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
1559 /* Vector is in use, end run. */
1560 if (lapics[apic_id].la_ioint_irqs[vector] != IRQ_FREE) {
1566 /* Start a new run if run == 0 and vector is aligned. */
1568 if ((vector & (align - 1)) != 0)
1574 /* Keep looping if the run isn't long enough yet. */
1578 /* Found a run, assign IRQs and return the first vector. */
1579 for (vector = 0; vector < count; vector++)
1580 lapics[apic_id].la_ioint_irqs[first + vector] =
1582 mtx_unlock_spin(&icu_lock);
1583 return (first + APIC_IO_INTS);
1585 mtx_unlock_spin(&icu_lock);
1586 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
1591 * Enable a vector for a particular apic_id. Since all lapics share idt
1592 * entries and ioint_handlers this enables the vector on all lapics. lapics
1593 * which do not have the vector configured would report spurious interrupts
1597 native_apic_enable_vector(u_int apic_id, u_int vector)
1600 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1601 KASSERT(ioint_handlers[vector / 32] != NULL,
1602 ("No ISR handler for vector %u", vector));
1603 #ifdef KDTRACE_HOOKS
1604 KASSERT(vector != IDT_DTRACE_RET,
1605 ("Attempt to overwrite DTrace entry"));
1607 setidt(vector, (pti ? ioint_pti_handlers : ioint_handlers)[vector / 32],
1608 SDT_APIC, SEL_KPL, GSEL_APIC);
1612 native_apic_disable_vector(u_int apic_id, u_int vector)
1615 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1616 #ifdef KDTRACE_HOOKS
1617 KASSERT(vector != IDT_DTRACE_RET,
1618 ("Attempt to overwrite DTrace entry"));
1620 KASSERT(ioint_handlers[vector / 32] != NULL,
1621 ("No ISR handler for vector %u", vector));
1624 * We can not currently clear the idt entry because other cpus
1625 * may have a valid vector at this offset.
1627 setidt(vector, pti ? &IDTVEC(rsvd_pti) : &IDTVEC(rsvd), SDT_APIC,
1628 SEL_KPL, GSEL_APIC);
1632 /* Release an APIC vector when it's no longer in use. */
1634 native_apic_free_vector(u_int apic_id, u_int vector, u_int irq)
1638 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1639 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1640 ("Vector %u does not map to an IRQ line", vector));
1641 KASSERT(irq < num_io_irqs, ("Invalid IRQ %u", irq));
1642 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] ==
1643 irq, ("IRQ mismatch"));
1644 #ifdef KDTRACE_HOOKS
1645 KASSERT(vector != IDT_DTRACE_RET,
1646 ("Attempt to overwrite DTrace entry"));
1650 * Bind us to the cpu that owned the vector before freeing it so
1651 * we don't lose an interrupt delivery race.
1656 if (sched_is_bound(td))
1657 panic("apic_free_vector: Thread already bound.\n");
1658 sched_bind(td, apic_cpuid(apic_id));
1661 mtx_lock_spin(&icu_lock);
1662 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = IRQ_FREE;
1663 mtx_unlock_spin(&icu_lock);
1671 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
1673 apic_idt_to_irq(u_int apic_id, u_int vector)
1677 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1678 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1679 ("Vector %u does not map to an IRQ line", vector));
1680 #ifdef KDTRACE_HOOKS
1681 KASSERT(vector != IDT_DTRACE_RET,
1682 ("Attempt to overwrite DTrace entry"));
1684 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS];
1692 * Dump data about APIC IDT vector mappings.
1694 DB_SHOW_COMMAND(apic, db_show_apic)
1696 struct intsrc *isrc;
1701 if (strcmp(modif, "vv") == 0)
1703 else if (strcmp(modif, "v") == 0)
1707 for (apic_id = 0; apic_id <= max_apic_id; apic_id++) {
1708 if (lapics[apic_id].la_present == 0)
1710 db_printf("Interrupts bound to lapic %u\n", apic_id);
1711 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
1712 irq = lapics[apic_id].la_ioint_irqs[i];
1713 if (irq == IRQ_FREE || irq == IRQ_SYSCALL)
1715 #ifdef KDTRACE_HOOKS
1716 if (irq == IRQ_DTRACE_RET)
1720 if (irq == IRQ_EVTCHN)
1723 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
1724 if (irq == IRQ_TIMER)
1725 db_printf("lapic timer\n");
1726 else if (irq < num_io_irqs) {
1727 isrc = intr_lookup_source(irq);
1728 if (isrc == NULL || verbose == 0)
1729 db_printf("IRQ %u\n", irq);
1731 db_dump_intr_event(isrc->is_event,
1734 db_printf("IRQ %u ???\n", irq);
1740 dump_mask(const char *prefix, uint32_t v, int base)
1745 for (i = 0; i < 32; i++)
1748 db_printf("%s:", prefix);
1751 db_printf(" %02x", base + i);
1757 /* Show info from the lapic regs for this CPU. */
1758 DB_SHOW_COMMAND(lapic, db_show_lapic)
1762 db_printf("lapic ID = %d\n", lapic_id());
1763 v = lapic_read32(LAPIC_VERSION);
1764 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
1766 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
1767 v = lapic_read32(LAPIC_SVR);
1768 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
1769 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
1770 db_printf("TPR = %02x\n", lapic_read32(LAPIC_TPR));
1772 #define dump_field(prefix, regn, index) \
1773 dump_mask(__XSTRING(prefix ## index), \
1774 lapic_read32(LAPIC_ ## regn ## index), \
1777 db_printf("In-service Interrupts:\n");
1778 dump_field(isr, ISR, 0);
1779 dump_field(isr, ISR, 1);
1780 dump_field(isr, ISR, 2);
1781 dump_field(isr, ISR, 3);
1782 dump_field(isr, ISR, 4);
1783 dump_field(isr, ISR, 5);
1784 dump_field(isr, ISR, 6);
1785 dump_field(isr, ISR, 7);
1787 db_printf("TMR Interrupts:\n");
1788 dump_field(tmr, TMR, 0);
1789 dump_field(tmr, TMR, 1);
1790 dump_field(tmr, TMR, 2);
1791 dump_field(tmr, TMR, 3);
1792 dump_field(tmr, TMR, 4);
1793 dump_field(tmr, TMR, 5);
1794 dump_field(tmr, TMR, 6);
1795 dump_field(tmr, TMR, 7);
1797 db_printf("IRR Interrupts:\n");
1798 dump_field(irr, IRR, 0);
1799 dump_field(irr, IRR, 1);
1800 dump_field(irr, IRR, 2);
1801 dump_field(irr, IRR, 3);
1802 dump_field(irr, IRR, 4);
1803 dump_field(irr, IRR, 5);
1804 dump_field(irr, IRR, 6);
1805 dump_field(irr, IRR, 7);
1812 * APIC probing support code. This includes code to manage enumerators.
1815 static SLIST_HEAD(, apic_enumerator) enumerators =
1816 SLIST_HEAD_INITIALIZER(enumerators);
1817 static struct apic_enumerator *best_enum;
1820 apic_register_enumerator(struct apic_enumerator *enumerator)
1823 struct apic_enumerator *apic_enum;
1825 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1826 if (apic_enum == enumerator)
1827 panic("%s: Duplicate register of %s", __func__,
1828 enumerator->apic_name);
1831 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1835 * We have to look for CPU's very, very early because certain subsystems
1836 * want to know how many CPU's we have extremely early on in the boot
1840 apic_init(void *dummy __unused)
1842 struct apic_enumerator *enumerator;
1845 /* We only support built in local APICs. */
1846 if (!(cpu_feature & CPUID_APIC))
1849 /* Don't probe if APIC mode is disabled. */
1850 if (resource_disabled("apic", 0))
1853 /* Probe all the enumerators to find the best match. */
1856 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1857 retval = enumerator->apic_probe();
1860 if (best_enum == NULL || best < retval) {
1861 best_enum = enumerator;
1865 if (best_enum == NULL) {
1867 printf("APIC: Could not find any APICs.\n");
1869 panic("running without device atpic requires a local APIC");
1875 printf("APIC: Using the %s enumerator.\n",
1876 best_enum->apic_name);
1880 * To work around an errata, we disable the local APIC on some
1881 * CPUs during early startup. We need to turn the local APIC back
1882 * on on such CPUs now.
1884 ppro_reenable_apic();
1887 /* Probe the CPU's in the system. */
1888 retval = best_enum->apic_probe_cpus();
1890 printf("%s: Failed to probe CPUs: returned %d\n",
1891 best_enum->apic_name, retval);
1894 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL);
1897 * Setup the local APIC. We have to do this prior to starting up the APs
1901 apic_setup_local(void *dummy __unused)
1905 if (best_enum == NULL)
1908 lapics = malloc(sizeof(*lapics) * (max_apic_id + 1), M_LAPIC,
1911 /* Initialize the local APIC. */
1912 retval = best_enum->apic_setup_local();
1914 printf("%s: Failed to setup the local APIC: returned %d\n",
1915 best_enum->apic_name, retval);
1917 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local, NULL);
1920 * Setup the I/O APICs.
1923 apic_setup_io(void *dummy __unused)
1927 if (best_enum == NULL)
1931 * Local APIC must be registered before other PICs and pseudo PICs
1932 * for proper suspend/resume order.
1934 intr_register_pic(&lapic_pic);
1936 retval = best_enum->apic_setup_io();
1938 printf("%s: Failed to setup I/O APICs: returned %d\n",
1939 best_enum->apic_name, retval);
1942 * Finish setting up the local APIC on the BSP once we know
1943 * how to properly program the LINT pins. In particular, this
1944 * enables the EOI suppression mode, if LAPIC supports it and
1945 * user did not disable the mode.
1951 /* Enable the MSI "pic". */
1952 init_ops.msi_init();
1955 xen_intr_alloc_irqs();
1958 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_THIRD, apic_setup_io, NULL);
1962 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1963 * private to the MD code. The public interface for the rest of the
1964 * kernel is defined in mp_machdep.c.
1968 * Wait delay microseconds for IPI to be sent. If delay is -1, we
1972 native_lapic_ipi_wait(int delay)
1976 /* LAPIC_ICR.APIC_DELSTAT_MASK is undefined in x2APIC mode */
1980 for (rx = 0; delay == -1 || rx < lapic_ipi_wait_mult * delay; rx++) {
1981 if ((lapic_read_icr_lo() & APIC_DELSTAT_MASK) ==
1990 native_lapic_ipi_raw(register_t icrlo, u_int dest)
1994 register_t saveintr;
1996 /* XXX: Need more sanity checking of icrlo? */
1997 KASSERT(x2apic_mode || lapic_map != NULL,
1998 ("%s called too early", __func__));
1999 KASSERT(x2apic_mode ||
2000 (dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
2001 ("%s: invalid dest field", __func__));
2002 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
2003 ("%s: reserved bits set in ICR LO register", __func__));
2005 /* Set destination in ICR HI register if it is being used. */
2007 saveintr = intr_disable();
2008 icr = lapic_read_icr();
2011 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
2016 vhi &= ~APIC_ID_MASK;
2017 vhi |= dest << APIC_ID_SHIFT;
2023 /* Program the contents of the IPI and dispatch it. */
2028 vlo &= APIC_ICRLO_RESV_MASK;
2031 lapic_write_icr(vhi, vlo);
2033 intr_restore(saveintr);
2036 #define BEFORE_SPIN 50000
2037 #ifdef DETECT_DEADLOCK
2038 #define AFTER_SPIN 50
2042 native_lapic_ipi_vectored(u_int vector, int dest)
2044 register_t icrlo, destfield;
2046 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
2047 ("%s: invalid vector %d", __func__, vector));
2049 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE | APIC_LEVEL_ASSERT;
2052 * NMI IPIs are just fake vectors used to send a NMI. Use special rules
2053 * regarding NMIs if passed, otherwise specify the vector.
2055 if (vector >= IPI_NMI_FIRST)
2056 icrlo |= APIC_DELMODE_NMI;
2058 icrlo |= vector | APIC_DELMODE_FIXED;
2061 case APIC_IPI_DEST_SELF:
2062 icrlo |= APIC_DEST_SELF;
2064 case APIC_IPI_DEST_ALL:
2065 icrlo |= APIC_DEST_ALLISELF;
2067 case APIC_IPI_DEST_OTHERS:
2068 icrlo |= APIC_DEST_ALLESELF;
2071 KASSERT(x2apic_mode ||
2072 (dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
2073 ("%s: invalid destination 0x%x", __func__, dest));
2077 /* Wait for an earlier IPI to finish. */
2078 if (!lapic_ipi_wait(BEFORE_SPIN)) {
2079 if (panicstr != NULL)
2082 panic("APIC: Previous IPI is stuck");
2085 lapic_ipi_raw(icrlo, destfield);
2087 #ifdef DETECT_DEADLOCK
2088 /* Wait for IPI to be delivered. */
2089 if (!lapic_ipi_wait(AFTER_SPIN)) {
2090 #ifdef needsattention
2094 * The above function waits for the message to actually be
2095 * delivered. It breaks out after an arbitrary timeout
2096 * since the message should eventually be delivered (at
2097 * least in theory) and that if it wasn't we would catch
2098 * the failure with the check above when the next IPI is
2101 * We could skip this wait entirely, EXCEPT it probably
2102 * protects us from other routines that assume that the
2103 * message was delivered and acted upon when this function
2106 printf("APIC: IPI might be stuck\n");
2107 #else /* !needsattention */
2108 /* Wait until mesage is sent without a timeout. */
2109 while (lapic_read_icr_lo() & APIC_DELSTAT_PEND)
2111 #endif /* needsattention */
2113 #endif /* DETECT_DEADLOCK */
2119 * Since the IDT is shared by all CPUs the IPI slot update needs to be globally
2122 * Consider the case where an IPI is generated immediately after allocation:
2123 * vector = lapic_ipi_alloc(ipifunc);
2124 * ipi_selected(other_cpus, vector);
2126 * In xAPIC mode a write to ICR_LO has serializing semantics because the
2127 * APIC page is mapped as an uncached region. In x2APIC mode there is an
2128 * explicit 'mfence' before the ICR MSR is written. Therefore in both cases
2129 * the IDT slot update is globally visible before the IPI is delivered.
2132 native_lapic_ipi_alloc(inthand_t *ipifunc)
2134 struct gate_descriptor *ip;
2138 KASSERT(ipifunc != &IDTVEC(rsvd) && ipifunc != &IDTVEC(rsvd_pti),
2139 ("invalid ipifunc %p", ipifunc));
2142 mtx_lock_spin(&icu_lock);
2143 for (idx = IPI_DYN_FIRST; idx <= IPI_DYN_LAST; idx++) {
2145 func = (ip->gd_hioffset << 16) | ip->gd_looffset;
2146 if ((!pti && func == (uintptr_t)&IDTVEC(rsvd)) ||
2147 (pti && func == (uintptr_t)&IDTVEC(rsvd_pti))) {
2149 setidt(vector, ipifunc, SDT_APIC, SEL_KPL, GSEL_APIC);
2153 mtx_unlock_spin(&icu_lock);
2158 native_lapic_ipi_free(int vector)
2160 struct gate_descriptor *ip;
2163 KASSERT(vector >= IPI_DYN_FIRST && vector <= IPI_DYN_LAST,
2164 ("%s: invalid vector %d", __func__, vector));
2166 mtx_lock_spin(&icu_lock);
2168 func = (ip->gd_hioffset << 16) | ip->gd_looffset;
2169 KASSERT(func != (uintptr_t)&IDTVEC(rsvd) &&
2170 func != (uintptr_t)&IDTVEC(rsvd_pti),
2171 ("invalid idtfunc %#lx", func));
2172 setidt(vector, pti ? &IDTVEC(rsvd_pti) : &IDTVEC(rsvd), SDT_APIC,
2173 SEL_KPL, GSEL_APIC);
2174 mtx_unlock_spin(&icu_lock);