2 * Copyright (c) 2009 Hudson River Trading LLC
3 * Written by: John H. Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Support for x86 machine check architecture.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
43 #include <sys/interrupt.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/mutex.h>
49 #include <sys/sched.h>
51 #include <sys/sysctl.h>
52 #include <sys/systm.h>
53 #include <sys/taskqueue.h>
54 #include <machine/intr_machdep.h>
55 #include <x86/apicvar.h>
56 #include <machine/cpu.h>
57 #include <machine/cputypes.h>
59 #include <machine/md_var.h>
60 #include <machine/specialreg.h>
62 /* Modes for mca_scan() */
71 * State maintained for each monitored MCx bank to control the
72 * corrected machine check interrupt threshold.
86 struct mca_record rec;
88 STAILQ_ENTRY(mca_internal) link;
91 static MALLOC_DEFINE(M_MCA, "MCA", "Machine Check Architecture");
93 static volatile int mca_count; /* Number of records stored. */
94 static int mca_banks; /* Number of per-CPU register banks. */
96 static SYSCTL_NODE(_hw, OID_AUTO, mca, CTLFLAG_RD, NULL,
97 "Machine Check Architecture");
99 static int mca_enabled = 1;
100 SYSCTL_INT(_hw_mca, OID_AUTO, enabled, CTLFLAG_RDTUN, &mca_enabled, 0,
101 "Administrative toggle for machine check support");
103 static int amd10h_L1TP = 1;
104 SYSCTL_INT(_hw_mca, OID_AUTO, amd10h_L1TP, CTLFLAG_RDTUN, &amd10h_L1TP, 0,
105 "Administrative toggle for logging of level one TLB parity (L1TP) errors");
107 static int intel6h_HSD131;
108 SYSCTL_INT(_hw_mca, OID_AUTO, intel6h_HSD131, CTLFLAG_RDTUN, &intel6h_HSD131, 0,
109 "Administrative toggle for logging of spurious corrected errors");
111 int workaround_erratum383;
112 SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RDTUN,
113 &workaround_erratum383, 0,
114 "Is the workaround for Erratum 383 on AMD Family 10h processors enabled?");
116 static STAILQ_HEAD(, mca_internal) mca_freelist;
117 static int mca_freecount;
118 static STAILQ_HEAD(, mca_internal) mca_records;
119 static struct callout mca_timer;
120 static int mca_ticks = 3600; /* Check hourly by default. */
121 static struct taskqueue *mca_tq;
122 static struct task mca_refill_task, mca_scan_task;
123 static struct mtx mca_lock;
126 static struct cmc_state **cmc_state; /* Indexed by cpuid, bank. */
127 static struct amd_et_state *amd_et_state; /* Indexed by cpuid. */
128 static int cmc_throttle = 60; /* Time in seconds to throttle CMCI. */
130 static int amd_elvt = -1;
133 amd_thresholding_supported(void)
135 return (cpu_vendor_id == CPU_VENDOR_AMD &&
136 CPUID_TO_FAMILY(cpu_id) >= 0x10 && CPUID_TO_FAMILY(cpu_id) <= 0x16);
141 sysctl_positive_int(SYSCTL_HANDLER_ARGS)
145 value = *(int *)arg1;
146 error = sysctl_handle_int(oidp, &value, 0, req);
147 if (error || req->newptr == NULL)
151 *(int *)arg1 = value;
156 sysctl_mca_records(SYSCTL_HANDLER_ARGS)
158 int *name = (int *)arg1;
159 u_int namelen = arg2;
160 struct mca_record record;
161 struct mca_internal *rec;
167 if (name[0] < 0 || name[0] >= mca_count)
170 mtx_lock_spin(&mca_lock);
171 if (name[0] >= mca_count) {
172 mtx_unlock_spin(&mca_lock);
176 STAILQ_FOREACH(rec, &mca_records, link) {
183 mtx_unlock_spin(&mca_lock);
184 return (SYSCTL_OUT(req, &record, sizeof(record)));
188 mca_error_ttype(uint16_t mca_error)
191 switch ((mca_error & 0x000c) >> 2) {
203 mca_error_level(uint16_t mca_error)
206 switch (mca_error & 0x0003) {
220 mca_error_request(uint16_t mca_error)
223 switch ((mca_error & 0x00f0) >> 4) {
247 mca_error_mmtype(uint16_t mca_error)
250 switch ((mca_error & 0x70) >> 4) {
266 mca_mute(const struct mca_record *rec)
270 * Skip spurious corrected parity errors generated by Intel Haswell-
271 * and Broadwell-based CPUs (see HSD131, HSM142, HSW131 and BDM48
272 * erratum respectively), unless reporting is enabled.
273 * Note that these errors also have been observed with the D0-stepping
274 * of Haswell, while at least initially the CPU specification updates
275 * suggested only the C0-stepping to be affected. Similarly, Celeron
276 * 2955U with a CPU ID of 0x45 apparently are also concerned with the
277 * same problem, with HSM142 only referring to 0x3c and 0x46.
279 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
280 CPUID_TO_FAMILY(cpu_id) == 0x6 &&
281 (CPUID_TO_MODEL(cpu_id) == 0x3c || /* HSD131, HSM142, HSW131 */
282 CPUID_TO_MODEL(cpu_id) == 0x3d || /* BDM48 */
283 CPUID_TO_MODEL(cpu_id) == 0x45 ||
284 CPUID_TO_MODEL(cpu_id) == 0x46) && /* HSM142 */
286 (rec->mr_status & 0xa0000000ffffffff) == 0x80000000000f0005 &&
293 /* Dump details about a single machine check. */
295 mca_log(const struct mca_record *rec)
302 printf("MCA: Bank %d, Status 0x%016llx\n", rec->mr_bank,
303 (long long)rec->mr_status);
304 printf("MCA: Global Cap 0x%016llx, Status 0x%016llx\n",
305 (long long)rec->mr_mcg_cap, (long long)rec->mr_mcg_status);
306 printf("MCA: Vendor \"%s\", ID 0x%x, APIC ID %d\n", cpu_vendor,
307 rec->mr_cpu_id, rec->mr_apic_id);
308 printf("MCA: CPU %d ", rec->mr_cpu);
309 if (rec->mr_status & MC_STATUS_UC)
313 if (rec->mr_mcg_cap & MCG_CAP_CMCI_P)
314 printf("(%lld) ", ((long long)rec->mr_status &
315 MC_STATUS_COR_COUNT) >> 38);
317 if (rec->mr_status & MC_STATUS_PCC)
319 if (rec->mr_status & MC_STATUS_OVER)
321 mca_error = rec->mr_status & MC_STATUS_MCA_ERROR;
323 /* Simple error codes. */
328 printf("unclassified error");
331 printf("ucode ROM parity error");
334 printf("external error");
340 printf("internal parity error");
343 printf("internal timer error");
346 if ((mca_error & 0xfc00) == 0x0400) {
347 printf("internal error %x", mca_error & 0x03ff);
351 /* Compound error codes. */
353 /* Memory hierarchy error. */
354 if ((mca_error & 0xeffc) == 0x000c) {
355 printf("%s memory error", mca_error_level(mca_error));
360 if ((mca_error & 0xeff0) == 0x0010) {
361 printf("%sTLB %s error", mca_error_ttype(mca_error),
362 mca_error_level(mca_error));
366 /* Memory controller error. */
367 if ((mca_error & 0xef80) == 0x0080) {
368 printf("%s channel ", mca_error_mmtype(mca_error));
369 if ((mca_error & 0x000f) != 0x000f)
370 printf("%d", mca_error & 0x000f);
373 printf(" memory error");
378 if ((mca_error & 0xef00) == 0x0100) {
379 printf("%sCACHE %s %s error",
380 mca_error_ttype(mca_error),
381 mca_error_level(mca_error),
382 mca_error_request(mca_error));
386 /* Bus and/or Interconnect error. */
387 if ((mca_error & 0xe800) == 0x0800) {
388 printf("BUS%s ", mca_error_level(mca_error));
389 switch ((mca_error & 0x0600) >> 9) {
403 printf(" %s ", mca_error_request(mca_error));
404 switch ((mca_error & 0x000c) >> 2) {
418 if (mca_error & 0x0100)
419 printf(" timed out");
423 printf("unknown error %x", mca_error);
427 if (rec->mr_status & MC_STATUS_ADDRV)
428 printf("MCA: Address 0x%llx\n", (long long)rec->mr_addr);
429 if (rec->mr_status & MC_STATUS_MISCV)
430 printf("MCA: Misc 0x%llx\n", (long long)rec->mr_misc);
434 mca_check_status(int bank, struct mca_record *rec)
439 status = rdmsr(MSR_MC_STATUS(bank));
440 if (!(status & MC_STATUS_VAL))
443 /* Save exception information. */
444 rec->mr_status = status;
447 if (status & MC_STATUS_ADDRV)
448 rec->mr_addr = rdmsr(MSR_MC_ADDR(bank));
450 if (status & MC_STATUS_MISCV)
451 rec->mr_misc = rdmsr(MSR_MC_MISC(bank));
452 rec->mr_tsc = rdtsc();
453 rec->mr_apic_id = PCPU_GET(apic_id);
454 rec->mr_mcg_cap = rdmsr(MSR_MCG_CAP);
455 rec->mr_mcg_status = rdmsr(MSR_MCG_STATUS);
456 rec->mr_cpu_id = cpu_id;
457 rec->mr_cpu_vendor_id = cpu_vendor_id;
458 rec->mr_cpu = PCPU_GET(cpuid);
461 * Clear machine check. Don't do this for uncorrectable
462 * errors so that the BIOS can see them.
464 if (!(rec->mr_status & (MC_STATUS_PCC | MC_STATUS_UC))) {
465 wrmsr(MSR_MC_STATUS(bank), 0);
472 mca_fill_freelist(void)
474 struct mca_internal *rec;
478 * Ensure we have at least one record for each bank and one
481 desired = imax(mp_ncpus, mca_banks);
482 mtx_lock_spin(&mca_lock);
483 while (mca_freecount < desired) {
484 mtx_unlock_spin(&mca_lock);
485 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK);
486 mtx_lock_spin(&mca_lock);
487 STAILQ_INSERT_TAIL(&mca_freelist, rec, link);
490 mtx_unlock_spin(&mca_lock);
494 mca_refill(void *context, int pending)
501 mca_record_entry(enum scan_mode mode, const struct mca_record *record)
503 struct mca_internal *rec;
505 if (mode == POLLED) {
506 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK);
507 mtx_lock_spin(&mca_lock);
509 mtx_lock_spin(&mca_lock);
510 rec = STAILQ_FIRST(&mca_freelist);
512 printf("MCA: Unable to allocate space for an event.\n");
514 mtx_unlock_spin(&mca_lock);
517 STAILQ_REMOVE_HEAD(&mca_freelist, link);
523 STAILQ_INSERT_TAIL(&mca_records, rec, link);
525 mtx_unlock_spin(&mca_lock);
526 if (mode == CMCI && !cold)
527 taskqueue_enqueue(mca_tq, &mca_refill_task);
532 * Update the interrupt threshold for a CMCI. The strategy is to use
533 * a low trigger that interrupts as soon as the first event occurs.
534 * However, if a steady stream of events arrive, the threshold is
535 * increased until the interrupts are throttled to once every
536 * cmc_throttle seconds or the periodic scan. If a periodic scan
537 * finds that the threshold is too high, it is lowered.
540 update_threshold(enum scan_mode mode, int valid, int last_intr, int count,
541 int cur_threshold, int max_threshold)
546 delta = (u_int)(time_uptime - last_intr);
547 limit = cur_threshold;
550 * If an interrupt was received less than cmc_throttle seconds
551 * since the previous interrupt and the count from the current
552 * event is greater than or equal to the current threshold,
553 * double the threshold up to the max.
555 if (mode == CMCI && valid) {
556 if (delta < cmc_throttle && count >= limit &&
557 limit < max_threshold) {
558 limit = min(limit << 1, max_threshold);
564 * When the banks are polled, check to see if the threshold
570 /* If a CMCI occured recently, do nothing for now. */
571 if (delta < cmc_throttle)
575 * Compute a new limit based on the average rate of events per
576 * cmc_throttle seconds since the last interrupt.
579 limit = count * cmc_throttle / delta;
582 else if (limit > max_threshold)
583 limit = max_threshold;
591 cmci_update(enum scan_mode mode, int bank, int valid, struct mca_record *rec)
593 struct cmc_state *cc;
595 int cur_threshold, new_threshold;
598 /* Fetch the current limit for this bank. */
599 cc = &cmc_state[PCPU_GET(cpuid)][bank];
600 ctl = rdmsr(MSR_MC_CTL2(bank));
601 count = (rec->mr_status & MC_STATUS_COR_COUNT) >> 38;
602 cur_threshold = ctl & MC_CTL2_THRESHOLD;
604 new_threshold = update_threshold(mode, valid, cc->last_intr, count,
605 cur_threshold, cc->max_threshold);
607 if (mode == CMCI && valid)
608 cc->last_intr = time_uptime;
609 if (new_threshold != cur_threshold) {
610 ctl &= ~MC_CTL2_THRESHOLD;
611 ctl |= new_threshold;
612 wrmsr(MSR_MC_CTL2(bank), ctl);
617 amd_thresholding_update(enum scan_mode mode, int bank, int valid)
619 struct amd_et_state *cc;
624 KASSERT(bank == MC_AMDNB_BANK,
625 ("%s: unexpected bank %d", __func__, bank));
626 cc = &amd_et_state[PCPU_GET(cpuid)];
627 misc = rdmsr(MSR_MC_MISC(bank));
628 count = (misc & MC_MISC_AMDNB_CNT_MASK) >> MC_MISC_AMDNB_CNT_SHIFT;
629 count = count - (MC_MISC_AMDNB_CNT_MAX - cc->cur_threshold);
631 new_threshold = update_threshold(mode, valid, cc->last_intr, count,
632 cc->cur_threshold, MC_MISC_AMDNB_CNT_MAX);
634 cc->cur_threshold = new_threshold;
635 misc &= ~MC_MISC_AMDNB_CNT_MASK;
636 misc |= (uint64_t)(MC_MISC_AMDNB_CNT_MAX - cc->cur_threshold)
637 << MC_MISC_AMDNB_CNT_SHIFT;
638 misc &= ~MC_MISC_AMDNB_OVERFLOW;
639 wrmsr(MSR_MC_MISC(bank), misc);
640 if (mode == CMCI && valid)
641 cc->last_intr = time_uptime;
646 * This scans all the machine check banks of the current CPU to see if
647 * there are any machine checks. Any non-recoverable errors are
648 * reported immediately via mca_log(). The current thread must be
649 * pinned when this is called. The 'mode' parameter indicates if we
650 * are being called from the MC exception handler, the CMCI handler,
651 * or the periodic poller. In the MC exception case this function
652 * returns true if the system is restartable. Otherwise, it returns a
653 * count of the number of valid MC records found.
656 mca_scan(enum scan_mode mode, int *recoverablep)
658 struct mca_record rec;
659 uint64_t mcg_cap, ucmask;
660 int count, i, recoverable, valid;
664 ucmask = MC_STATUS_UC | MC_STATUS_PCC;
666 /* When handling a MCE#, treat the OVER flag as non-restartable. */
668 ucmask |= MC_STATUS_OVER;
669 mcg_cap = rdmsr(MSR_MCG_CAP);
670 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
673 * For a CMCI, only check banks this CPU is
676 if (mode == CMCI && !(PCPU_GET(cmci_mask) & 1 << i))
680 valid = mca_check_status(i, &rec);
683 if (rec.mr_status & ucmask) {
685 mtx_lock_spin(&mca_lock);
687 mtx_unlock_spin(&mca_lock);
689 mca_record_entry(mode, &rec);
694 * If this is a bank this CPU monitors via CMCI,
695 * update the threshold.
697 if (PCPU_GET(cmci_mask) & 1 << i) {
698 if (cmc_state != NULL)
699 cmci_update(mode, i, valid, &rec);
701 amd_thresholding_update(mode, i, valid);
707 if (recoverablep != NULL)
708 *recoverablep = recoverable;
713 * Scan the machine check banks on all CPUs by binding to each CPU in
714 * turn. If any of the CPUs contained new machine check records, log
715 * them to the console.
718 mca_scan_cpus(void *context, int pending)
720 struct mca_internal *mca;
731 count += mca_scan(POLLED, NULL);
737 mtx_lock_spin(&mca_lock);
738 STAILQ_FOREACH(mca, &mca_records, link) {
744 mtx_unlock_spin(&mca_lock);
749 mca_periodic_scan(void *arg)
752 taskqueue_enqueue(mca_tq, &mca_scan_task);
753 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL);
757 sysctl_mca_scan(SYSCTL_HANDLER_ARGS)
762 error = sysctl_handle_int(oidp, &i, 0, req);
766 taskqueue_enqueue(mca_tq, &mca_scan_task);
771 mca_createtq(void *dummy)
776 mca_tq = taskqueue_create_fast("mca", M_WAITOK,
777 taskqueue_thread_enqueue, &mca_tq);
778 taskqueue_start_threads(&mca_tq, 1, PI_SWI(SWI_TQ), "mca taskq");
780 /* CMCIs during boot may have claimed items from the freelist. */
783 SYSINIT(mca_createtq, SI_SUB_CONFIGURE, SI_ORDER_ANY, mca_createtq, NULL);
786 mca_startup(void *dummy)
792 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL);
794 #ifdef EARLY_AP_STARTUP
795 SYSINIT(mca_startup, SI_SUB_KICK_SCHEDULER, SI_ORDER_ANY, mca_startup, NULL);
797 SYSINIT(mca_startup, SI_SUB_SMP, SI_ORDER_ANY, mca_startup, NULL);
806 cmc_state = malloc((mp_maxid + 1) * sizeof(struct cmc_state *), M_MCA,
808 for (i = 0; i <= mp_maxid; i++)
809 cmc_state[i] = malloc(sizeof(struct cmc_state) * mca_banks,
810 M_MCA, M_WAITOK | M_ZERO);
811 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
812 "cmc_throttle", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
813 &cmc_throttle, 0, sysctl_positive_int, "I",
814 "Interval in seconds to throttle corrected MC interrupts");
818 amd_thresholding_setup(void)
821 amd_et_state = malloc((mp_maxid + 1) * sizeof(struct amd_et_state),
822 M_MCA, M_WAITOK | M_ZERO);
823 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
824 "cmc_throttle", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
825 &cmc_throttle, 0, sysctl_positive_int, "I",
826 "Interval in seconds to throttle corrected MC interrupts");
831 mca_setup(uint64_t mcg_cap)
835 * On AMD Family 10h processors, unless logging of level one TLB
836 * parity (L1TP) errors is disabled, enable the recommended workaround
839 if (cpu_vendor_id == CPU_VENDOR_AMD &&
840 CPUID_TO_FAMILY(cpu_id) == 0x10 && amd10h_L1TP)
841 workaround_erratum383 = 1;
843 mca_banks = mcg_cap & MCG_CAP_COUNT;
844 mtx_init(&mca_lock, "mca", NULL, MTX_SPIN);
845 STAILQ_INIT(&mca_records);
846 TASK_INIT(&mca_scan_task, 0, mca_scan_cpus, NULL);
847 callout_init(&mca_timer, 1);
848 STAILQ_INIT(&mca_freelist);
849 TASK_INIT(&mca_refill_task, 0, mca_refill, NULL);
851 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
852 "count", CTLFLAG_RD, (int *)(uintptr_t)&mca_count, 0,
854 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
855 "interval", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, &mca_ticks,
856 0, sysctl_positive_int, "I",
857 "Periodic interval in seconds to scan for machine checks");
858 SYSCTL_ADD_NODE(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
859 "records", CTLFLAG_RD, sysctl_mca_records, "Machine check records");
860 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
861 "force_scan", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 0,
862 sysctl_mca_scan, "I", "Force an immediate scan for machine checks");
864 if (mcg_cap & MCG_CAP_CMCI_P)
866 else if (amd_thresholding_supported())
867 amd_thresholding_setup();
873 * See if we should monitor CMCI for this bank. If CMCI_EN is already
874 * set in MC_CTL2, then another CPU is responsible for this bank, so
875 * ignore it. If CMCI_EN returns zero after being set, then this bank
876 * does not support CMCI_EN. If this CPU sets CMCI_EN, then it should
877 * now monitor this bank.
882 struct cmc_state *cc;
885 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid)));
887 ctl = rdmsr(MSR_MC_CTL2(i));
888 if (ctl & MC_CTL2_CMCI_EN)
889 /* Already monitored by another CPU. */
892 /* Set the threshold to one event for now. */
893 ctl &= ~MC_CTL2_THRESHOLD;
894 ctl |= MC_CTL2_CMCI_EN | 1;
895 wrmsr(MSR_MC_CTL2(i), ctl);
896 ctl = rdmsr(MSR_MC_CTL2(i));
897 if (!(ctl & MC_CTL2_CMCI_EN))
898 /* This bank does not support CMCI. */
901 cc = &cmc_state[PCPU_GET(cpuid)][i];
903 /* Determine maximum threshold. */
904 ctl &= ~MC_CTL2_THRESHOLD;
906 wrmsr(MSR_MC_CTL2(i), ctl);
907 ctl = rdmsr(MSR_MC_CTL2(i));
908 cc->max_threshold = ctl & MC_CTL2_THRESHOLD;
910 /* Start off with a threshold of 1. */
911 ctl &= ~MC_CTL2_THRESHOLD;
913 wrmsr(MSR_MC_CTL2(i), ctl);
915 /* Mark this bank as monitored. */
916 PCPU_SET(cmci_mask, PCPU_GET(cmci_mask) | 1 << i);
920 * For resume, reset the threshold for any banks we monitor back to
921 * one and throw away the timestamp of the last interrupt.
926 struct cmc_state *cc;
929 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid)));
931 /* Ignore banks not monitored by this CPU. */
932 if (!(PCPU_GET(cmci_mask) & 1 << i))
935 cc = &cmc_state[PCPU_GET(cpuid)][i];
937 ctl = rdmsr(MSR_MC_CTL2(i));
938 ctl &= ~MC_CTL2_THRESHOLD;
939 ctl |= MC_CTL2_CMCI_EN | 1;
940 wrmsr(MSR_MC_CTL2(i), ctl);
944 amd_thresholding_start(struct amd_et_state *cc)
948 KASSERT(amd_elvt >= 0, ("ELVT offset is not set"));
949 misc = rdmsr(MSR_MC_MISC(MC_AMDNB_BANK));
950 misc &= ~MC_MISC_AMDNB_INT_MASK;
951 misc |= MC_MISC_AMDNB_INT_LVT;
952 misc &= ~MC_MISC_AMDNB_LVT_MASK;
953 misc |= (uint64_t)amd_elvt << MC_MISC_AMDNB_LVT_SHIFT;
954 misc &= ~MC_MISC_AMDNB_CNT_MASK;
955 misc |= (uint64_t)(MC_MISC_AMDNB_CNT_MAX - cc->cur_threshold)
956 << MC_MISC_AMDNB_CNT_SHIFT;
957 misc &= ~MC_MISC_AMDNB_OVERFLOW;
958 misc |= MC_MISC_AMDNB_CNTEN;
960 wrmsr(MSR_MC_MISC(MC_AMDNB_BANK), misc);
964 amd_thresholding_init(void)
966 struct amd_et_state *cc;
969 /* The counter must be valid and present. */
970 misc = rdmsr(MSR_MC_MISC(MC_AMDNB_BANK));
971 if ((misc & (MC_MISC_AMDNB_VAL | MC_MISC_AMDNB_CNTP)) !=
972 (MC_MISC_AMDNB_VAL | MC_MISC_AMDNB_CNTP))
975 /* The register should not be locked. */
976 if ((misc & MC_MISC_AMDNB_LOCK) != 0)
980 * If counter is enabled then either the firmware or another CPU
981 * has already claimed it.
983 if ((misc & MC_MISC_AMDNB_CNTEN) != 0)
987 * Configure an Extended Interrupt LVT register for reporting
988 * counter overflows if that feature is supported and the first
989 * extended register is available.
991 amd_elvt = lapic_enable_mca_elvt();
995 /* Re-use Intel CMC support infrastructure. */
996 cc = &amd_et_state[PCPU_GET(cpuid)];
997 cc->cur_threshold = 1;
998 amd_thresholding_start(cc);
1000 /* Mark the NB bank as monitored. */
1001 PCPU_SET(cmci_mask, PCPU_GET(cmci_mask) | 1 << MC_AMDNB_BANK);
1005 amd_thresholding_resume(void)
1007 struct amd_et_state *cc;
1009 /* Nothing to do if this CPU doesn't monitor the NB bank. */
1010 if ((PCPU_GET(cmci_mask) & 1 << MC_AMDNB_BANK) == 0)
1013 cc = &amd_et_state[PCPU_GET(cpuid)];
1015 cc->cur_threshold = 1;
1016 amd_thresholding_start(cc);
1021 * Initializes per-CPU machine check registers and enables corrected
1022 * machine check interrupts.
1031 /* MCE is required. */
1032 if (!mca_enabled || !(cpu_feature & CPUID_MCE))
1035 if (cpu_feature & CPUID_MCA) {
1037 PCPU_SET(cmci_mask, 0);
1039 mcg_cap = rdmsr(MSR_MCG_CAP);
1040 if (mcg_cap & MCG_CAP_CTL_P)
1041 /* Enable MCA features. */
1042 wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE);
1043 if (PCPU_GET(cpuid) == 0 && boot)
1047 * Disable logging of level one TLB parity (L1TP) errors by
1048 * the data cache as an alternative workaround for AMD Family
1049 * 10h Erratum 383. Unlike the recommended workaround, there
1050 * is no performance penalty to this workaround. However,
1051 * L1TP errors will go unreported.
1053 if (cpu_vendor_id == CPU_VENDOR_AMD &&
1054 CPUID_TO_FAMILY(cpu_id) == 0x10 && !amd10h_L1TP) {
1055 mask = rdmsr(MSR_MC0_CTL_MASK);
1056 if ((mask & (1UL << 5)) == 0)
1057 wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5));
1059 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
1060 /* By default enable logging of all errors. */
1061 ctl = 0xffffffffffffffffUL;
1064 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
1066 * For P6 models before Nehalem MC0_CTL is
1067 * always enabled and reserved.
1069 if (i == 0 && CPUID_TO_FAMILY(cpu_id) == 0x6
1070 && CPUID_TO_MODEL(cpu_id) < 0x1a)
1072 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
1073 /* BKDG for Family 10h: unset GartTblWkEn. */
1074 if (i == 4 && CPUID_TO_FAMILY(cpu_id) >= 0xf)
1075 ctl &= ~(1UL << 10);
1079 wrmsr(MSR_MC_CTL(i), ctl);
1082 if (mcg_cap & MCG_CAP_CMCI_P) {
1090 /* Clear all errors. */
1091 wrmsr(MSR_MC_STATUS(i), 0);
1096 * AMD Processors from families 10h - 16h provide support
1097 * for Machine Check Error Thresholding.
1098 * The processors support counters of MC errors and they
1099 * can be configured to generate an interrupt when a counter
1101 * The counters are all associated with Bank 4 and each
1102 * of them covers a group of errors reported via that bank.
1103 * At the moment only the DRAM Error Threshold Group is
1106 if (amd_thresholding_supported() &&
1107 (mcg_cap & MCG_CAP_COUNT) >= 4) {
1109 amd_thresholding_init();
1111 amd_thresholding_resume();
1112 } else if (PCPU_GET(cmci_mask) != 0 && boot) {
1118 load_cr4(rcr4() | CR4_MCE);
1121 /* Must be executed on each CPU during boot. */
1129 /* Must be executed on each CPU during resume. */
1138 * The machine check registers for the BSP cannot be initialized until
1139 * the local APIC is initialized. This happens at SI_SUB_CPU,
1143 mca_init_bsp(void *arg __unused)
1148 SYSINIT(mca_init_bsp, SI_SUB_CPU, SI_ORDER_ANY, mca_init_bsp, NULL);
1150 /* Called when a machine check exception fires. */
1154 uint64_t mcg_status;
1155 int recoverable, count;
1157 if (!(cpu_feature & CPUID_MCA)) {
1159 * Just print the values of the old Pentium registers
1162 printf("MC Type: 0x%jx Address: 0x%jx\n",
1163 (uintmax_t)rdmsr(MSR_P5_MC_TYPE),
1164 (uintmax_t)rdmsr(MSR_P5_MC_ADDR));
1165 panic("Machine check");
1168 /* Scan the banks and check for any non-recoverable errors. */
1169 count = mca_scan(MCE, &recoverable);
1170 mcg_status = rdmsr(MSR_MCG_STATUS);
1171 if (!(mcg_status & MCG_STATUS_RIPV))
1176 * Only panic if the error was detected local to this CPU.
1177 * Some errors will assert a machine check on all CPUs, but
1178 * only certain CPUs will find a valid bank to log.
1183 panic("Unrecoverable machine check exception");
1187 wrmsr(MSR_MCG_STATUS, mcg_status & ~MCG_STATUS_MCIP);
1191 /* Called for a CMCI (correctable machine check interrupt). */
1195 struct mca_internal *mca;
1199 * Serialize MCA bank scanning to prevent collisions from
1202 count = mca_scan(CMCI, NULL);
1204 /* If we found anything, log them to the console. */
1206 mtx_lock_spin(&mca_lock);
1207 STAILQ_FOREACH(mca, &mca_records, link) {
1213 mtx_unlock_spin(&mca_lock);