2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
34 #include "opt_kstack_pages.h"
36 #include "opt_sched.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/cons.h> /* cngetc() */
43 #include <sys/cpuset.h>
48 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/memrange.h>
53 #include <sys/mutex.h>
56 #include <sys/sched.h>
58 #include <sys/sysctl.h>
61 #include <vm/vm_param.h>
63 #include <vm/vm_kern.h>
64 #include <vm/vm_extern.h>
65 #include <vm/vm_map.h>
67 #include <x86/apicreg.h>
68 #include <machine/clock.h>
69 #include <machine/cpu.h>
70 #include <machine/cputypes.h>
72 #include <machine/md_var.h>
73 #include <machine/pcb.h>
74 #include <machine/psl.h>
75 #include <machine/smp.h>
76 #include <machine/specialreg.h>
77 #include <x86/ucode.h>
79 static MALLOC_DEFINE(M_CPUS, "cpus", "CPU items");
81 /* lock region used by kernel profiling */
84 int mp_naps; /* # of Applications processors */
85 int boot_cpu_id = -1; /* designated BSP */
87 /* AP uses this during bootstrap. Do not staticize. */
91 /* Free these after use */
92 void *bootstacks[MAXCPU];
95 struct pcb stoppcbs[MAXCPU];
96 struct susppcb **susppcbs;
99 /* Interrupt counts. */
100 static u_long *ipi_preempt_counts[MAXCPU];
101 static u_long *ipi_ast_counts[MAXCPU];
102 u_long *ipi_invltlb_counts[MAXCPU];
103 u_long *ipi_invlrng_counts[MAXCPU];
104 u_long *ipi_invlpg_counts[MAXCPU];
105 u_long *ipi_invlcache_counts[MAXCPU];
106 u_long *ipi_rendezvous_counts[MAXCPU];
107 static u_long *ipi_hardclock_counts[MAXCPU];
110 /* Default cpu_ops implementation. */
111 struct cpu_ops cpu_ops;
114 * Local data and functions.
117 static volatile cpuset_t ipi_stop_nmi_pending;
119 volatile cpuset_t resuming_cpus;
120 volatile cpuset_t toresume_cpus;
122 /* used to hold the AP's until we are ready to release them */
123 struct mtx ap_boot_mtx;
125 /* Set to 1 once we're ready to let the APs out of the pen. */
126 volatile int aps_ready = 0;
129 * Store data from cpu_add() until later in the boot when we actually setup
132 struct cpu_info *cpu_info;
134 int cpu_apic_ids[MAXCPU];
135 _Static_assert(MAXCPU <= MAX_APIC_ID,
136 "MAXCPU cannot be larger that MAX_APIC_ID");
137 _Static_assert(xAPIC_MAX_APIC_ID <= MAX_APIC_ID,
138 "xAPIC_MAX_APIC_ID cannot be larger that MAX_APIC_ID");
140 static void release_aps(void *dummy);
141 static void cpustop_handler_post(u_int cpu);
143 static int hyperthreading_allowed = 1;
144 SYSCTL_INT(_machdep, OID_AUTO, hyperthreading_allowed, CTLFLAG_RDTUN,
145 &hyperthreading_allowed, 0, "Use Intel HTT logical CPUs");
147 static struct topo_node topo_root;
149 static int pkg_id_shift;
150 static int node_id_shift;
151 static int core_id_shift;
152 static int disabled_cpus;
157 } static caches[MAX_CACHE_LEVELS];
159 unsigned int boot_address;
161 static bool stop_mwait = false;
162 SYSCTL_BOOL(_machdep, OID_AUTO, stop_mwait, CTLFLAG_RWTUN, &stop_mwait, 0,
163 "Use MONITOR/MWAIT when stopping CPU, if available");
165 #define MiB(v) (v ## ULL << 20)
168 mem_range_AP_init(void)
171 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
172 mem_range_softc.mr_op->initAP(&mem_range_softc);
176 * Round up to the next power of two, if necessary, and then
178 * Returns -1 if argument is zero.
184 return (fls(x << (1 - powerof2(x))) - 1);
188 * Add a cache level to the cache topology description.
191 add_deterministic_cache(int type, int level, int share_count)
197 printf("unexpected cache type %d\n", type);
200 if (type == 2) /* ignore instruction cache */
202 if (level == 0 || level > MAX_CACHE_LEVELS) {
203 printf("unexpected cache level %d\n", type);
207 if (caches[level - 1].present) {
208 printf("WARNING: multiple entries for L%u data cache\n", level);
209 printf("%u => %u\n", caches[level - 1].id_shift,
210 mask_width(share_count));
212 caches[level - 1].id_shift = mask_width(share_count);
213 caches[level - 1].present = 1;
215 if (caches[level - 1].id_shift > pkg_id_shift) {
216 printf("WARNING: L%u data cache covers more "
217 "APIC IDs than a package (%u > %u)\n", level,
218 caches[level - 1].id_shift, pkg_id_shift);
219 caches[level - 1].id_shift = pkg_id_shift;
221 if (caches[level - 1].id_shift < core_id_shift) {
222 printf("WARNING: L%u data cache covers fewer "
223 "APIC IDs than a core (%u < %u)\n", level,
224 caches[level - 1].id_shift, core_id_shift);
225 caches[level - 1].id_shift = core_id_shift;
232 * Determine topology of processing units and caches for AMD CPUs.
234 * - AMD CPUID Specification (Publication # 25481)
235 * - BKDG for AMD NPT Family 0Fh Processors (Publication # 32559)
236 * - BKDG For AMD Family 10h Processors (Publication # 31116)
237 * - BKDG For AMD Family 15h Models 00h-0Fh Processors (Publication # 42301)
238 * - BKDG For AMD Family 16h Models 00h-0Fh Processors (Publication # 48751)
239 * - PPR For AMD Family 17h Models 00h-0Fh Processors (Publication # 54945)
247 int nodes_per_socket;
252 /* No multi-core capability. */
253 if ((amd_feature2 & AMDID2_CMP) == 0)
256 /* For families 10h and newer. */
257 pkg_id_shift = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
258 AMDID_COREID_SIZE_SHIFT;
260 /* For 0Fh family. */
261 if (pkg_id_shift == 0)
263 mask_width((cpu_procinfo2 & AMDID_CMP_CORES) + 1);
266 * Families prior to 16h define the following value as
267 * cores per compute unit and we don't really care about the AMD
268 * compute units at the moment. Perhaps we should treat them as
269 * cores and cores within the compute units as hardware threads,
270 * but that's up for debate.
271 * Later families define the value as threads per compute unit,
272 * so we are following AMD's nomenclature here.
274 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0 &&
275 CPUID_TO_FAMILY(cpu_id) >= 0x16) {
276 cpuid_count(0x8000001e, 0, p);
277 share_count = ((p[1] >> 8) & 0xff) + 1;
278 core_id_shift = mask_width(share_count);
281 * For Zen (17h), gather Nodes per Processor. Each node is a
282 * Zeppelin die; TR and EPYC CPUs will have multiple dies per
283 * package. Communication latency between dies is higher than
286 nodes_per_socket = ((p[2] >> 8) & 0x7) + 1;
287 node_id_shift = pkg_id_shift - mask_width(nodes_per_socket);
290 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0) {
292 cpuid_count(0x8000001d, i, p);
294 level = (p[0] >> 5) & 0x7;
295 share_count = 1 + ((p[0] >> 14) & 0xfff);
297 if (!add_deterministic_cache(type, level, share_count))
301 if (cpu_exthigh >= 0x80000005) {
302 cpuid_count(0x80000005, 0, p);
303 if (((p[2] >> 24) & 0xff) != 0) {
304 caches[0].id_shift = 0;
305 caches[0].present = 1;
308 if (cpu_exthigh >= 0x80000006) {
309 cpuid_count(0x80000006, 0, p);
310 if (((p[2] >> 16) & 0xffff) != 0) {
311 caches[1].id_shift = 0;
312 caches[1].present = 1;
314 if (((p[3] >> 18) & 0x3fff) != 0) {
315 nodes_per_socket = 1;
316 if ((amd_feature2 & AMDID2_NODE_ID) != 0) {
318 * Handle multi-node processors that
319 * have multiple chips, each with its
320 * own L3 cache, on the same die.
322 v = rdmsr(0xc001100c);
323 nodes_per_socket = 1 + ((v >> 3) & 0x7);
326 pkg_id_shift - mask_width(nodes_per_socket);
327 caches[2].present = 1;
334 * Determine topology of processing units for Intel CPUs
335 * using CPUID Leaf 1 and Leaf 4, if supported.
337 * - Intel 64 Architecture Processor Topology Enumeration
338 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
339 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
340 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
343 topo_probe_intel_0x4(void)
349 /* Both zero and one here mean one logical processor per package. */
350 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
351 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
352 if (max_logical <= 1)
355 if (cpu_high >= 0x4) {
356 cpuid_count(0x04, 0, p);
357 max_cores = ((p[0] >> 26) & 0x3f) + 1;
361 core_id_shift = mask_width(max_logical/max_cores);
362 KASSERT(core_id_shift >= 0,
363 ("intel topo: max_cores > max_logical\n"));
364 pkg_id_shift = core_id_shift + mask_width(max_cores);
368 * Determine topology of processing units for Intel CPUs
369 * using CPUID Leaf 11, if supported.
371 * - Intel 64 Architecture Processor Topology Enumeration
372 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
373 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
374 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
377 topo_probe_intel_0xb(void)
384 /* Fall back if CPU leaf 11 doesn't really exist. */
385 cpuid_count(0x0b, 0, p);
387 topo_probe_intel_0x4();
391 /* We only support three levels for now. */
393 cpuid_count(0x0b, i, p);
396 type = (p[2] >> 8) & 0xff;
401 /* TODO: check for duplicate (re-)assignment */
402 if (type == CPUID_TYPE_SMT)
403 core_id_shift = bits;
404 else if (type == CPUID_TYPE_CORE)
407 printf("unknown CPU level type %d\n", type);
410 if (pkg_id_shift < core_id_shift) {
411 printf("WARNING: core covers more APIC IDs than a package\n");
412 core_id_shift = pkg_id_shift;
417 * Determine topology of caches for Intel CPUs.
419 * - Intel 64 Architecture Processor Topology Enumeration
420 * - Intel 64 and IA-32 Architectures Software Developer’s Manual
421 * Volume 2A: Instruction Set Reference, A-M,
425 topo_probe_intel_caches(void)
433 if (cpu_high < 0x4) {
435 * Available cache level and sizes can be determined
436 * via CPUID leaf 2, but that requires a huge table of hardcoded
437 * values, so for now just assume L1 and L2 caches potentially
438 * shared only by HTT processing units, if HTT is present.
440 caches[0].id_shift = pkg_id_shift;
441 caches[0].present = 1;
442 caches[1].id_shift = pkg_id_shift;
443 caches[1].present = 1;
448 cpuid_count(0x4, i, p);
450 level = (p[0] >> 5) & 0x7;
451 share_count = 1 + ((p[0] >> 14) & 0xfff);
453 if (!add_deterministic_cache(type, level, share_count))
459 * Determine topology of processing units and caches for Intel CPUs.
461 * - Intel 64 Architecture Processor Topology Enumeration
464 topo_probe_intel(void)
468 * Note that 0x1 <= cpu_high < 4 case should be
469 * compatible with topo_probe_intel_0x4() logic when
470 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
471 * or it should trigger the fallback otherwise.
474 topo_probe_intel_0xb();
475 else if (cpu_high >= 0x1)
476 topo_probe_intel_0x4();
478 topo_probe_intel_caches();
482 * Topology information is queried only on BSP, on which this
483 * code runs and for which it can query CPUID information.
484 * Then topology is extrapolated on all packages using an
485 * assumption that APIC ID to hardware component ID mapping is
487 * That doesn't necesserily imply that the topology is uniform.
492 static int cpu_topo_probed = 0;
493 struct x86_topo_layer {
497 } topo_layers[MAX_CACHE_LEVELS + 4];
498 struct topo_node *parent;
499 struct topo_node *node;
508 CPU_ZERO(&logical_cpus_mask);
512 else if (cpu_vendor_id == CPU_VENDOR_AMD)
514 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
517 KASSERT(pkg_id_shift >= core_id_shift,
518 ("bug in APIC topology discovery"));
521 bzero(topo_layers, sizeof(topo_layers));
523 topo_layers[nlayers].type = TOPO_TYPE_PKG;
524 topo_layers[nlayers].id_shift = pkg_id_shift;
526 printf("Package ID shift: %u\n", topo_layers[nlayers].id_shift);
529 if (pkg_id_shift > node_id_shift && node_id_shift != 0) {
530 topo_layers[nlayers].type = TOPO_TYPE_GROUP;
531 topo_layers[nlayers].id_shift = node_id_shift;
533 printf("Node ID shift: %u\n",
534 topo_layers[nlayers].id_shift);
539 * Consider all caches to be within a package/chip
540 * and "in front" of all sub-components like
541 * cores and hardware threads.
543 for (i = MAX_CACHE_LEVELS - 1; i >= 0; --i) {
544 if (caches[i].present) {
545 if (node_id_shift != 0)
546 KASSERT(caches[i].id_shift <= node_id_shift,
547 ("bug in APIC topology discovery"));
548 KASSERT(caches[i].id_shift <= pkg_id_shift,
549 ("bug in APIC topology discovery"));
550 KASSERT(caches[i].id_shift >= core_id_shift,
551 ("bug in APIC topology discovery"));
553 topo_layers[nlayers].type = TOPO_TYPE_CACHE;
554 topo_layers[nlayers].subtype = i + 1;
555 topo_layers[nlayers].id_shift = caches[i].id_shift;
557 printf("L%u cache ID shift: %u\n",
558 topo_layers[nlayers].subtype,
559 topo_layers[nlayers].id_shift);
564 if (pkg_id_shift > core_id_shift) {
565 topo_layers[nlayers].type = TOPO_TYPE_CORE;
566 topo_layers[nlayers].id_shift = core_id_shift;
568 printf("Core ID shift: %u\n",
569 topo_layers[nlayers].id_shift);
573 topo_layers[nlayers].type = TOPO_TYPE_PU;
574 topo_layers[nlayers].id_shift = 0;
577 topo_init_root(&topo_root);
578 for (i = 0; i <= max_apic_id; ++i) {
579 if (!cpu_info[i].cpu_present)
583 for (layer = 0; layer < nlayers; ++layer) {
584 node_id = i >> topo_layers[layer].id_shift;
585 parent = topo_add_node_by_hwid(parent, node_id,
586 topo_layers[layer].type,
587 topo_layers[layer].subtype);
592 for (layer = 0; layer < nlayers; ++layer) {
593 node_id = boot_cpu_id >> topo_layers[layer].id_shift;
594 node = topo_find_node_by_hwid(parent, node_id,
595 topo_layers[layer].type,
596 topo_layers[layer].subtype);
597 topo_promote_child(node);
605 * Assign logical CPU IDs to local APICs.
610 struct topo_node *node;
614 smt_mask = (1u << core_id_shift) - 1;
617 * Assign CPU IDs to local APIC IDs and disable any CPUs
618 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
622 TOPO_FOREACH(node, &topo_root) {
623 if (node->type != TOPO_TYPE_PU)
626 if ((node->hwid & smt_mask) != (boot_cpu_id & smt_mask))
627 cpu_info[node->hwid].cpu_hyperthread = 1;
629 if (resource_disabled("lapic", node->hwid)) {
630 if (node->hwid != boot_cpu_id)
631 cpu_info[node->hwid].cpu_disabled = 1;
633 printf("Cannot disable BSP, APIC ID = %d\n",
637 if (!hyperthreading_allowed &&
638 cpu_info[node->hwid].cpu_hyperthread)
639 cpu_info[node->hwid].cpu_disabled = 1;
641 if (mp_ncpus >= MAXCPU)
642 cpu_info[node->hwid].cpu_disabled = 1;
644 if (cpu_info[node->hwid].cpu_disabled) {
649 if (cpu_info[node->hwid].cpu_hyperthread)
652 cpu_apic_ids[mp_ncpus] = node->hwid;
653 apic_cpuids[node->hwid] = mp_ncpus;
654 topo_set_pu_id(node, mp_ncpus);
658 KASSERT(mp_maxid >= mp_ncpus - 1,
659 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
662 mp_ncores = mp_ncpus - nhyper;
663 smp_threads_per_core = mp_ncpus / mp_ncores;
667 * Print various information about the SMP system hardware and setup.
670 cpu_mp_announce(void)
672 struct topo_node *node;
673 const char *hyperthread;
674 struct topo_analysis topology;
676 printf("FreeBSD/SMP: ");
677 if (topo_analyze(&topo_root, 1, &topology)) {
678 printf("%d package(s)", topology.entities[TOPO_LEVEL_PKG]);
679 if (topology.entities[TOPO_LEVEL_GROUP] > 1)
680 printf(" x %d groups",
681 topology.entities[TOPO_LEVEL_GROUP]);
682 if (topology.entities[TOPO_LEVEL_CACHEGROUP] > 1)
683 printf(" x %d cache groups",
684 topology.entities[TOPO_LEVEL_CACHEGROUP]);
685 if (topology.entities[TOPO_LEVEL_CORE] > 0)
686 printf(" x %d core(s)",
687 topology.entities[TOPO_LEVEL_CORE]);
688 if (topology.entities[TOPO_LEVEL_THREAD] > 1)
689 printf(" x %d hardware threads",
690 topology.entities[TOPO_LEVEL_THREAD]);
692 printf("Non-uniform topology");
697 printf("FreeBSD/SMP Online: ");
698 if (topo_analyze(&topo_root, 0, &topology)) {
699 printf("%d package(s)",
700 topology.entities[TOPO_LEVEL_PKG]);
701 if (topology.entities[TOPO_LEVEL_GROUP] > 1)
702 printf(" x %d groups",
703 topology.entities[TOPO_LEVEL_GROUP]);
704 if (topology.entities[TOPO_LEVEL_CACHEGROUP] > 1)
705 printf(" x %d cache groups",
706 topology.entities[TOPO_LEVEL_CACHEGROUP]);
707 if (topology.entities[TOPO_LEVEL_CORE] > 0)
708 printf(" x %d core(s)",
709 topology.entities[TOPO_LEVEL_CORE]);
710 if (topology.entities[TOPO_LEVEL_THREAD] > 1)
711 printf(" x %d hardware threads",
712 topology.entities[TOPO_LEVEL_THREAD]);
714 printf("Non-uniform topology");
722 TOPO_FOREACH(node, &topo_root) {
723 switch (node->type) {
725 printf("Package HW ID = %u\n", node->hwid);
728 printf("\tCore HW ID = %u\n", node->hwid);
731 if (cpu_info[node->hwid].cpu_hyperthread)
736 if (node->subtype == 0)
737 printf("\t\tCPU (AP%s): APIC ID: %u"
738 "(disabled)\n", hyperthread, node->hwid);
739 else if (node->id == 0)
740 printf("\t\tCPU0 (BSP): APIC ID: %u\n",
743 printf("\t\tCPU%u (AP%s): APIC ID: %u\n",
744 node->id, hyperthread, node->hwid);
754 * Add a scheduling group, a group of logical processors sharing
755 * a particular cache (and, thus having an affinity), to the scheduling
757 * This function recursively works on lower level caches.
760 x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
762 struct topo_node *node;
767 KASSERT(root->type == TOPO_TYPE_SYSTEM || root->type == TOPO_TYPE_CACHE ||
768 root->type == TOPO_TYPE_GROUP,
769 ("x86topo_add_sched_group: bad type: %u", root->type));
770 CPU_COPY(&root->cpuset, &cg_root->cg_mask);
771 cg_root->cg_count = root->cpu_count;
772 if (root->type == TOPO_TYPE_SYSTEM)
773 cg_root->cg_level = CG_SHARE_NONE;
775 cg_root->cg_level = root->subtype;
778 * Check how many core nodes we have under the given root node.
779 * If we have multiple logical processors, but not multiple
780 * cores, then those processors must be hardware threads.
784 while (node != NULL) {
785 if (node->type != TOPO_TYPE_CORE) {
786 node = topo_next_node(root, node);
791 node = topo_next_nonchild_node(root, node);
794 if (cg_root->cg_level != CG_SHARE_NONE &&
795 root->cpu_count > 1 && ncores < 2)
796 cg_root->cg_flags = CG_FLAG_SMT;
799 * Find out how many cache nodes we have under the given root node.
800 * We ignore cache nodes that cover all the same processors as the
801 * root node. Also, we do not descend below found cache nodes.
802 * That is, we count top-level "non-redundant" caches under the root
807 while (node != NULL) {
808 if ((node->type != TOPO_TYPE_GROUP &&
809 node->type != TOPO_TYPE_CACHE) ||
810 (root->type != TOPO_TYPE_SYSTEM &&
811 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
812 node = topo_next_node(root, node);
816 node = topo_next_nonchild_node(root, node);
819 cg_root->cg_child = smp_topo_alloc(nchildren);
820 cg_root->cg_children = nchildren;
823 * Now find again the same cache nodes as above and recursively
824 * build scheduling topologies for them.
828 while (node != NULL) {
829 if ((node->type != TOPO_TYPE_GROUP &&
830 node->type != TOPO_TYPE_CACHE) ||
831 (root->type != TOPO_TYPE_SYSTEM &&
832 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
833 node = topo_next_node(root, node);
836 cg_root->cg_child[i].cg_parent = cg_root;
837 x86topo_add_sched_group(node, &cg_root->cg_child[i]);
839 node = topo_next_nonchild_node(root, node);
844 * Build the MI scheduling topology from the discovered hardware topology.
849 struct cpu_group *cg_root;
852 return (smp_topo_none());
854 cg_root = smp_topo_alloc(1);
855 x86topo_add_sched_group(&topo_root, cg_root);
860 cpu_alloc(void *dummy __unused)
863 * Dynamically allocate the arrays that depend on the
866 cpu_info = malloc(sizeof(*cpu_info) * (max_apic_id + 1), M_CPUS,
868 apic_cpuids = malloc(sizeof(*apic_cpuids) * (max_apic_id + 1), M_CPUS,
871 SYSINIT(cpu_alloc, SI_SUB_CPU, SI_ORDER_FIRST, cpu_alloc, NULL);
874 * Add a logical CPU to the topology.
877 cpu_add(u_int apic_id, char boot_cpu)
880 if (apic_id > max_apic_id) {
881 panic("SMP: APIC ID %d too high", apic_id);
884 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %u added twice",
886 cpu_info[apic_id].cpu_present = 1;
888 KASSERT(boot_cpu_id == -1,
889 ("CPU %u claims to be BSP, but CPU %u already is", apic_id,
891 boot_cpu_id = apic_id;
892 cpu_info[apic_id].cpu_bsp = 1;
895 printf("SMP: Added CPU %u (%s)\n", apic_id, boot_cpu ? "BSP" :
900 cpu_mp_setmaxid(void)
904 * mp_ncpus and mp_maxid should be already set by calls to cpu_add().
905 * If there were no calls to cpu_add() assume this is a UP system.
916 * Always record BSP in CPU map so that the mbuf init code works
919 CPU_SETOF(0, &all_cpus);
920 return (mp_ncpus > 1);
923 /* Allocate memory for the AP trampoline. */
925 alloc_ap_trampoline(vm_paddr_t *physmap, unsigned int *physmap_idx)
931 for (i = *physmap_idx; i <= *physmap_idx; i -= 2) {
933 * Find a memory region big enough and below the 1MB boundary
934 * for the trampoline code.
935 * NB: needs to be page aligned.
937 if (physmap[i] >= MiB(1) ||
938 (trunc_page(physmap[i + 1]) - round_page(physmap[i])) <
939 round_page(bootMP_size))
944 * Try to steal from the end of the region to mimic previous
945 * behaviour, else fallback to steal from the start.
947 if (physmap[i + 1] < MiB(1)) {
948 boot_address = trunc_page(physmap[i + 1]);
949 if ((physmap[i + 1] - boot_address) < bootMP_size)
950 boot_address -= round_page(bootMP_size);
951 physmap[i + 1] = boot_address;
953 boot_address = round_page(physmap[i]);
954 physmap[i] = boot_address + round_page(bootMP_size);
956 if (physmap[i] == physmap[i + 1] && *physmap_idx != 0) {
957 memmove(&physmap[i], &physmap[i + 2],
958 sizeof(*physmap) * (*physmap_idx - i + 2));
965 boot_address = basemem * 1024 - bootMP_size;
968 "Cannot find enough space for the boot trampoline, placing it at %#x",
974 * AP CPU's call this to initialize themselves.
977 init_secondary_tail(void)
981 pmap_activate_boot(vmspace_pmap(proc0.p_vmspace));
984 * On real hardware, switch to x2apic mode if possible. Do it
985 * after aps_ready was signalled, to avoid manipulating the
986 * mode while BSP might still want to send some IPI to us
987 * (second startup IPI is ignored on modern hardware etc).
991 /* Initialize the PAT MSR. */
994 /* set up CPU registers and state */
1000 /* set up FPU state on the AP */
1007 if (cpu_ops.cpu_init)
1010 /* A quick check from sanity claus */
1011 cpuid = PCPU_GET(cpuid);
1012 if (PCPU_GET(apic_id) != lapic_id()) {
1013 printf("SMP: cpuid = %d\n", cpuid);
1014 printf("SMP: actual apic_id = %d\n", lapic_id());
1015 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
1016 panic("cpuid mismatch! boom!!");
1019 /* Initialize curthread. */
1020 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
1021 PCPU_SET(curthread, PCPU_GET(idlethread));
1023 mtx_lock_spin(&ap_boot_mtx);
1027 /* Init local apic for irq's */
1030 /* Set memory range attributes for this CPU to match the BSP */
1031 mem_range_AP_init();
1035 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
1037 printf("SMP: AP CPU #%d Launched!\n", cpuid);
1039 printf("%s%d%s", smp_cpus == 2 ? "Launching APs: " : "",
1040 cpuid, smp_cpus == mp_ncpus ? "\n" : " ");
1042 /* Determine if we are a logical CPU. */
1043 if (cpu_info[PCPU_GET(apic_id)].cpu_hyperthread)
1044 CPU_SET(cpuid, &logical_cpus_mask);
1049 if (smp_cpus == mp_ncpus) {
1050 /* enable IPI's, tlb shootdown, freezes etc */
1051 atomic_store_rel_int(&smp_started, 1);
1056 * Enable global pages TLB extension
1057 * This also implicitly flushes the TLB
1059 load_cr4(rcr4() | CR4_PGE);
1060 if (pmap_pcid_enabled)
1061 load_cr4(rcr4() | CR4_PCIDE);
1067 mtx_unlock_spin(&ap_boot_mtx);
1069 /* Wait until all the AP's are up. */
1070 while (atomic_load_acq_int(&smp_started) == 0)
1073 #ifndef EARLY_AP_STARTUP
1074 /* Start per-CPU event timers. */
1075 cpu_initclocks_ap();
1080 panic("scheduler returned us to %s", __func__);
1085 smp_after_idle_runnable(void *arg __unused)
1087 struct thread *idle_td;
1090 for (cpu = 1; cpu < mp_ncpus; cpu++) {
1091 idle_td = pcpu_find(cpu)->pc_idlethread;
1092 while (atomic_load_int(&idle_td->td_lastcpu) == NOCPU &&
1093 atomic_load_int(&idle_td->td_oncpu) == NOCPU)
1095 kmem_free((vm_offset_t)bootstacks[cpu], kstack_pages *
1099 SYSINIT(smp_after_idle_runnable, SI_SUB_SMP, SI_ORDER_ANY,
1100 smp_after_idle_runnable, NULL);
1103 * We tell the I/O APIC code about all the CPUs we want to receive
1104 * interrupts. If we don't want certain CPUs to receive IRQs we
1105 * can simply not tell the I/O APIC code about them in this function.
1106 * We also do not tell it about the BSP since it tells itself about
1107 * the BSP internally to work with UP kernels and on UP machines.
1110 set_interrupt_apic_ids(void)
1114 for (i = 0; i < MAXCPU; i++) {
1115 apic_id = cpu_apic_ids[i];
1118 if (cpu_info[apic_id].cpu_bsp)
1120 if (cpu_info[apic_id].cpu_disabled)
1123 /* Don't let hyperthreads service interrupts. */
1124 if (cpu_info[apic_id].cpu_hyperthread)
1132 #ifdef COUNT_XINVLTLB_HITS
1133 u_int xhits_gbl[MAXCPU];
1134 u_int xhits_pg[MAXCPU];
1135 u_int xhits_rng[MAXCPU];
1136 static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1137 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1138 sizeof(xhits_gbl), "IU", "");
1139 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1140 sizeof(xhits_pg), "IU", "");
1141 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1142 sizeof(xhits_rng), "IU", "");
1147 u_int ipi_range_size;
1148 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1149 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1150 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1151 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1153 #endif /* COUNT_XINVLTLB_HITS */
1156 * Init and startup IPI.
1159 ipi_startup(int apic_id, int vector)
1163 * This attempts to follow the algorithm described in the
1164 * Intel Multiprocessor Specification v1.4 in section B.4.
1165 * For each IPI, we allow the local APIC ~20us to deliver the
1166 * IPI. If that times out, we panic.
1170 * first we do an INIT IPI: this INIT IPI might be run, resetting
1171 * and running the target CPU. OR this INIT IPI might be latched (P5
1172 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1175 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1176 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1177 lapic_ipi_wait(100);
1179 /* Explicitly deassert the INIT IPI. */
1180 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1181 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT,
1184 DELAY(10000); /* wait ~10mS */
1187 * next we do a STARTUP IPI: the previous INIT IPI might still be
1188 * latched, (P5 bug) this 1st STARTUP would then terminate
1189 * immediately, and the previously started INIT IPI would continue. OR
1190 * the previous INIT IPI has already run. and this STARTUP IPI will
1191 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1194 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1195 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1197 if (!lapic_ipi_wait(100))
1198 panic("Failed to deliver first STARTUP IPI to APIC %d",
1200 DELAY(200); /* wait ~200uS */
1203 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1204 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1205 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1206 * recognized after hardware RESET or INIT IPI.
1208 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1209 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1211 if (!lapic_ipi_wait(100))
1212 panic("Failed to deliver second STARTUP IPI to APIC %d",
1215 DELAY(200); /* wait ~200uS */
1219 * Send an IPI to specified CPU handling the bitmap logic.
1222 ipi_send_cpu(int cpu, u_int ipi)
1224 u_int bitmap, old, new;
1227 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1229 if (IPI_IS_BITMAPED(ipi)) {
1231 ipi = IPI_BITMAP_VECTOR;
1232 cpu_bitmap = &cpuid_to_pcpu[cpu]->pc_ipi_bitmap;
1235 if ((old & bitmap) == bitmap)
1238 if (atomic_fcmpset_int(cpu_bitmap, &old, new))
1244 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1248 ipi_bitmap_handler(struct trapframe frame)
1250 struct trapframe *oldframe;
1252 int cpu = PCPU_GET(cpuid);
1257 td->td_intr_nesting_level++;
1258 oldframe = td->td_intr_frame;
1259 td->td_intr_frame = &frame;
1260 ipi_bitmap = atomic_readandclear_int(&cpuid_to_pcpu[cpu]->pc_ipi_bitmap);
1261 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1263 (*ipi_preempt_counts[cpu])++;
1267 if (ipi_bitmap & (1 << IPI_AST)) {
1269 (*ipi_ast_counts[cpu])++;
1271 /* Nothing to do for AST */
1273 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1275 (*ipi_hardclock_counts[cpu])++;
1279 td->td_intr_frame = oldframe;
1280 td->td_intr_nesting_level--;
1285 * send an IPI to a set of cpus.
1288 ipi_selected(cpuset_t cpus, u_int ipi)
1293 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1294 * of help in order to understand what is the source.
1295 * Set the mask of receiving CPUs for this purpose.
1297 if (ipi == IPI_STOP_HARD)
1298 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &cpus);
1300 while ((cpu = CPU_FFS(&cpus)) != 0) {
1302 CPU_CLR(cpu, &cpus);
1303 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1304 ipi_send_cpu(cpu, ipi);
1309 * send an IPI to a specific CPU.
1312 ipi_cpu(int cpu, u_int ipi)
1316 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1317 * of help in order to understand what is the source.
1318 * Set the mask of receiving CPUs for this purpose.
1320 if (ipi == IPI_STOP_HARD)
1321 CPU_SET_ATOMIC(cpu, &ipi_stop_nmi_pending);
1323 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1324 ipi_send_cpu(cpu, ipi);
1328 * send an IPI to all CPUs EXCEPT myself
1331 ipi_all_but_self(u_int ipi)
1333 cpuset_t other_cpus;
1335 other_cpus = all_cpus;
1336 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1337 if (IPI_IS_BITMAPED(ipi)) {
1338 ipi_selected(other_cpus, ipi);
1343 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1344 * of help in order to understand what is the source.
1345 * Set the mask of receiving CPUs for this purpose.
1347 if (ipi == IPI_STOP_HARD)
1348 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &other_cpus);
1350 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1351 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1355 ipi_nmi_handler(void)
1360 * As long as there is not a simple way to know about a NMI's
1361 * source, if the bitmask for the current CPU is present in
1362 * the global pending bitword an IPI_STOP_HARD has been issued
1363 * and should be handled.
1365 cpuid = PCPU_GET(cpuid);
1366 if (!CPU_ISSET(cpuid, &ipi_stop_nmi_pending))
1369 CPU_CLR_ATOMIC(cpuid, &ipi_stop_nmi_pending);
1377 nmi_call_kdb_smp(u_int type, struct trapframe *frame)
1382 cpu = PCPU_GET(cpuid);
1383 if (atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1)) {
1384 nmi_call_kdb(cpu, type, frame);
1387 savectx(&stoppcbs[cpu]);
1388 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1389 while (!atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1))
1393 atomic_store_rel_int(&nmi_kdb_lock, 0);
1395 cpustop_handler_post(cpu);
1399 * Handle an IPI_STOP by saving our current context and spinning (or mwaiting,
1400 * if available) until we are resumed.
1403 cpustop_handler(void)
1405 struct monitorbuf *mb;
1409 cpu = PCPU_GET(cpuid);
1411 savectx(&stoppcbs[cpu]);
1413 use_mwait = (stop_mwait && (cpu_feature2 & CPUID2_MON) != 0 &&
1414 !mwait_cpustop_broken);
1416 mb = PCPU_PTR(monitorbuf);
1417 atomic_store_int(&mb->stop_state,
1418 MONITOR_STOPSTATE_STOPPED);
1421 /* Indicate that we are stopped */
1422 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1424 /* Wait for restart */
1425 while (!CPU_ISSET(cpu, &started_cpus)) {
1427 cpu_monitor(mb, 0, 0);
1428 if (atomic_load_int(&mb->stop_state) ==
1429 MONITOR_STOPSTATE_STOPPED)
1430 cpu_mwait(0, MWAIT_C1);
1437 * Halt non-BSP CPUs on panic -- we're never going to need them
1438 * again, and might as well save power / release resources
1439 * (e.g., overprovisioned VM infrastructure).
1441 while (__predict_false(!IS_BSP() && panicstr != NULL))
1445 cpustop_handler_post(cpu);
1449 cpustop_handler_post(u_int cpu)
1452 CPU_CLR_ATOMIC(cpu, &started_cpus);
1453 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1456 * We don't broadcast TLB invalidations to other CPUs when they are
1457 * stopped. Hence, we clear the TLB before resuming.
1461 #if defined(__amd64__) && defined(DDB)
1462 amd64_db_resume_dbreg();
1465 if (cpu == 0 && cpustop_restartfunc != NULL) {
1466 cpustop_restartfunc();
1467 cpustop_restartfunc = NULL;
1472 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1476 cpususpend_handler(void)
1480 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED);
1482 cpu = PCPU_GET(cpuid);
1483 if (savectx(&susppcbs[cpu]->sp_pcb)) {
1485 fpususpend(susppcbs[cpu]->sp_fpususpend);
1487 npxsuspend(susppcbs[cpu]->sp_fpususpend);
1490 * suspended_cpus is cleared shortly after each AP is restarted
1491 * by a Startup IPI, so that the BSP can proceed to restarting
1494 * resuming_cpus gets cleared when the AP completes
1495 * initialization after having been released by the BSP.
1496 * resuming_cpus is probably not the best name for the
1497 * variable, because it is actually a set of processors that
1498 * haven't resumed yet and haven't necessarily started resuming.
1500 * Note that suspended_cpus is meaningful only for ACPI suspend
1501 * as it's not really used for Xen suspend since the APs are
1502 * automatically restored to the running state and the correct
1503 * context. For the same reason resumectx is never called in
1506 CPU_SET_ATOMIC(cpu, &suspended_cpus);
1507 CPU_SET_ATOMIC(cpu, &resuming_cpus);
1510 * Invalidate the cache after setting the global status bits.
1511 * The last AP to set its bit may end up being an Owner of the
1512 * corresponding cache line in MOESI protocol. The AP may be
1513 * stopped before the cache line is written to the main memory.
1518 fpuresume(susppcbs[cpu]->sp_fpususpend);
1520 npxresume(susppcbs[cpu]->sp_fpususpend);
1524 PCPU_SET(switchtime, 0);
1525 PCPU_SET(switchticks, ticks);
1527 /* Indicate that we have restarted and restored the context. */
1528 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1531 /* Wait for resume directive */
1532 while (!CPU_ISSET(cpu, &toresume_cpus))
1535 /* Re-apply microcode updates. */
1539 /* Finish removing the identity mapping of low memory for this AP. */
1543 if (cpu_ops.cpu_resume)
1544 cpu_ops.cpu_resume();
1550 /* Resume MCA and local APIC */
1555 /* Indicate that we are resumed */
1556 CPU_CLR_ATOMIC(cpu, &resuming_cpus);
1557 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1558 CPU_CLR_ATOMIC(cpu, &toresume_cpus);
1563 invlcache_handler(void)
1565 uint32_t generation;
1568 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
1569 #endif /* COUNT_IPIS */
1572 * Reading the generation here allows greater parallelism
1573 * since wbinvd is a serializing instruction. Without the
1574 * temporary, we'd wait for wbinvd to complete, then the read
1575 * would execute, then the dependent write, which must then
1576 * complete before return from interrupt.
1578 generation = smp_tlb_generation;
1580 PCPU_SET(smp_tlb_done, generation);
1584 * This is called once the rest of the system is up and running and we're
1585 * ready to let the AP's out of the pen.
1588 release_aps(void *dummy __unused)
1593 atomic_store_rel_int(&aps_ready, 1);
1594 while (smp_started == 0)
1597 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1601 * Setup interrupt counters for IPI handlers.
1604 mp_ipi_intrcnt(void *dummy)
1610 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1611 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1612 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1613 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1614 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1615 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1616 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
1617 intrcnt_add(buf, &ipi_invlcache_counts[i]);
1618 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1619 intrcnt_add(buf, &ipi_preempt_counts[i]);
1620 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1621 intrcnt_add(buf, &ipi_ast_counts[i]);
1622 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1623 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1624 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1625 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1628 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
1632 * Flush the TLB on other CPU's
1635 /* Variables needed for SMP tlb shootdown. */
1636 vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
1637 pmap_t smp_tlb_pmap;
1638 volatile uint32_t smp_tlb_generation;
1641 #define read_eflags() read_rflags()
1645 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
1646 vm_offset_t addr1, vm_offset_t addr2)
1648 cpuset_t other_cpus;
1649 volatile uint32_t *p_cpudone;
1650 uint32_t generation;
1653 /* It is not necessary to signal other CPUs while in the debugger. */
1654 if (kdb_active || panicstr != NULL)
1658 * Check for other cpus. Return if none.
1660 if (CPU_ISFULLSET(&mask)) {
1664 CPU_CLR(PCPU_GET(cpuid), &mask);
1665 if (CPU_EMPTY(&mask))
1669 if (!(read_eflags() & PSL_I))
1670 panic("%s: interrupts disabled", __func__);
1671 mtx_lock_spin(&smp_ipi_mtx);
1672 smp_tlb_addr1 = addr1;
1673 smp_tlb_addr2 = addr2;
1674 smp_tlb_pmap = pmap;
1675 generation = ++smp_tlb_generation;
1676 if (CPU_ISFULLSET(&mask)) {
1677 ipi_all_but_self(vector);
1678 other_cpus = all_cpus;
1679 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1682 while ((cpu = CPU_FFS(&mask)) != 0) {
1684 CPU_CLR(cpu, &mask);
1685 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
1687 ipi_send_cpu(cpu, vector);
1690 while ((cpu = CPU_FFS(&other_cpus)) != 0) {
1692 CPU_CLR(cpu, &other_cpus);
1693 p_cpudone = &cpuid_to_pcpu[cpu]->pc_smp_tlb_done;
1694 while (*p_cpudone != generation)
1697 mtx_unlock_spin(&smp_ipi_mtx);
1701 smp_masked_invltlb(cpuset_t mask, pmap_t pmap)
1705 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0);
1706 #ifdef COUNT_XINVLTLB_HITS
1713 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr, pmap_t pmap)
1717 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, pmap, addr, 0);
1718 #ifdef COUNT_XINVLTLB_HITS
1725 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2,
1730 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, pmap,
1732 #ifdef COUNT_XINVLTLB_HITS
1734 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1740 smp_cache_flush(void)
1744 smp_targeted_tlb_shootdown(all_cpus, IPI_INVLCACHE, NULL,
1750 * Handlers for TLB related IPIs
1753 invltlb_handler(void)
1755 uint32_t generation;
1757 #ifdef COUNT_XINVLTLB_HITS
1758 xhits_gbl[PCPU_GET(cpuid)]++;
1759 #endif /* COUNT_XINVLTLB_HITS */
1761 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1762 #endif /* COUNT_IPIS */
1765 * Reading the generation here allows greater parallelism
1766 * since invalidating the TLB is a serializing operation.
1768 generation = smp_tlb_generation;
1769 if (smp_tlb_pmap == kernel_pmap)
1775 PCPU_SET(smp_tlb_done, generation);
1779 invlpg_handler(void)
1781 uint32_t generation;
1783 #ifdef COUNT_XINVLTLB_HITS
1784 xhits_pg[PCPU_GET(cpuid)]++;
1785 #endif /* COUNT_XINVLTLB_HITS */
1787 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1788 #endif /* COUNT_IPIS */
1790 generation = smp_tlb_generation; /* Overlap with serialization */
1792 if (smp_tlb_pmap == kernel_pmap)
1794 invlpg(smp_tlb_addr1);
1795 PCPU_SET(smp_tlb_done, generation);
1799 invlrng_handler(void)
1801 vm_offset_t addr, addr2;
1802 uint32_t generation;
1804 #ifdef COUNT_XINVLTLB_HITS
1805 xhits_rng[PCPU_GET(cpuid)]++;
1806 #endif /* COUNT_XINVLTLB_HITS */
1808 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
1809 #endif /* COUNT_IPIS */
1811 addr = smp_tlb_addr1;
1812 addr2 = smp_tlb_addr2;
1813 generation = smp_tlb_generation; /* Overlap with serialization */
1815 if (smp_tlb_pmap == kernel_pmap)
1820 } while (addr < addr2);
1822 PCPU_SET(smp_tlb_done, generation);