2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
34 #include "opt_kstack_pages.h"
36 #include "opt_sched.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/cons.h> /* cngetc() */
43 #include <sys/cpuset.h>
49 #include <sys/kernel.h>
52 #include <sys/malloc.h>
53 #include <sys/memrange.h>
54 #include <sys/mutex.h>
57 #include <sys/sched.h>
59 #include <sys/sysctl.h>
62 #include <vm/vm_param.h>
64 #include <vm/vm_kern.h>
65 #include <vm/vm_extern.h>
66 #include <vm/vm_map.h>
68 #include <x86/apicreg.h>
69 #include <machine/clock.h>
70 #include <machine/cpu.h>
71 #include <machine/cputypes.h>
73 #include <machine/md_var.h>
74 #include <machine/pcb.h>
75 #include <machine/psl.h>
76 #include <machine/smp.h>
77 #include <machine/specialreg.h>
78 #include <x86/ucode.h>
80 static MALLOC_DEFINE(M_CPUS, "cpus", "CPU items");
82 /* lock region used by kernel profiling */
85 int mp_naps; /* # of Applications processors */
86 int boot_cpu_id = -1; /* designated BSP */
88 /* AP uses this during bootstrap. Do not staticize. */
92 /* Free these after use */
93 void *bootstacks[MAXCPU];
96 struct pcb stoppcbs[MAXCPU];
97 struct susppcb **susppcbs;
100 /* Interrupt counts. */
101 static u_long *ipi_preempt_counts[MAXCPU];
102 static u_long *ipi_ast_counts[MAXCPU];
103 u_long *ipi_invltlb_counts[MAXCPU];
104 u_long *ipi_invlrng_counts[MAXCPU];
105 u_long *ipi_invlpg_counts[MAXCPU];
106 u_long *ipi_invlcache_counts[MAXCPU];
107 u_long *ipi_rendezvous_counts[MAXCPU];
108 static u_long *ipi_hardclock_counts[MAXCPU];
111 /* Default cpu_ops implementation. */
112 struct cpu_ops cpu_ops;
115 * Local data and functions.
118 static volatile cpuset_t ipi_stop_nmi_pending;
120 volatile cpuset_t resuming_cpus;
121 volatile cpuset_t toresume_cpus;
123 /* used to hold the AP's until we are ready to release them */
124 struct mtx ap_boot_mtx;
126 /* Set to 1 once we're ready to let the APs out of the pen. */
127 volatile int aps_ready = 0;
130 * Store data from cpu_add() until later in the boot when we actually setup
133 struct cpu_info *cpu_info;
135 int cpu_apic_ids[MAXCPU];
136 _Static_assert(MAXCPU <= MAX_APIC_ID,
137 "MAXCPU cannot be larger that MAX_APIC_ID");
138 _Static_assert(xAPIC_MAX_APIC_ID <= MAX_APIC_ID,
139 "xAPIC_MAX_APIC_ID cannot be larger that MAX_APIC_ID");
141 static void release_aps(void *dummy);
142 static void cpustop_handler_post(u_int cpu);
144 static int hyperthreading_allowed = 1;
145 SYSCTL_INT(_machdep, OID_AUTO, hyperthreading_allowed, CTLFLAG_RDTUN,
146 &hyperthreading_allowed, 0, "Use Intel HTT logical CPUs");
148 static int hyperthreading_intr_allowed = 0;
149 SYSCTL_INT(_machdep, OID_AUTO, hyperthreading_intr_allowed, CTLFLAG_RDTUN,
150 &hyperthreading_intr_allowed, 0,
151 "Allow interrupts on HTT logical CPUs");
153 static struct topo_node topo_root;
155 static int pkg_id_shift;
156 static int node_id_shift;
157 static int core_id_shift;
158 static int disabled_cpus;
163 } static caches[MAX_CACHE_LEVELS];
165 unsigned int boot_address;
167 static bool stop_mwait = false;
168 SYSCTL_BOOL(_machdep, OID_AUTO, stop_mwait, CTLFLAG_RWTUN, &stop_mwait, 0,
169 "Use MONITOR/MWAIT when stopping CPU, if available");
171 #define MiB(v) (v ## ULL << 20)
174 mem_range_AP_init(void)
177 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
178 mem_range_softc.mr_op->initAP(&mem_range_softc);
182 * Round up to the next power of two, if necessary, and then
184 * Returns -1 if argument is zero.
190 return (fls(x << (1 - powerof2(x))) - 1);
194 * Add a cache level to the cache topology description.
197 add_deterministic_cache(int type, int level, int share_count)
203 printf("unexpected cache type %d\n", type);
206 if (type == 2) /* ignore instruction cache */
208 if (level == 0 || level > MAX_CACHE_LEVELS) {
209 printf("unexpected cache level %d\n", type);
213 if (caches[level - 1].present) {
214 printf("WARNING: multiple entries for L%u data cache\n", level);
215 printf("%u => %u\n", caches[level - 1].id_shift,
216 mask_width(share_count));
218 caches[level - 1].id_shift = mask_width(share_count);
219 caches[level - 1].present = 1;
221 if (caches[level - 1].id_shift > pkg_id_shift) {
222 printf("WARNING: L%u data cache covers more "
223 "APIC IDs than a package (%u > %u)\n", level,
224 caches[level - 1].id_shift, pkg_id_shift);
225 caches[level - 1].id_shift = pkg_id_shift;
227 if (caches[level - 1].id_shift < core_id_shift) {
228 printf("WARNING: L%u data cache covers fewer "
229 "APIC IDs than a core (%u < %u)\n", level,
230 caches[level - 1].id_shift, core_id_shift);
231 caches[level - 1].id_shift = core_id_shift;
238 * Determine topology of processing units and caches for AMD CPUs.
240 * - AMD CPUID Specification (Publication # 25481)
241 * - BKDG for AMD NPT Family 0Fh Processors (Publication # 32559)
242 * - BKDG For AMD Family 10h Processors (Publication # 31116)
243 * - BKDG For AMD Family 15h Models 00h-0Fh Processors (Publication # 42301)
244 * - BKDG For AMD Family 16h Models 00h-0Fh Processors (Publication # 48751)
245 * - PPR For AMD Family 17h Models 00h-0Fh Processors (Publication # 54945)
253 int nodes_per_socket;
258 /* No multi-core capability. */
259 if ((amd_feature2 & AMDID2_CMP) == 0)
262 /* For families 10h and newer. */
263 pkg_id_shift = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
264 AMDID_COREID_SIZE_SHIFT;
266 /* For 0Fh family. */
267 if (pkg_id_shift == 0)
269 mask_width((cpu_procinfo2 & AMDID_CMP_CORES) + 1);
272 * Families prior to 16h define the following value as
273 * cores per compute unit and we don't really care about the AMD
274 * compute units at the moment. Perhaps we should treat them as
275 * cores and cores within the compute units as hardware threads,
276 * but that's up for debate.
277 * Later families define the value as threads per compute unit,
278 * so we are following AMD's nomenclature here.
280 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0 &&
281 CPUID_TO_FAMILY(cpu_id) >= 0x16) {
282 cpuid_count(0x8000001e, 0, p);
283 share_count = ((p[1] >> 8) & 0xff) + 1;
284 core_id_shift = mask_width(share_count);
287 * For Zen (17h), gather Nodes per Processor. Each node is a
288 * Zeppelin die; TR and EPYC CPUs will have multiple dies per
289 * package. Communication latency between dies is higher than
292 nodes_per_socket = ((p[2] >> 8) & 0x7) + 1;
293 node_id_shift = pkg_id_shift - mask_width(nodes_per_socket);
296 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0) {
298 cpuid_count(0x8000001d, i, p);
300 level = (p[0] >> 5) & 0x7;
301 share_count = 1 + ((p[0] >> 14) & 0xfff);
303 if (!add_deterministic_cache(type, level, share_count))
307 if (cpu_exthigh >= 0x80000005) {
308 cpuid_count(0x80000005, 0, p);
309 if (((p[2] >> 24) & 0xff) != 0) {
310 caches[0].id_shift = 0;
311 caches[0].present = 1;
314 if (cpu_exthigh >= 0x80000006) {
315 cpuid_count(0x80000006, 0, p);
316 if (((p[2] >> 16) & 0xffff) != 0) {
317 caches[1].id_shift = 0;
318 caches[1].present = 1;
320 if (((p[3] >> 18) & 0x3fff) != 0) {
321 nodes_per_socket = 1;
322 if ((amd_feature2 & AMDID2_NODE_ID) != 0) {
324 * Handle multi-node processors that
325 * have multiple chips, each with its
326 * own L3 cache, on the same die.
328 v = rdmsr(0xc001100c);
329 nodes_per_socket = 1 + ((v >> 3) & 0x7);
332 pkg_id_shift - mask_width(nodes_per_socket);
333 caches[2].present = 1;
340 * Determine topology of processing units for Intel CPUs
341 * using CPUID Leaf 1 and Leaf 4, if supported.
343 * - Intel 64 Architecture Processor Topology Enumeration
344 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
345 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
346 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
349 topo_probe_intel_0x4(void)
355 /* Both zero and one here mean one logical processor per package. */
356 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
357 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
358 if (max_logical <= 1)
361 if (cpu_high >= 0x4) {
362 cpuid_count(0x04, 0, p);
363 max_cores = ((p[0] >> 26) & 0x3f) + 1;
367 core_id_shift = mask_width(max_logical/max_cores);
368 KASSERT(core_id_shift >= 0,
369 ("intel topo: max_cores > max_logical\n"));
370 pkg_id_shift = core_id_shift + mask_width(max_cores);
374 * Determine topology of processing units for Intel CPUs
375 * using CPUID Leaf 11, if supported.
377 * - Intel 64 Architecture Processor Topology Enumeration
378 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
379 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
380 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
383 topo_probe_intel_0xb(void)
390 /* Fall back if CPU leaf 11 doesn't really exist. */
391 cpuid_count(0x0b, 0, p);
393 topo_probe_intel_0x4();
397 /* We only support three levels for now. */
399 cpuid_count(0x0b, i, p);
402 type = (p[2] >> 8) & 0xff;
407 /* TODO: check for duplicate (re-)assignment */
408 if (type == CPUID_TYPE_SMT)
409 core_id_shift = bits;
410 else if (type == CPUID_TYPE_CORE)
413 printf("unknown CPU level type %d\n", type);
416 if (pkg_id_shift < core_id_shift) {
417 printf("WARNING: core covers more APIC IDs than a package\n");
418 core_id_shift = pkg_id_shift;
423 * Determine topology of caches for Intel CPUs.
425 * - Intel 64 Architecture Processor Topology Enumeration
426 * - Intel 64 and IA-32 Architectures Software Developer’s Manual
427 * Volume 2A: Instruction Set Reference, A-M,
431 topo_probe_intel_caches(void)
439 if (cpu_high < 0x4) {
441 * Available cache level and sizes can be determined
442 * via CPUID leaf 2, but that requires a huge table of hardcoded
443 * values, so for now just assume L1 and L2 caches potentially
444 * shared only by HTT processing units, if HTT is present.
446 caches[0].id_shift = pkg_id_shift;
447 caches[0].present = 1;
448 caches[1].id_shift = pkg_id_shift;
449 caches[1].present = 1;
454 cpuid_count(0x4, i, p);
456 level = (p[0] >> 5) & 0x7;
457 share_count = 1 + ((p[0] >> 14) & 0xfff);
459 if (!add_deterministic_cache(type, level, share_count))
465 * Determine topology of processing units and caches for Intel CPUs.
467 * - Intel 64 Architecture Processor Topology Enumeration
470 topo_probe_intel(void)
474 * Note that 0x1 <= cpu_high < 4 case should be
475 * compatible with topo_probe_intel_0x4() logic when
476 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
477 * or it should trigger the fallback otherwise.
480 topo_probe_intel_0xb();
481 else if (cpu_high >= 0x1)
482 topo_probe_intel_0x4();
484 topo_probe_intel_caches();
488 * Topology information is queried only on BSP, on which this
489 * code runs and for which it can query CPUID information.
490 * Then topology is extrapolated on all packages using an
491 * assumption that APIC ID to hardware component ID mapping is
493 * That doesn't necesserily imply that the topology is uniform.
498 static int cpu_topo_probed = 0;
499 struct x86_topo_layer {
503 } topo_layers[MAX_CACHE_LEVELS + 4];
504 struct topo_node *parent;
505 struct topo_node *node;
514 CPU_ZERO(&logical_cpus_mask);
518 else if (cpu_vendor_id == CPU_VENDOR_AMD)
520 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
523 KASSERT(pkg_id_shift >= core_id_shift,
524 ("bug in APIC topology discovery"));
527 bzero(topo_layers, sizeof(topo_layers));
529 topo_layers[nlayers].type = TOPO_TYPE_PKG;
530 topo_layers[nlayers].id_shift = pkg_id_shift;
532 printf("Package ID shift: %u\n", topo_layers[nlayers].id_shift);
535 if (pkg_id_shift > node_id_shift && node_id_shift != 0) {
536 topo_layers[nlayers].type = TOPO_TYPE_GROUP;
537 topo_layers[nlayers].id_shift = node_id_shift;
539 printf("Node ID shift: %u\n",
540 topo_layers[nlayers].id_shift);
545 * Consider all caches to be within a package/chip
546 * and "in front" of all sub-components like
547 * cores and hardware threads.
549 for (i = MAX_CACHE_LEVELS - 1; i >= 0; --i) {
550 if (caches[i].present) {
551 if (node_id_shift != 0)
552 KASSERT(caches[i].id_shift <= node_id_shift,
553 ("bug in APIC topology discovery"));
554 KASSERT(caches[i].id_shift <= pkg_id_shift,
555 ("bug in APIC topology discovery"));
556 KASSERT(caches[i].id_shift >= core_id_shift,
557 ("bug in APIC topology discovery"));
559 topo_layers[nlayers].type = TOPO_TYPE_CACHE;
560 topo_layers[nlayers].subtype = i + 1;
561 topo_layers[nlayers].id_shift = caches[i].id_shift;
563 printf("L%u cache ID shift: %u\n",
564 topo_layers[nlayers].subtype,
565 topo_layers[nlayers].id_shift);
570 if (pkg_id_shift > core_id_shift) {
571 topo_layers[nlayers].type = TOPO_TYPE_CORE;
572 topo_layers[nlayers].id_shift = core_id_shift;
574 printf("Core ID shift: %u\n",
575 topo_layers[nlayers].id_shift);
579 topo_layers[nlayers].type = TOPO_TYPE_PU;
580 topo_layers[nlayers].id_shift = 0;
583 topo_init_root(&topo_root);
584 for (i = 0; i <= max_apic_id; ++i) {
585 if (!cpu_info[i].cpu_present)
589 for (layer = 0; layer < nlayers; ++layer) {
590 node_id = i >> topo_layers[layer].id_shift;
591 parent = topo_add_node_by_hwid(parent, node_id,
592 topo_layers[layer].type,
593 topo_layers[layer].subtype);
598 for (layer = 0; layer < nlayers; ++layer) {
599 node_id = boot_cpu_id >> topo_layers[layer].id_shift;
600 node = topo_find_node_by_hwid(parent, node_id,
601 topo_layers[layer].type,
602 topo_layers[layer].subtype);
603 topo_promote_child(node);
611 * Assign logical CPU IDs to local APICs.
616 struct topo_node *node;
620 smt_mask = (1u << core_id_shift) - 1;
623 * Assign CPU IDs to local APIC IDs and disable any CPUs
624 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
628 TOPO_FOREACH(node, &topo_root) {
629 if (node->type != TOPO_TYPE_PU)
632 if ((node->hwid & smt_mask) != (boot_cpu_id & smt_mask))
633 cpu_info[node->hwid].cpu_hyperthread = 1;
635 if (resource_disabled("lapic", node->hwid)) {
636 if (node->hwid != boot_cpu_id)
637 cpu_info[node->hwid].cpu_disabled = 1;
639 printf("Cannot disable BSP, APIC ID = %d\n",
643 if (!hyperthreading_allowed &&
644 cpu_info[node->hwid].cpu_hyperthread)
645 cpu_info[node->hwid].cpu_disabled = 1;
647 if (mp_ncpus >= MAXCPU)
648 cpu_info[node->hwid].cpu_disabled = 1;
650 if (cpu_info[node->hwid].cpu_disabled) {
655 if (cpu_info[node->hwid].cpu_hyperthread)
658 cpu_apic_ids[mp_ncpus] = node->hwid;
659 apic_cpuids[node->hwid] = mp_ncpus;
660 topo_set_pu_id(node, mp_ncpus);
664 KASSERT(mp_maxid >= mp_ncpus - 1,
665 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
668 mp_ncores = mp_ncpus - nhyper;
669 smp_threads_per_core = mp_ncpus / mp_ncores;
673 * Print various information about the SMP system hardware and setup.
676 cpu_mp_announce(void)
678 struct topo_node *node;
679 const char *hyperthread;
680 struct topo_analysis topology;
682 printf("FreeBSD/SMP: ");
683 if (topo_analyze(&topo_root, 1, &topology)) {
684 printf("%d package(s)", topology.entities[TOPO_LEVEL_PKG]);
685 if (topology.entities[TOPO_LEVEL_GROUP] > 1)
686 printf(" x %d groups",
687 topology.entities[TOPO_LEVEL_GROUP]);
688 if (topology.entities[TOPO_LEVEL_CACHEGROUP] > 1)
689 printf(" x %d cache groups",
690 topology.entities[TOPO_LEVEL_CACHEGROUP]);
691 if (topology.entities[TOPO_LEVEL_CORE] > 0)
692 printf(" x %d core(s)",
693 topology.entities[TOPO_LEVEL_CORE]);
694 if (topology.entities[TOPO_LEVEL_THREAD] > 1)
695 printf(" x %d hardware threads",
696 topology.entities[TOPO_LEVEL_THREAD]);
698 printf("Non-uniform topology");
703 printf("FreeBSD/SMP Online: ");
704 if (topo_analyze(&topo_root, 0, &topology)) {
705 printf("%d package(s)",
706 topology.entities[TOPO_LEVEL_PKG]);
707 if (topology.entities[TOPO_LEVEL_GROUP] > 1)
708 printf(" x %d groups",
709 topology.entities[TOPO_LEVEL_GROUP]);
710 if (topology.entities[TOPO_LEVEL_CACHEGROUP] > 1)
711 printf(" x %d cache groups",
712 topology.entities[TOPO_LEVEL_CACHEGROUP]);
713 if (topology.entities[TOPO_LEVEL_CORE] > 0)
714 printf(" x %d core(s)",
715 topology.entities[TOPO_LEVEL_CORE]);
716 if (topology.entities[TOPO_LEVEL_THREAD] > 1)
717 printf(" x %d hardware threads",
718 topology.entities[TOPO_LEVEL_THREAD]);
720 printf("Non-uniform topology");
728 TOPO_FOREACH(node, &topo_root) {
729 switch (node->type) {
731 printf("Package HW ID = %u\n", node->hwid);
734 printf("\tCore HW ID = %u\n", node->hwid);
737 if (cpu_info[node->hwid].cpu_hyperthread)
742 if (node->subtype == 0)
743 printf("\t\tCPU (AP%s): APIC ID: %u"
744 "(disabled)\n", hyperthread, node->hwid);
745 else if (node->id == 0)
746 printf("\t\tCPU0 (BSP): APIC ID: %u\n",
749 printf("\t\tCPU%u (AP%s): APIC ID: %u\n",
750 node->id, hyperthread, node->hwid);
760 * Add a scheduling group, a group of logical processors sharing
761 * a particular cache (and, thus having an affinity), to the scheduling
763 * This function recursively works on lower level caches.
766 x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
768 struct topo_node *node;
773 KASSERT(root->type == TOPO_TYPE_SYSTEM || root->type == TOPO_TYPE_CACHE ||
774 root->type == TOPO_TYPE_GROUP,
775 ("x86topo_add_sched_group: bad type: %u", root->type));
776 CPU_COPY(&root->cpuset, &cg_root->cg_mask);
777 cg_root->cg_count = root->cpu_count;
778 if (root->type == TOPO_TYPE_SYSTEM)
779 cg_root->cg_level = CG_SHARE_NONE;
781 cg_root->cg_level = root->subtype;
784 * Check how many core nodes we have under the given root node.
785 * If we have multiple logical processors, but not multiple
786 * cores, then those processors must be hardware threads.
790 while (node != NULL) {
791 if (node->type != TOPO_TYPE_CORE) {
792 node = topo_next_node(root, node);
797 node = topo_next_nonchild_node(root, node);
800 if (cg_root->cg_level != CG_SHARE_NONE &&
801 root->cpu_count > 1 && ncores < 2)
802 cg_root->cg_flags = CG_FLAG_SMT;
805 * Find out how many cache nodes we have under the given root node.
806 * We ignore cache nodes that cover all the same processors as the
807 * root node. Also, we do not descend below found cache nodes.
808 * That is, we count top-level "non-redundant" caches under the root
813 while (node != NULL) {
814 if ((node->type != TOPO_TYPE_GROUP &&
815 node->type != TOPO_TYPE_CACHE) ||
816 (root->type != TOPO_TYPE_SYSTEM &&
817 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
818 node = topo_next_node(root, node);
822 node = topo_next_nonchild_node(root, node);
825 cg_root->cg_child = smp_topo_alloc(nchildren);
826 cg_root->cg_children = nchildren;
829 * Now find again the same cache nodes as above and recursively
830 * build scheduling topologies for them.
834 while (node != NULL) {
835 if ((node->type != TOPO_TYPE_GROUP &&
836 node->type != TOPO_TYPE_CACHE) ||
837 (root->type != TOPO_TYPE_SYSTEM &&
838 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
839 node = topo_next_node(root, node);
842 cg_root->cg_child[i].cg_parent = cg_root;
843 x86topo_add_sched_group(node, &cg_root->cg_child[i]);
845 node = topo_next_nonchild_node(root, node);
850 * Build the MI scheduling topology from the discovered hardware topology.
855 struct cpu_group *cg_root;
858 return (smp_topo_none());
860 cg_root = smp_topo_alloc(1);
861 x86topo_add_sched_group(&topo_root, cg_root);
866 cpu_alloc(void *dummy __unused)
869 * Dynamically allocate the arrays that depend on the
872 cpu_info = malloc(sizeof(*cpu_info) * (max_apic_id + 1), M_CPUS,
874 apic_cpuids = malloc(sizeof(*apic_cpuids) * (max_apic_id + 1), M_CPUS,
877 SYSINIT(cpu_alloc, SI_SUB_CPU, SI_ORDER_FIRST, cpu_alloc, NULL);
880 * Add a logical CPU to the topology.
883 cpu_add(u_int apic_id, char boot_cpu)
886 if (apic_id > max_apic_id) {
887 panic("SMP: APIC ID %d too high", apic_id);
890 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %u added twice",
892 cpu_info[apic_id].cpu_present = 1;
894 KASSERT(boot_cpu_id == -1,
895 ("CPU %u claims to be BSP, but CPU %u already is", apic_id,
897 boot_cpu_id = apic_id;
898 cpu_info[apic_id].cpu_bsp = 1;
901 printf("SMP: Added CPU %u (%s)\n", apic_id, boot_cpu ? "BSP" :
906 cpu_mp_setmaxid(void)
910 * mp_ncpus and mp_maxid should be already set by calls to cpu_add().
911 * If there were no calls to cpu_add() assume this is a UP system.
922 * Always record BSP in CPU map so that the mbuf init code works
925 CPU_SETOF(0, &all_cpus);
926 return (mp_ncpus > 1);
929 /* Allocate memory for the AP trampoline. */
931 alloc_ap_trampoline(vm_paddr_t *physmap, unsigned int *physmap_idx)
937 for (i = *physmap_idx; i <= *physmap_idx; i -= 2) {
939 * Find a memory region big enough and below the 1MB boundary
940 * for the trampoline code.
941 * NB: needs to be page aligned.
943 if (physmap[i] >= MiB(1) ||
944 (trunc_page(physmap[i + 1]) - round_page(physmap[i])) <
945 round_page(bootMP_size))
950 * Try to steal from the end of the region to mimic previous
951 * behaviour, else fallback to steal from the start.
953 if (physmap[i + 1] < MiB(1)) {
954 boot_address = trunc_page(physmap[i + 1]);
955 if ((physmap[i + 1] - boot_address) < bootMP_size)
956 boot_address -= round_page(bootMP_size);
957 physmap[i + 1] = boot_address;
959 boot_address = round_page(physmap[i]);
960 physmap[i] = boot_address + round_page(bootMP_size);
962 if (physmap[i] == physmap[i + 1] && *physmap_idx != 0) {
963 memmove(&physmap[i], &physmap[i + 2],
964 sizeof(*physmap) * (*physmap_idx - i + 2));
971 boot_address = basemem * 1024 - bootMP_size;
974 "Cannot find enough space for the boot trampoline, placing it at %#x",
980 * AP CPU's call this to initialize themselves.
983 init_secondary_tail(void)
987 pmap_activate_boot(vmspace_pmap(proc0.p_vmspace));
990 * On real hardware, switch to x2apic mode if possible. Do it
991 * after aps_ready was signalled, to avoid manipulating the
992 * mode while BSP might still want to send some IPI to us
993 * (second startup IPI is ignored on modern hardware etc).
997 /* Initialize the PAT MSR. */
1000 /* set up CPU registers and state */
1006 /* set up FPU state on the AP */
1013 if (cpu_ops.cpu_init)
1016 /* A quick check from sanity claus */
1017 cpuid = PCPU_GET(cpuid);
1018 if (PCPU_GET(apic_id) != lapic_id()) {
1019 printf("SMP: cpuid = %d\n", cpuid);
1020 printf("SMP: actual apic_id = %d\n", lapic_id());
1021 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
1022 panic("cpuid mismatch! boom!!");
1025 /* Initialize curthread. */
1026 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
1027 PCPU_SET(curthread, PCPU_GET(idlethread));
1029 mtx_lock_spin(&ap_boot_mtx);
1033 /* Init local apic for irq's */
1036 /* Set memory range attributes for this CPU to match the BSP */
1037 mem_range_AP_init();
1041 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
1043 printf("SMP: AP CPU #%d Launched!\n", cpuid);
1045 printf("%s%d%s", smp_cpus == 2 ? "Launching APs: " : "",
1046 cpuid, smp_cpus == mp_ncpus ? "\n" : " ");
1048 /* Determine if we are a logical CPU. */
1049 if (cpu_info[PCPU_GET(apic_id)].cpu_hyperthread)
1050 CPU_SET(cpuid, &logical_cpus_mask);
1055 if (smp_cpus == mp_ncpus) {
1056 /* enable IPI's, tlb shootdown, freezes etc */
1057 atomic_store_rel_int(&smp_started, 1);
1062 * Enable global pages TLB extension
1063 * This also implicitly flushes the TLB
1065 load_cr4(rcr4() | CR4_PGE);
1066 if (pmap_pcid_enabled)
1067 load_cr4(rcr4() | CR4_PCIDE);
1073 mtx_unlock_spin(&ap_boot_mtx);
1075 /* Wait until all the AP's are up. */
1076 while (atomic_load_acq_int(&smp_started) == 0)
1079 #ifndef EARLY_AP_STARTUP
1080 /* Start per-CPU event timers. */
1081 cpu_initclocks_ap();
1084 kcsan_cpu_init(cpuid);
1088 panic("scheduler returned us to %s", __func__);
1093 smp_after_idle_runnable(void *arg __unused)
1098 for (cpu = 1; cpu < mp_ncpus; cpu++) {
1099 pc = pcpu_find(cpu);
1100 while (atomic_load_ptr(&pc->pc_curthread) == (uintptr_t)NULL)
1102 kmem_free((vm_offset_t)bootstacks[cpu], kstack_pages *
1106 SYSINIT(smp_after_idle_runnable, SI_SUB_SMP, SI_ORDER_ANY,
1107 smp_after_idle_runnable, NULL);
1110 * We tell the I/O APIC code about all the CPUs we want to receive
1111 * interrupts. If we don't want certain CPUs to receive IRQs we
1112 * can simply not tell the I/O APIC code about them in this function.
1113 * We also do not tell it about the BSP since it tells itself about
1114 * the BSP internally to work with UP kernels and on UP machines.
1117 set_interrupt_apic_ids(void)
1121 for (i = 0; i < MAXCPU; i++) {
1122 apic_id = cpu_apic_ids[i];
1125 if (cpu_info[apic_id].cpu_bsp)
1127 if (cpu_info[apic_id].cpu_disabled)
1130 /* Don't let hyperthreads service interrupts. */
1131 if (cpu_info[apic_id].cpu_hyperthread &&
1132 !hyperthreading_intr_allowed)
1140 #ifdef COUNT_XINVLTLB_HITS
1141 u_int xhits_gbl[MAXCPU];
1142 u_int xhits_pg[MAXCPU];
1143 u_int xhits_rng[MAXCPU];
1144 static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1145 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1146 sizeof(xhits_gbl), "IU", "");
1147 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1148 sizeof(xhits_pg), "IU", "");
1149 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1150 sizeof(xhits_rng), "IU", "");
1155 u_int ipi_range_size;
1156 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1157 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1158 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1159 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1161 #endif /* COUNT_XINVLTLB_HITS */
1164 * Init and startup IPI.
1167 ipi_startup(int apic_id, int vector)
1171 * This attempts to follow the algorithm described in the
1172 * Intel Multiprocessor Specification v1.4 in section B.4.
1173 * For each IPI, we allow the local APIC ~20us to deliver the
1174 * IPI. If that times out, we panic.
1178 * first we do an INIT IPI: this INIT IPI might be run, resetting
1179 * and running the target CPU. OR this INIT IPI might be latched (P5
1180 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1183 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1184 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1185 lapic_ipi_wait(100);
1187 /* Explicitly deassert the INIT IPI. */
1188 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1189 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT,
1192 DELAY(10000); /* wait ~10mS */
1195 * next we do a STARTUP IPI: the previous INIT IPI might still be
1196 * latched, (P5 bug) this 1st STARTUP would then terminate
1197 * immediately, and the previously started INIT IPI would continue. OR
1198 * the previous INIT IPI has already run. and this STARTUP IPI will
1199 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1202 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1203 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1205 if (!lapic_ipi_wait(100))
1206 panic("Failed to deliver first STARTUP IPI to APIC %d",
1208 DELAY(200); /* wait ~200uS */
1211 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1212 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1213 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1214 * recognized after hardware RESET or INIT IPI.
1216 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1217 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1219 if (!lapic_ipi_wait(100))
1220 panic("Failed to deliver second STARTUP IPI to APIC %d",
1223 DELAY(200); /* wait ~200uS */
1227 * Send an IPI to specified CPU handling the bitmap logic.
1230 ipi_send_cpu(int cpu, u_int ipi)
1232 u_int bitmap, old, new;
1235 KASSERT((u_int)cpu < MAXCPU && cpu_apic_ids[cpu] != -1,
1236 ("IPI to non-existent CPU %d", cpu));
1238 if (IPI_IS_BITMAPED(ipi)) {
1240 ipi = IPI_BITMAP_VECTOR;
1241 cpu_bitmap = &cpuid_to_pcpu[cpu]->pc_ipi_bitmap;
1244 if ((old & bitmap) == bitmap)
1247 if (atomic_fcmpset_int(cpu_bitmap, &old, new))
1253 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1257 ipi_bitmap_handler(struct trapframe frame)
1259 struct trapframe *oldframe;
1261 int cpu = PCPU_GET(cpuid);
1265 ipi_bitmap = atomic_readandclear_int(&cpuid_to_pcpu[cpu]->
1269 * sched_preempt() must be called to clear the pending preempt
1270 * IPI to enable delivery of further preempts. However, the
1271 * critical section will cause extra scheduler lock thrashing
1272 * when used unconditionally. Only critical_enter() if
1273 * hardclock must also run, which requires the section entry.
1275 if (ipi_bitmap & (1 << IPI_HARDCLOCK))
1278 td->td_intr_nesting_level++;
1279 oldframe = td->td_intr_frame;
1280 td->td_intr_frame = &frame;
1281 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1283 (*ipi_preempt_counts[cpu])++;
1287 if (ipi_bitmap & (1 << IPI_AST)) {
1289 (*ipi_ast_counts[cpu])++;
1291 /* Nothing to do for AST */
1293 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1295 (*ipi_hardclock_counts[cpu])++;
1299 td->td_intr_frame = oldframe;
1300 td->td_intr_nesting_level--;
1301 if (ipi_bitmap & (1 << IPI_HARDCLOCK))
1306 * send an IPI to a set of cpus.
1309 ipi_selected(cpuset_t cpus, u_int ipi)
1314 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1315 * of help in order to understand what is the source.
1316 * Set the mask of receiving CPUs for this purpose.
1318 if (ipi == IPI_STOP_HARD)
1319 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &cpus);
1321 while ((cpu = CPU_FFS(&cpus)) != 0) {
1323 CPU_CLR(cpu, &cpus);
1324 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1325 ipi_send_cpu(cpu, ipi);
1330 * send an IPI to a specific CPU.
1333 ipi_cpu(int cpu, u_int ipi)
1337 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1338 * of help in order to understand what is the source.
1339 * Set the mask of receiving CPUs for this purpose.
1341 if (ipi == IPI_STOP_HARD)
1342 CPU_SET_ATOMIC(cpu, &ipi_stop_nmi_pending);
1344 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1345 ipi_send_cpu(cpu, ipi);
1349 * send an IPI to all CPUs EXCEPT myself
1352 ipi_all_but_self(u_int ipi)
1354 cpuset_t other_cpus;
1356 other_cpus = all_cpus;
1357 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1358 if (IPI_IS_BITMAPED(ipi)) {
1359 ipi_selected(other_cpus, ipi);
1364 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1365 * of help in order to understand what is the source.
1366 * Set the mask of receiving CPUs for this purpose.
1368 if (ipi == IPI_STOP_HARD)
1369 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &other_cpus);
1371 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1372 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1376 ipi_nmi_handler(void)
1381 * As long as there is not a simple way to know about a NMI's
1382 * source, if the bitmask for the current CPU is present in
1383 * the global pending bitword an IPI_STOP_HARD has been issued
1384 * and should be handled.
1386 cpuid = PCPU_GET(cpuid);
1387 if (!CPU_ISSET(cpuid, &ipi_stop_nmi_pending))
1390 CPU_CLR_ATOMIC(cpuid, &ipi_stop_nmi_pending);
1398 nmi_call_kdb_smp(u_int type, struct trapframe *frame)
1403 cpu = PCPU_GET(cpuid);
1404 if (atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1)) {
1405 nmi_call_kdb(cpu, type, frame);
1408 savectx(&stoppcbs[cpu]);
1409 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1410 while (!atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1))
1414 atomic_store_rel_int(&nmi_kdb_lock, 0);
1416 cpustop_handler_post(cpu);
1420 * Handle an IPI_STOP by saving our current context and spinning (or mwaiting,
1421 * if available) until we are resumed.
1424 cpustop_handler(void)
1426 struct monitorbuf *mb;
1430 cpu = PCPU_GET(cpuid);
1432 savectx(&stoppcbs[cpu]);
1434 use_mwait = (stop_mwait && (cpu_feature2 & CPUID2_MON) != 0 &&
1435 !mwait_cpustop_broken);
1437 mb = PCPU_PTR(monitorbuf);
1438 atomic_store_int(&mb->stop_state,
1439 MONITOR_STOPSTATE_STOPPED);
1442 /* Indicate that we are stopped */
1443 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1445 /* Wait for restart */
1446 while (!CPU_ISSET(cpu, &started_cpus)) {
1448 cpu_monitor(mb, 0, 0);
1449 if (atomic_load_int(&mb->stop_state) ==
1450 MONITOR_STOPSTATE_STOPPED)
1451 cpu_mwait(0, MWAIT_C1);
1458 * Halt non-BSP CPUs on panic -- we're never going to need them
1459 * again, and might as well save power / release resources
1460 * (e.g., overprovisioned VM infrastructure).
1462 while (__predict_false(!IS_BSP() && KERNEL_PANICKED()))
1466 cpustop_handler_post(cpu);
1470 cpustop_handler_post(u_int cpu)
1473 CPU_CLR_ATOMIC(cpu, &started_cpus);
1474 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1477 * We don't broadcast TLB invalidations to other CPUs when they are
1478 * stopped. Hence, we clear the TLB before resuming.
1482 #if defined(__amd64__) && defined(DDB)
1483 amd64_db_resume_dbreg();
1486 if (cpu == 0 && cpustop_restartfunc != NULL) {
1487 cpustop_restartfunc();
1488 cpustop_restartfunc = NULL;
1493 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1497 cpususpend_handler(void)
1501 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED);
1503 cpu = PCPU_GET(cpuid);
1504 if (savectx(&susppcbs[cpu]->sp_pcb)) {
1506 fpususpend(susppcbs[cpu]->sp_fpususpend);
1508 npxsuspend(susppcbs[cpu]->sp_fpususpend);
1511 * suspended_cpus is cleared shortly after each AP is restarted
1512 * by a Startup IPI, so that the BSP can proceed to restarting
1515 * resuming_cpus gets cleared when the AP completes
1516 * initialization after having been released by the BSP.
1517 * resuming_cpus is probably not the best name for the
1518 * variable, because it is actually a set of processors that
1519 * haven't resumed yet and haven't necessarily started resuming.
1521 * Note that suspended_cpus is meaningful only for ACPI suspend
1522 * as it's not really used for Xen suspend since the APs are
1523 * automatically restored to the running state and the correct
1524 * context. For the same reason resumectx is never called in
1527 CPU_SET_ATOMIC(cpu, &suspended_cpus);
1528 CPU_SET_ATOMIC(cpu, &resuming_cpus);
1531 * Invalidate the cache after setting the global status bits.
1532 * The last AP to set its bit may end up being an Owner of the
1533 * corresponding cache line in MOESI protocol. The AP may be
1534 * stopped before the cache line is written to the main memory.
1539 fpuresume(susppcbs[cpu]->sp_fpususpend);
1541 npxresume(susppcbs[cpu]->sp_fpususpend);
1545 PCPU_SET(switchtime, 0);
1546 PCPU_SET(switchticks, ticks);
1548 /* Indicate that we have restarted and restored the context. */
1549 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1552 /* Wait for resume directive */
1553 while (!CPU_ISSET(cpu, &toresume_cpus))
1556 /* Re-apply microcode updates. */
1560 /* Finish removing the identity mapping of low memory for this AP. */
1564 if (cpu_ops.cpu_resume)
1565 cpu_ops.cpu_resume();
1571 /* Resume MCA and local APIC */
1576 /* Indicate that we are resumed */
1577 CPU_CLR_ATOMIC(cpu, &resuming_cpus);
1578 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1579 CPU_CLR_ATOMIC(cpu, &toresume_cpus);
1584 invlcache_handler(void)
1586 uint32_t generation;
1589 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
1590 #endif /* COUNT_IPIS */
1593 * Reading the generation here allows greater parallelism
1594 * since wbinvd is a serializing instruction. Without the
1595 * temporary, we'd wait for wbinvd to complete, then the read
1596 * would execute, then the dependent write, which must then
1597 * complete before return from interrupt.
1599 generation = smp_tlb_generation;
1601 PCPU_SET(smp_tlb_done, generation);
1605 * This is called once the rest of the system is up and running and we're
1606 * ready to let the AP's out of the pen.
1609 release_aps(void *dummy __unused)
1614 atomic_store_rel_int(&aps_ready, 1);
1615 while (smp_started == 0)
1618 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1622 * Setup interrupt counters for IPI handlers.
1625 mp_ipi_intrcnt(void *dummy)
1631 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1632 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1633 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1634 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1635 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1636 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1637 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
1638 intrcnt_add(buf, &ipi_invlcache_counts[i]);
1639 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1640 intrcnt_add(buf, &ipi_preempt_counts[i]);
1641 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1642 intrcnt_add(buf, &ipi_ast_counts[i]);
1643 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1644 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1645 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1646 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1649 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
1653 * Flush the TLB on other CPU's
1656 /* Variables needed for SMP tlb shootdown. */
1657 vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
1658 pmap_t smp_tlb_pmap;
1659 volatile uint32_t smp_tlb_generation;
1662 #define read_eflags() read_rflags()
1666 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
1667 vm_offset_t addr1, vm_offset_t addr2)
1669 cpuset_t other_cpus;
1670 volatile uint32_t *p_cpudone;
1671 uint32_t generation;
1674 /* It is not necessary to signal other CPUs while in the debugger. */
1675 if (kdb_active || KERNEL_PANICKED())
1679 * Check for other cpus. Return if none.
1681 if (CPU_ISFULLSET(&mask)) {
1685 CPU_CLR(PCPU_GET(cpuid), &mask);
1686 if (CPU_EMPTY(&mask))
1690 if (!(read_eflags() & PSL_I))
1691 panic("%s: interrupts disabled", __func__);
1692 mtx_lock_spin(&smp_ipi_mtx);
1693 smp_tlb_addr1 = addr1;
1694 smp_tlb_addr2 = addr2;
1695 smp_tlb_pmap = pmap;
1696 generation = ++smp_tlb_generation;
1697 if (CPU_ISFULLSET(&mask)) {
1698 ipi_all_but_self(vector);
1699 other_cpus = all_cpus;
1700 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1703 while ((cpu = CPU_FFS(&mask)) != 0) {
1705 CPU_CLR(cpu, &mask);
1706 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
1708 ipi_send_cpu(cpu, vector);
1711 while ((cpu = CPU_FFS(&other_cpus)) != 0) {
1713 CPU_CLR(cpu, &other_cpus);
1714 p_cpudone = &cpuid_to_pcpu[cpu]->pc_smp_tlb_done;
1715 while (*p_cpudone != generation)
1718 mtx_unlock_spin(&smp_ipi_mtx);
1722 smp_masked_invltlb(cpuset_t mask, pmap_t pmap)
1726 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0);
1727 #ifdef COUNT_XINVLTLB_HITS
1734 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr, pmap_t pmap)
1738 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, pmap, addr, 0);
1739 #ifdef COUNT_XINVLTLB_HITS
1746 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2,
1751 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, pmap,
1753 #ifdef COUNT_XINVLTLB_HITS
1755 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1761 smp_cache_flush(void)
1765 smp_targeted_tlb_shootdown(all_cpus, IPI_INVLCACHE, NULL,
1771 * Handlers for TLB related IPIs
1774 invltlb_handler(void)
1776 uint32_t generation;
1778 #ifdef COUNT_XINVLTLB_HITS
1779 xhits_gbl[PCPU_GET(cpuid)]++;
1780 #endif /* COUNT_XINVLTLB_HITS */
1782 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1783 #endif /* COUNT_IPIS */
1786 * Reading the generation here allows greater parallelism
1787 * since invalidating the TLB is a serializing operation.
1789 generation = smp_tlb_generation;
1790 if (smp_tlb_pmap == kernel_pmap)
1796 PCPU_SET(smp_tlb_done, generation);
1800 invlpg_handler(void)
1802 uint32_t generation;
1804 #ifdef COUNT_XINVLTLB_HITS
1805 xhits_pg[PCPU_GET(cpuid)]++;
1806 #endif /* COUNT_XINVLTLB_HITS */
1808 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1809 #endif /* COUNT_IPIS */
1811 generation = smp_tlb_generation; /* Overlap with serialization */
1813 if (smp_tlb_pmap == kernel_pmap)
1815 invlpg(smp_tlb_addr1);
1816 PCPU_SET(smp_tlb_done, generation);
1820 invlrng_handler(void)
1822 vm_offset_t addr, addr2;
1823 uint32_t generation;
1825 #ifdef COUNT_XINVLTLB_HITS
1826 xhits_rng[PCPU_GET(cpuid)]++;
1827 #endif /* COUNT_XINVLTLB_HITS */
1829 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
1830 #endif /* COUNT_IPIS */
1832 addr = smp_tlb_addr1;
1833 addr2 = smp_tlb_addr2;
1834 generation = smp_tlb_generation; /* Overlap with serialization */
1836 if (smp_tlb_pmap == kernel_pmap)
1841 } while (addr < addr2);
1843 PCPU_SET(smp_tlb_done, generation);