2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
35 #include "opt_kstack_pages.h"
37 #include "opt_sched.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/cons.h> /* cngetc() */
44 #include <sys/cpuset.h>
49 #include <sys/kernel.h>
52 #include <sys/malloc.h>
53 #include <sys/memrange.h>
54 #include <sys/mutex.h>
57 #include <sys/sched.h>
59 #include <sys/sysctl.h>
62 #include <vm/vm_param.h>
64 #include <vm/vm_kern.h>
65 #include <vm/vm_extern.h>
67 #include <x86/apicreg.h>
68 #include <machine/clock.h>
69 #include <machine/cputypes.h>
71 #include <machine/md_var.h>
72 #include <machine/pcb.h>
73 #include <machine/psl.h>
74 #include <machine/smp.h>
75 #include <machine/specialreg.h>
76 #include <machine/cpu.h>
78 #define WARMBOOT_TARGET 0
79 #define WARMBOOT_OFF (KERNBASE + 0x0467)
80 #define WARMBOOT_SEG (KERNBASE + 0x0469)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 static MALLOC_DEFINE(M_CPUS, "cpus", "CPU items");
89 /* lock region used by kernel profiling */
92 int mp_naps; /* # of Applications processors */
93 int boot_cpu_id = -1; /* designated BSP */
95 /* AP uses this during bootstrap. Do not staticize. */
99 /* Free these after use */
100 void *bootstacks[MAXCPU];
103 struct pcb stoppcbs[MAXCPU];
104 struct susppcb **susppcbs;
107 /* Interrupt counts. */
108 static u_long *ipi_preempt_counts[MAXCPU];
109 static u_long *ipi_ast_counts[MAXCPU];
110 u_long *ipi_invltlb_counts[MAXCPU];
111 u_long *ipi_invlrng_counts[MAXCPU];
112 u_long *ipi_invlpg_counts[MAXCPU];
113 u_long *ipi_invlcache_counts[MAXCPU];
114 u_long *ipi_rendezvous_counts[MAXCPU];
115 static u_long *ipi_hardclock_counts[MAXCPU];
118 /* Default cpu_ops implementation. */
119 struct cpu_ops cpu_ops;
122 * Local data and functions.
125 static volatile cpuset_t ipi_stop_nmi_pending;
127 /* used to hold the AP's until we are ready to release them */
128 struct mtx ap_boot_mtx;
130 /* Set to 1 once we're ready to let the APs out of the pen. */
131 volatile int aps_ready = 0;
134 * Store data from cpu_add() until later in the boot when we actually setup
137 struct cpu_info *cpu_info;
139 int cpu_apic_ids[MAXCPU];
140 _Static_assert(MAXCPU <= MAX_APIC_ID,
141 "MAXCPU cannot be larger that MAX_APIC_ID");
142 _Static_assert(xAPIC_MAX_APIC_ID <= MAX_APIC_ID,
143 "xAPIC_MAX_APIC_ID cannot be larger that MAX_APIC_ID");
145 /* Holds pending bitmap based IPIs per CPU */
146 volatile u_int cpu_ipi_pending[MAXCPU];
148 static void release_aps(void *dummy);
149 static void cpustop_handler_post(u_int cpu);
151 static int hyperthreading_allowed = 1;
152 SYSCTL_INT(_machdep, OID_AUTO, hyperthreading_allowed, CTLFLAG_RDTUN,
153 &hyperthreading_allowed, 0, "Use Intel HTT logical CPUs");
155 static struct topo_node topo_root;
157 static int pkg_id_shift;
158 static int node_id_shift;
159 static int core_id_shift;
160 static int disabled_cpus;
165 } static caches[MAX_CACHE_LEVELS];
168 mem_range_AP_init(void)
171 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
172 mem_range_softc.mr_op->initAP(&mem_range_softc);
176 * Round up to the next power of two, if necessary, and then
178 * Returns -1 if argument is zero.
184 return (fls(x << (1 - powerof2(x))) - 1);
188 * Add a cache level to the cache topology description.
191 add_deterministic_cache(int type, int level, int share_count)
197 printf("unexpected cache type %d\n", type);
200 if (type == 2) /* ignore instruction cache */
202 if (level == 0 || level > MAX_CACHE_LEVELS) {
203 printf("unexpected cache level %d\n", type);
207 if (caches[level - 1].present) {
208 printf("WARNING: multiple entries for L%u data cache\n", level);
209 printf("%u => %u\n", caches[level - 1].id_shift,
210 mask_width(share_count));
212 caches[level - 1].id_shift = mask_width(share_count);
213 caches[level - 1].present = 1;
215 if (caches[level - 1].id_shift > pkg_id_shift) {
216 printf("WARNING: L%u data cache covers more "
217 "APIC IDs than a package (%u > %u)\n", level,
218 caches[level - 1].id_shift, pkg_id_shift);
219 caches[level - 1].id_shift = pkg_id_shift;
221 if (caches[level - 1].id_shift < core_id_shift) {
222 printf("WARNING: L%u data cache covers fewer "
223 "APIC IDs than a core (%u < %u)\n", level,
224 caches[level - 1].id_shift, core_id_shift);
225 caches[level - 1].id_shift = core_id_shift;
232 * Determine topology of processing units and caches for AMD CPUs.
234 * - AMD CPUID Specification (Publication # 25481)
235 * - BKDG for AMD NPT Family 0Fh Processors (Publication # 32559)
236 * - BKDG For AMD Family 10h Processors (Publication # 31116)
237 * - BKDG For AMD Family 15h Models 00h-0Fh Processors (Publication # 42301)
238 * - BKDG For AMD Family 16h Models 00h-0Fh Processors (Publication # 48751)
246 int nodes_per_socket;
251 /* No multi-core capability. */
252 if ((amd_feature2 & AMDID2_CMP) == 0)
255 /* For families 10h and newer. */
256 pkg_id_shift = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
257 AMDID_COREID_SIZE_SHIFT;
259 /* For 0Fh family. */
260 if (pkg_id_shift == 0)
262 mask_width((cpu_procinfo2 & AMDID_CMP_CORES) + 1);
265 * Families prior to 16h define the following value as
266 * cores per compute unit and we don't really care about the AMD
267 * compute units at the moment. Perhaps we should treat them as
268 * cores and cores within the compute units as hardware threads,
269 * but that's up for debate.
270 * Later families define the value as threads per compute unit,
271 * so we are following AMD's nomenclature here.
273 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0 &&
274 CPUID_TO_FAMILY(cpu_id) >= 0x16) {
275 cpuid_count(0x8000001e, 0, p);
276 share_count = ((p[1] >> 8) & 0xff) + 1;
277 core_id_shift = mask_width(share_count);
280 * For Zen (17h), gather Nodes per Processor. Each node is a
281 * Zeppelin die; TR and EPYC CPUs will have multiple dies per
282 * package. Communication latency between dies is higher than
285 nodes_per_socket = ((p[2] >> 8) & 0x7) + 1;
286 node_id_shift = pkg_id_shift - mask_width(nodes_per_socket);
289 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0) {
291 cpuid_count(0x8000001d, i, p);
293 level = (p[0] >> 5) & 0x7;
294 share_count = 1 + ((p[0] >> 14) & 0xfff);
296 if (!add_deterministic_cache(type, level, share_count))
300 if (cpu_exthigh >= 0x80000005) {
301 cpuid_count(0x80000005, 0, p);
302 if (((p[2] >> 24) & 0xff) != 0) {
303 caches[0].id_shift = 0;
304 caches[0].present = 1;
307 if (cpu_exthigh >= 0x80000006) {
308 cpuid_count(0x80000006, 0, p);
309 if (((p[2] >> 16) & 0xffff) != 0) {
310 caches[1].id_shift = 0;
311 caches[1].present = 1;
313 if (((p[3] >> 18) & 0x3fff) != 0) {
314 nodes_per_socket = 1;
315 if ((amd_feature2 & AMDID2_NODE_ID) != 0) {
317 * Handle multi-node processors that
318 * have multiple chips, each with its
319 * own L3 cache, on the same die.
321 v = rdmsr(0xc001100c);
322 nodes_per_socket = 1 + ((v >> 3) & 0x7);
325 pkg_id_shift - mask_width(nodes_per_socket);
326 caches[2].present = 1;
333 * Determine topology of processing units for Intel CPUs
334 * using CPUID Leaf 1 and Leaf 4, if supported.
336 * - Intel 64 Architecture Processor Topology Enumeration
337 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
338 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
339 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
342 topo_probe_intel_0x4(void)
348 /* Both zero and one here mean one logical processor per package. */
349 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
350 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
351 if (max_logical <= 1)
354 if (cpu_high >= 0x4) {
355 cpuid_count(0x04, 0, p);
356 max_cores = ((p[0] >> 26) & 0x3f) + 1;
360 core_id_shift = mask_width(max_logical/max_cores);
361 KASSERT(core_id_shift >= 0,
362 ("intel topo: max_cores > max_logical\n"));
363 pkg_id_shift = core_id_shift + mask_width(max_cores);
367 * Determine topology of processing units for Intel CPUs
368 * using CPUID Leaf 11, if supported.
370 * - Intel 64 Architecture Processor Topology Enumeration
371 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
372 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
373 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
376 topo_probe_intel_0xb(void)
383 /* Fall back if CPU leaf 11 doesn't really exist. */
384 cpuid_count(0x0b, 0, p);
386 topo_probe_intel_0x4();
390 /* We only support three levels for now. */
392 cpuid_count(0x0b, i, p);
395 type = (p[2] >> 8) & 0xff;
400 /* TODO: check for duplicate (re-)assignment */
401 if (type == CPUID_TYPE_SMT)
402 core_id_shift = bits;
403 else if (type == CPUID_TYPE_CORE)
406 printf("unknown CPU level type %d\n", type);
409 if (pkg_id_shift < core_id_shift) {
410 printf("WARNING: core covers more APIC IDs than a package\n");
411 core_id_shift = pkg_id_shift;
416 * Determine topology of caches for Intel CPUs.
418 * - Intel 64 Architecture Processor Topology Enumeration
419 * - Intel 64 and IA-32 Architectures Software Developer’s Manual
420 * Volume 2A: Instruction Set Reference, A-M,
424 topo_probe_intel_caches(void)
432 if (cpu_high < 0x4) {
434 * Available cache level and sizes can be determined
435 * via CPUID leaf 2, but that requires a huge table of hardcoded
436 * values, so for now just assume L1 and L2 caches potentially
437 * shared only by HTT processing units, if HTT is present.
439 caches[0].id_shift = pkg_id_shift;
440 caches[0].present = 1;
441 caches[1].id_shift = pkg_id_shift;
442 caches[1].present = 1;
447 cpuid_count(0x4, i, p);
449 level = (p[0] >> 5) & 0x7;
450 share_count = 1 + ((p[0] >> 14) & 0xfff);
452 if (!add_deterministic_cache(type, level, share_count))
458 * Determine topology of processing units and caches for Intel CPUs.
460 * - Intel 64 Architecture Processor Topology Enumeration
463 topo_probe_intel(void)
467 * Note that 0x1 <= cpu_high < 4 case should be
468 * compatible with topo_probe_intel_0x4() logic when
469 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
470 * or it should trigger the fallback otherwise.
473 topo_probe_intel_0xb();
474 else if (cpu_high >= 0x1)
475 topo_probe_intel_0x4();
477 topo_probe_intel_caches();
481 * Topology information is queried only on BSP, on which this
482 * code runs and for which it can query CPUID information.
483 * Then topology is extrapolated on all packages using an
484 * assumption that APIC ID to hardware component ID mapping is
486 * That doesn't necesserily imply that the topology is uniform.
491 static int cpu_topo_probed = 0;
492 struct x86_topo_layer {
496 } topo_layers[MAX_CACHE_LEVELS + 4];
497 struct topo_node *parent;
498 struct topo_node *node;
507 CPU_ZERO(&logical_cpus_mask);
511 else if (cpu_vendor_id == CPU_VENDOR_AMD)
513 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
516 KASSERT(pkg_id_shift >= core_id_shift,
517 ("bug in APIC topology discovery"));
520 bzero(topo_layers, sizeof(topo_layers));
522 topo_layers[nlayers].type = TOPO_TYPE_PKG;
523 topo_layers[nlayers].id_shift = pkg_id_shift;
525 printf("Package ID shift: %u\n", topo_layers[nlayers].id_shift);
528 if (pkg_id_shift > node_id_shift && node_id_shift != 0) {
529 topo_layers[nlayers].type = TOPO_TYPE_GROUP;
530 topo_layers[nlayers].id_shift = node_id_shift;
532 printf("Node ID shift: %u\n",
533 topo_layers[nlayers].id_shift);
538 * Consider all caches to be within a package/chip
539 * and "in front" of all sub-components like
540 * cores and hardware threads.
542 for (i = MAX_CACHE_LEVELS - 1; i >= 0; --i) {
543 if (caches[i].present) {
544 if (node_id_shift != 0)
545 KASSERT(caches[i].id_shift <= node_id_shift,
546 ("bug in APIC topology discovery"));
547 KASSERT(caches[i].id_shift <= pkg_id_shift,
548 ("bug in APIC topology discovery"));
549 KASSERT(caches[i].id_shift >= core_id_shift,
550 ("bug in APIC topology discovery"));
552 topo_layers[nlayers].type = TOPO_TYPE_CACHE;
553 topo_layers[nlayers].subtype = i + 1;
554 topo_layers[nlayers].id_shift = caches[i].id_shift;
556 printf("L%u cache ID shift: %u\n",
557 topo_layers[nlayers].subtype,
558 topo_layers[nlayers].id_shift);
563 if (pkg_id_shift > core_id_shift) {
564 topo_layers[nlayers].type = TOPO_TYPE_CORE;
565 topo_layers[nlayers].id_shift = core_id_shift;
567 printf("Core ID shift: %u\n",
568 topo_layers[nlayers].id_shift);
572 topo_layers[nlayers].type = TOPO_TYPE_PU;
573 topo_layers[nlayers].id_shift = 0;
576 topo_init_root(&topo_root);
577 for (i = 0; i <= max_apic_id; ++i) {
578 if (!cpu_info[i].cpu_present)
582 for (layer = 0; layer < nlayers; ++layer) {
583 node_id = i >> topo_layers[layer].id_shift;
584 parent = topo_add_node_by_hwid(parent, node_id,
585 topo_layers[layer].type,
586 topo_layers[layer].subtype);
591 for (layer = 0; layer < nlayers; ++layer) {
592 node_id = boot_cpu_id >> topo_layers[layer].id_shift;
593 node = topo_find_node_by_hwid(parent, node_id,
594 topo_layers[layer].type,
595 topo_layers[layer].subtype);
596 topo_promote_child(node);
604 * Assign logical CPU IDs to local APICs.
609 struct topo_node *node;
612 smt_mask = (1u << core_id_shift) - 1;
615 * Assign CPU IDs to local APIC IDs and disable any CPUs
616 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
619 TOPO_FOREACH(node, &topo_root) {
620 if (node->type != TOPO_TYPE_PU)
623 if ((node->hwid & smt_mask) != (boot_cpu_id & smt_mask))
624 cpu_info[node->hwid].cpu_hyperthread = 1;
626 if (resource_disabled("lapic", node->hwid)) {
627 if (node->hwid != boot_cpu_id)
628 cpu_info[node->hwid].cpu_disabled = 1;
630 printf("Cannot disable BSP, APIC ID = %d\n",
634 if (!hyperthreading_allowed &&
635 cpu_info[node->hwid].cpu_hyperthread)
636 cpu_info[node->hwid].cpu_disabled = 1;
638 if (mp_ncpus >= MAXCPU)
639 cpu_info[node->hwid].cpu_disabled = 1;
641 if (cpu_info[node->hwid].cpu_disabled) {
646 cpu_apic_ids[mp_ncpus] = node->hwid;
647 apic_cpuids[node->hwid] = mp_ncpus;
648 topo_set_pu_id(node, mp_ncpus);
652 KASSERT(mp_maxid >= mp_ncpus - 1,
653 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
658 * Print various information about the SMP system hardware and setup.
661 cpu_mp_announce(void)
663 struct topo_node *node;
664 const char *hyperthread;
665 struct topo_analysis topology;
667 printf("FreeBSD/SMP: ");
668 if (topo_analyze(&topo_root, 1, &topology)) {
669 printf("%d package(s)", topology.entities[TOPO_LEVEL_PKG]);
670 if (topology.entities[TOPO_LEVEL_GROUP] > 1)
671 printf(" x %d groups",
672 topology.entities[TOPO_LEVEL_GROUP]);
673 if (topology.entities[TOPO_LEVEL_CACHEGROUP] > 1)
674 printf(" x %d cache groups",
675 topology.entities[TOPO_LEVEL_CACHEGROUP]);
676 if (topology.entities[TOPO_LEVEL_CORE] > 0)
677 printf(" x %d core(s)",
678 topology.entities[TOPO_LEVEL_CORE]);
679 if (topology.entities[TOPO_LEVEL_THREAD] > 1)
680 printf(" x %d hardware threads",
681 topology.entities[TOPO_LEVEL_THREAD]);
683 printf("Non-uniform topology");
688 printf("FreeBSD/SMP Online: ");
689 if (topo_analyze(&topo_root, 0, &topology)) {
690 printf("%d package(s)",
691 topology.entities[TOPO_LEVEL_PKG]);
692 if (topology.entities[TOPO_LEVEL_GROUP] > 1)
693 printf(" x %d groups",
694 topology.entities[TOPO_LEVEL_GROUP]);
695 if (topology.entities[TOPO_LEVEL_CACHEGROUP] > 1)
696 printf(" x %d cache groups",
697 topology.entities[TOPO_LEVEL_CACHEGROUP]);
698 if (topology.entities[TOPO_LEVEL_CORE] > 0)
699 printf(" x %d core(s)",
700 topology.entities[TOPO_LEVEL_CORE]);
701 if (topology.entities[TOPO_LEVEL_THREAD] > 1)
702 printf(" x %d hardware threads",
703 topology.entities[TOPO_LEVEL_THREAD]);
705 printf("Non-uniform topology");
713 TOPO_FOREACH(node, &topo_root) {
714 switch (node->type) {
716 printf("Package HW ID = %u\n", node->hwid);
719 printf("\tCore HW ID = %u\n", node->hwid);
722 if (cpu_info[node->hwid].cpu_hyperthread)
727 if (node->subtype == 0)
728 printf("\t\tCPU (AP%s): APIC ID: %u"
729 "(disabled)\n", hyperthread, node->hwid);
730 else if (node->id == 0)
731 printf("\t\tCPU0 (BSP): APIC ID: %u\n",
734 printf("\t\tCPU%u (AP%s): APIC ID: %u\n",
735 node->id, hyperthread, node->hwid);
745 * Add a scheduling group, a group of logical processors sharing
746 * a particular cache (and, thus having an affinity), to the scheduling
748 * This function recursively works on lower level caches.
751 x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
753 struct topo_node *node;
758 KASSERT(root->type == TOPO_TYPE_SYSTEM || root->type == TOPO_TYPE_CACHE ||
759 root->type == TOPO_TYPE_GROUP,
760 ("x86topo_add_sched_group: bad type: %u", root->type));
761 CPU_COPY(&root->cpuset, &cg_root->cg_mask);
762 cg_root->cg_count = root->cpu_count;
763 if (root->type == TOPO_TYPE_SYSTEM)
764 cg_root->cg_level = CG_SHARE_NONE;
766 cg_root->cg_level = root->subtype;
769 * Check how many core nodes we have under the given root node.
770 * If we have multiple logical processors, but not multiple
771 * cores, then those processors must be hardware threads.
775 while (node != NULL) {
776 if (node->type != TOPO_TYPE_CORE) {
777 node = topo_next_node(root, node);
782 node = topo_next_nonchild_node(root, node);
785 if (cg_root->cg_level != CG_SHARE_NONE &&
786 root->cpu_count > 1 && ncores < 2)
787 cg_root->cg_flags = CG_FLAG_SMT;
790 * Find out how many cache nodes we have under the given root node.
791 * We ignore cache nodes that cover all the same processors as the
792 * root node. Also, we do not descend below found cache nodes.
793 * That is, we count top-level "non-redundant" caches under the root
798 while (node != NULL) {
799 if ((node->type != TOPO_TYPE_GROUP &&
800 node->type != TOPO_TYPE_CACHE) ||
801 (root->type != TOPO_TYPE_SYSTEM &&
802 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
803 node = topo_next_node(root, node);
807 node = topo_next_nonchild_node(root, node);
810 cg_root->cg_child = smp_topo_alloc(nchildren);
811 cg_root->cg_children = nchildren;
814 * Now find again the same cache nodes as above and recursively
815 * build scheduling topologies for them.
819 while (node != NULL) {
820 if ((node->type != TOPO_TYPE_GROUP &&
821 node->type != TOPO_TYPE_CACHE) ||
822 (root->type != TOPO_TYPE_SYSTEM &&
823 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
824 node = topo_next_node(root, node);
827 cg_root->cg_child[i].cg_parent = cg_root;
828 x86topo_add_sched_group(node, &cg_root->cg_child[i]);
830 node = topo_next_nonchild_node(root, node);
835 * Build the MI scheduling topology from the discovered hardware topology.
840 struct cpu_group *cg_root;
843 return (smp_topo_none());
845 cg_root = smp_topo_alloc(1);
846 x86topo_add_sched_group(&topo_root, cg_root);
851 cpu_alloc(void *dummy __unused)
854 * Dynamically allocate the arrays that depend on the
857 cpu_info = malloc(sizeof(*cpu_info) * (max_apic_id + 1), M_CPUS,
859 apic_cpuids = malloc(sizeof(*apic_cpuids) * (max_apic_id + 1), M_CPUS,
862 SYSINIT(cpu_alloc, SI_SUB_CPU, SI_ORDER_FIRST, cpu_alloc, NULL);
865 * Add a logical CPU to the topology.
868 cpu_add(u_int apic_id, char boot_cpu)
871 if (apic_id > max_apic_id) {
872 panic("SMP: APIC ID %d too high", apic_id);
875 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %u added twice",
877 cpu_info[apic_id].cpu_present = 1;
879 KASSERT(boot_cpu_id == -1,
880 ("CPU %u claims to be BSP, but CPU %u already is", apic_id,
882 boot_cpu_id = apic_id;
883 cpu_info[apic_id].cpu_bsp = 1;
886 printf("SMP: Added CPU %u (%s)\n", apic_id, boot_cpu ? "BSP" :
891 cpu_mp_setmaxid(void)
895 * mp_ncpus and mp_maxid should be already set by calls to cpu_add().
896 * If there were no calls to cpu_add() assume this is a UP system.
907 * Always record BSP in CPU map so that the mbuf init code works
910 CPU_SETOF(0, &all_cpus);
911 return (mp_ncpus > 1);
915 * AP CPU's call this to initialize themselves.
918 init_secondary_tail(void)
923 * On real hardware, switch to x2apic mode if possible. Do it
924 * after aps_ready was signalled, to avoid manipulating the
925 * mode while BSP might still want to send some IPI to us
926 * (second startup IPI is ignored on modern hardware etc).
930 /* Initialize the PAT MSR. */
933 /* set up CPU registers and state */
939 /* set up FPU state on the AP */
946 if (cpu_ops.cpu_init)
949 /* A quick check from sanity claus */
950 cpuid = PCPU_GET(cpuid);
951 if (PCPU_GET(apic_id) != lapic_id()) {
952 printf("SMP: cpuid = %d\n", cpuid);
953 printf("SMP: actual apic_id = %d\n", lapic_id());
954 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
955 panic("cpuid mismatch! boom!!");
958 /* Initialize curthread. */
959 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
960 PCPU_SET(curthread, PCPU_GET(idlethread));
964 mtx_lock_spin(&ap_boot_mtx);
966 /* Init local apic for irq's */
969 /* Set memory range attributes for this CPU to match the BSP */
974 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
975 printf("SMP: AP CPU #%d Launched!\n", cpuid);
977 /* Determine if we are a logical CPU. */
978 if (cpu_info[PCPU_GET(apic_id)].cpu_hyperthread)
979 CPU_SET(cpuid, &logical_cpus_mask);
984 if (smp_cpus == mp_ncpus) {
985 /* enable IPI's, tlb shootdown, freezes etc */
986 atomic_store_rel_int(&smp_started, 1);
991 * Enable global pages TLB extension
992 * This also implicitly flushes the TLB
994 load_cr4(rcr4() | CR4_PGE);
995 if (pmap_pcid_enabled)
996 load_cr4(rcr4() | CR4_PCIDE);
1002 mtx_unlock_spin(&ap_boot_mtx);
1004 /* Wait until all the AP's are up. */
1005 while (atomic_load_acq_int(&smp_started) == 0)
1008 #ifndef EARLY_AP_STARTUP
1009 /* Start per-CPU event timers. */
1010 cpu_initclocks_ap();
1015 panic("scheduler returned us to %s", __func__);
1019 /*******************************************************************
1020 * local functions and data
1024 * We tell the I/O APIC code about all the CPUs we want to receive
1025 * interrupts. If we don't want certain CPUs to receive IRQs we
1026 * can simply not tell the I/O APIC code about them in this function.
1027 * We also do not tell it about the BSP since it tells itself about
1028 * the BSP internally to work with UP kernels and on UP machines.
1031 set_interrupt_apic_ids(void)
1035 for (i = 0; i < MAXCPU; i++) {
1036 apic_id = cpu_apic_ids[i];
1039 if (cpu_info[apic_id].cpu_bsp)
1041 if (cpu_info[apic_id].cpu_disabled)
1044 /* Don't let hyperthreads service interrupts. */
1045 if (cpu_info[apic_id].cpu_hyperthread)
1053 #ifdef COUNT_XINVLTLB_HITS
1054 u_int xhits_gbl[MAXCPU];
1055 u_int xhits_pg[MAXCPU];
1056 u_int xhits_rng[MAXCPU];
1057 static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1058 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1059 sizeof(xhits_gbl), "IU", "");
1060 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1061 sizeof(xhits_pg), "IU", "");
1062 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1063 sizeof(xhits_rng), "IU", "");
1068 u_int ipi_range_size;
1069 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1070 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1071 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1072 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1074 #endif /* COUNT_XINVLTLB_HITS */
1077 * Init and startup IPI.
1080 ipi_startup(int apic_id, int vector)
1084 * This attempts to follow the algorithm described in the
1085 * Intel Multiprocessor Specification v1.4 in section B.4.
1086 * For each IPI, we allow the local APIC ~20us to deliver the
1087 * IPI. If that times out, we panic.
1091 * first we do an INIT IPI: this INIT IPI might be run, resetting
1092 * and running the target CPU. OR this INIT IPI might be latched (P5
1093 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1096 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1097 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1098 lapic_ipi_wait(100);
1100 /* Explicitly deassert the INIT IPI. */
1101 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1102 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT,
1105 DELAY(10000); /* wait ~10mS */
1108 * next we do a STARTUP IPI: the previous INIT IPI might still be
1109 * latched, (P5 bug) this 1st STARTUP would then terminate
1110 * immediately, and the previously started INIT IPI would continue. OR
1111 * the previous INIT IPI has already run. and this STARTUP IPI will
1112 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1115 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1116 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1118 if (!lapic_ipi_wait(100))
1119 panic("Failed to deliver first STARTUP IPI to APIC %d",
1121 DELAY(200); /* wait ~200uS */
1124 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1125 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1126 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1127 * recognized after hardware RESET or INIT IPI.
1129 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1130 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1132 if (!lapic_ipi_wait(100))
1133 panic("Failed to deliver second STARTUP IPI to APIC %d",
1136 DELAY(200); /* wait ~200uS */
1140 * Send an IPI to specified CPU handling the bitmap logic.
1143 ipi_send_cpu(int cpu, u_int ipi)
1145 u_int bitmap, old_pending, new_pending;
1147 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1149 if (IPI_IS_BITMAPED(ipi)) {
1151 ipi = IPI_BITMAP_VECTOR;
1153 old_pending = cpu_ipi_pending[cpu];
1154 new_pending = old_pending | bitmap;
1155 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1156 old_pending, new_pending));
1160 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1164 ipi_bitmap_handler(struct trapframe frame)
1166 struct trapframe *oldframe;
1168 int cpu = PCPU_GET(cpuid);
1173 td->td_intr_nesting_level++;
1174 oldframe = td->td_intr_frame;
1175 td->td_intr_frame = &frame;
1176 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1177 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1179 (*ipi_preempt_counts[cpu])++;
1183 if (ipi_bitmap & (1 << IPI_AST)) {
1185 (*ipi_ast_counts[cpu])++;
1187 /* Nothing to do for AST */
1189 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1191 (*ipi_hardclock_counts[cpu])++;
1195 td->td_intr_frame = oldframe;
1196 td->td_intr_nesting_level--;
1201 * send an IPI to a set of cpus.
1204 ipi_selected(cpuset_t cpus, u_int ipi)
1209 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1210 * of help in order to understand what is the source.
1211 * Set the mask of receiving CPUs for this purpose.
1213 if (ipi == IPI_STOP_HARD)
1214 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &cpus);
1216 while ((cpu = CPU_FFS(&cpus)) != 0) {
1218 CPU_CLR(cpu, &cpus);
1219 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1220 ipi_send_cpu(cpu, ipi);
1225 * send an IPI to a specific CPU.
1228 ipi_cpu(int cpu, u_int ipi)
1232 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1233 * of help in order to understand what is the source.
1234 * Set the mask of receiving CPUs for this purpose.
1236 if (ipi == IPI_STOP_HARD)
1237 CPU_SET_ATOMIC(cpu, &ipi_stop_nmi_pending);
1239 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1240 ipi_send_cpu(cpu, ipi);
1244 * send an IPI to all CPUs EXCEPT myself
1247 ipi_all_but_self(u_int ipi)
1249 cpuset_t other_cpus;
1251 other_cpus = all_cpus;
1252 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1253 if (IPI_IS_BITMAPED(ipi)) {
1254 ipi_selected(other_cpus, ipi);
1259 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1260 * of help in order to understand what is the source.
1261 * Set the mask of receiving CPUs for this purpose.
1263 if (ipi == IPI_STOP_HARD)
1264 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &other_cpus);
1266 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1267 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1271 ipi_nmi_handler(void)
1276 * As long as there is not a simple way to know about a NMI's
1277 * source, if the bitmask for the current CPU is present in
1278 * the global pending bitword an IPI_STOP_HARD has been issued
1279 * and should be handled.
1281 cpuid = PCPU_GET(cpuid);
1282 if (!CPU_ISSET(cpuid, &ipi_stop_nmi_pending))
1285 CPU_CLR_ATOMIC(cpuid, &ipi_stop_nmi_pending);
1294 nmi_call_kdb_smp(u_int type, struct trapframe *frame)
1299 cpu = PCPU_GET(cpuid);
1300 if (atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1)) {
1301 nmi_call_kdb(cpu, type, frame);
1304 savectx(&stoppcbs[cpu]);
1305 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1306 while (!atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1))
1310 atomic_store_rel_int(&nmi_kdb_lock, 0);
1312 cpustop_handler_post(cpu);
1317 * Handle an IPI_STOP by saving our current context and spinning until we
1321 cpustop_handler(void)
1325 cpu = PCPU_GET(cpuid);
1327 savectx(&stoppcbs[cpu]);
1329 /* Indicate that we are stopped */
1330 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1332 /* Wait for restart */
1333 while (!CPU_ISSET(cpu, &started_cpus))
1336 cpustop_handler_post(cpu);
1340 cpustop_handler_post(u_int cpu)
1343 CPU_CLR_ATOMIC(cpu, &started_cpus);
1344 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1347 * We don't broadcast TLB invalidations to other CPUs when they are
1348 * stopped. Hence, we clear the TLB before resuming.
1352 #if defined(__amd64__) && defined(DDB)
1353 amd64_db_resume_dbreg();
1356 if (cpu == 0 && cpustop_restartfunc != NULL) {
1357 cpustop_restartfunc();
1358 cpustop_restartfunc = NULL;
1363 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1367 cpususpend_handler(void)
1371 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED);
1373 cpu = PCPU_GET(cpuid);
1374 if (savectx(&susppcbs[cpu]->sp_pcb)) {
1376 fpususpend(susppcbs[cpu]->sp_fpususpend);
1378 npxsuspend(susppcbs[cpu]->sp_fpususpend);
1381 CPU_SET_ATOMIC(cpu, &suspended_cpus);
1384 fpuresume(susppcbs[cpu]->sp_fpususpend);
1386 npxresume(susppcbs[cpu]->sp_fpususpend);
1390 PCPU_SET(switchtime, 0);
1391 PCPU_SET(switchticks, ticks);
1393 /* Indicate that we are resumed */
1394 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1397 /* Wait for resume */
1398 while (!CPU_ISSET(cpu, &started_cpus))
1402 /* Finish removing the identity mapping of low memory for this AP. */
1406 if (cpu_ops.cpu_resume)
1407 cpu_ops.cpu_resume();
1413 /* Resume MCA and local APIC */
1418 /* Indicate that we are resumed */
1419 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1420 CPU_CLR_ATOMIC(cpu, &started_cpus);
1425 invlcache_handler(void)
1427 uint32_t generation;
1430 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
1431 #endif /* COUNT_IPIS */
1434 * Reading the generation here allows greater parallelism
1435 * since wbinvd is a serializing instruction. Without the
1436 * temporary, we'd wait for wbinvd to complete, then the read
1437 * would execute, then the dependent write, which must then
1438 * complete before return from interrupt.
1440 generation = smp_tlb_generation;
1442 PCPU_SET(smp_tlb_done, generation);
1446 * This is called once the rest of the system is up and running and we're
1447 * ready to let the AP's out of the pen.
1450 release_aps(void *dummy __unused)
1455 atomic_store_rel_int(&aps_ready, 1);
1456 while (smp_started == 0)
1459 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1463 * Setup interrupt counters for IPI handlers.
1466 mp_ipi_intrcnt(void *dummy)
1472 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1473 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1474 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1475 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1476 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1477 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1478 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
1479 intrcnt_add(buf, &ipi_invlcache_counts[i]);
1480 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1481 intrcnt_add(buf, &ipi_preempt_counts[i]);
1482 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1483 intrcnt_add(buf, &ipi_ast_counts[i]);
1484 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1485 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1486 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1487 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1490 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
1494 * Flush the TLB on other CPU's
1497 /* Variables needed for SMP tlb shootdown. */
1498 static vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
1499 pmap_t smp_tlb_pmap;
1500 volatile uint32_t smp_tlb_generation;
1503 #define read_eflags() read_rflags()
1507 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
1508 vm_offset_t addr1, vm_offset_t addr2)
1510 cpuset_t other_cpus;
1511 volatile uint32_t *p_cpudone;
1512 uint32_t generation;
1515 /* It is not necessary to signal other CPUs while in the debugger. */
1516 if (kdb_active || panicstr != NULL)
1520 * Check for other cpus. Return if none.
1522 if (CPU_ISFULLSET(&mask)) {
1526 CPU_CLR(PCPU_GET(cpuid), &mask);
1527 if (CPU_EMPTY(&mask))
1531 if (!(read_eflags() & PSL_I))
1532 panic("%s: interrupts disabled", __func__);
1533 mtx_lock_spin(&smp_ipi_mtx);
1534 smp_tlb_addr1 = addr1;
1535 smp_tlb_addr2 = addr2;
1536 smp_tlb_pmap = pmap;
1537 generation = ++smp_tlb_generation;
1538 if (CPU_ISFULLSET(&mask)) {
1539 ipi_all_but_self(vector);
1540 other_cpus = all_cpus;
1541 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1544 while ((cpu = CPU_FFS(&mask)) != 0) {
1546 CPU_CLR(cpu, &mask);
1547 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
1549 ipi_send_cpu(cpu, vector);
1552 while ((cpu = CPU_FFS(&other_cpus)) != 0) {
1554 CPU_CLR(cpu, &other_cpus);
1555 p_cpudone = &cpuid_to_pcpu[cpu]->pc_smp_tlb_done;
1556 while (*p_cpudone != generation)
1559 mtx_unlock_spin(&smp_ipi_mtx);
1563 smp_masked_invltlb(cpuset_t mask, pmap_t pmap)
1567 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0);
1568 #ifdef COUNT_XINVLTLB_HITS
1575 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
1579 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, NULL, addr, 0);
1580 #ifdef COUNT_XINVLTLB_HITS
1587 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
1591 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, NULL,
1593 #ifdef COUNT_XINVLTLB_HITS
1595 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1601 smp_cache_flush(void)
1605 smp_targeted_tlb_shootdown(all_cpus, IPI_INVLCACHE, NULL,
1611 * Handlers for TLB related IPIs
1614 invltlb_handler(void)
1616 uint32_t generation;
1618 #ifdef COUNT_XINVLTLB_HITS
1619 xhits_gbl[PCPU_GET(cpuid)]++;
1620 #endif /* COUNT_XINVLTLB_HITS */
1622 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1623 #endif /* COUNT_IPIS */
1626 * Reading the generation here allows greater parallelism
1627 * since invalidating the TLB is a serializing operation.
1629 generation = smp_tlb_generation;
1630 if (smp_tlb_pmap == kernel_pmap)
1634 PCPU_SET(smp_tlb_done, generation);
1638 invlpg_handler(void)
1640 uint32_t generation;
1642 #ifdef COUNT_XINVLTLB_HITS
1643 xhits_pg[PCPU_GET(cpuid)]++;
1644 #endif /* COUNT_XINVLTLB_HITS */
1646 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1647 #endif /* COUNT_IPIS */
1649 generation = smp_tlb_generation; /* Overlap with serialization */
1650 invlpg(smp_tlb_addr1);
1651 PCPU_SET(smp_tlb_done, generation);
1655 invlrng_handler(void)
1657 vm_offset_t addr, addr2;
1658 uint32_t generation;
1660 #ifdef COUNT_XINVLTLB_HITS
1661 xhits_rng[PCPU_GET(cpuid)]++;
1662 #endif /* COUNT_XINVLTLB_HITS */
1664 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
1665 #endif /* COUNT_IPIS */
1667 addr = smp_tlb_addr1;
1668 addr2 = smp_tlb_addr2;
1669 generation = smp_tlb_generation; /* Overlap with serialization */
1673 } while (addr < addr2);
1675 PCPU_SET(smp_tlb_done, generation);