2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
35 #include "opt_kstack_pages.h"
37 #include "opt_sched.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/cons.h> /* cngetc() */
44 #include <sys/cpuset.h>
49 #include <sys/kernel.h>
52 #include <sys/malloc.h>
53 #include <sys/memrange.h>
54 #include <sys/mutex.h>
57 #include <sys/sched.h>
59 #include <sys/sysctl.h>
62 #include <vm/vm_param.h>
64 #include <vm/vm_kern.h>
65 #include <vm/vm_extern.h>
67 #include <x86/apicreg.h>
68 #include <machine/clock.h>
69 #include <machine/cputypes.h>
71 #include <machine/md_var.h>
72 #include <machine/pcb.h>
73 #include <machine/psl.h>
74 #include <machine/smp.h>
75 #include <machine/specialreg.h>
76 #include <machine/cpu.h>
78 #define WARMBOOT_TARGET 0
79 #define WARMBOOT_OFF (KERNBASE + 0x0467)
80 #define WARMBOOT_SEG (KERNBASE + 0x0469)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 static MALLOC_DEFINE(M_CPUS, "cpus", "CPU items");
89 /* lock region used by kernel profiling */
92 int mp_naps; /* # of Applications processors */
93 int boot_cpu_id = -1; /* designated BSP */
95 /* AP uses this during bootstrap. Do not staticize. */
99 /* Free these after use */
100 void *bootstacks[MAXCPU];
103 struct pcb stoppcbs[MAXCPU];
104 struct susppcb **susppcbs;
107 /* Interrupt counts. */
108 static u_long *ipi_preempt_counts[MAXCPU];
109 static u_long *ipi_ast_counts[MAXCPU];
110 u_long *ipi_invltlb_counts[MAXCPU];
111 u_long *ipi_invlrng_counts[MAXCPU];
112 u_long *ipi_invlpg_counts[MAXCPU];
113 u_long *ipi_invlcache_counts[MAXCPU];
114 u_long *ipi_rendezvous_counts[MAXCPU];
115 static u_long *ipi_hardclock_counts[MAXCPU];
118 /* Default cpu_ops implementation. */
119 struct cpu_ops cpu_ops;
122 * Local data and functions.
125 static volatile cpuset_t ipi_stop_nmi_pending;
127 volatile cpuset_t resuming_cpus;
128 volatile cpuset_t toresume_cpus;
130 /* used to hold the AP's until we are ready to release them */
131 struct mtx ap_boot_mtx;
133 /* Set to 1 once we're ready to let the APs out of the pen. */
134 volatile int aps_ready = 0;
137 * Store data from cpu_add() until later in the boot when we actually setup
140 struct cpu_info *cpu_info;
142 int cpu_apic_ids[MAXCPU];
143 _Static_assert(MAXCPU <= MAX_APIC_ID,
144 "MAXCPU cannot be larger that MAX_APIC_ID");
145 _Static_assert(xAPIC_MAX_APIC_ID <= MAX_APIC_ID,
146 "xAPIC_MAX_APIC_ID cannot be larger that MAX_APIC_ID");
148 /* Holds pending bitmap based IPIs per CPU */
149 volatile u_int cpu_ipi_pending[MAXCPU];
151 static void release_aps(void *dummy);
152 static void cpustop_handler_post(u_int cpu);
154 static int hyperthreading_allowed = 1;
155 SYSCTL_INT(_machdep, OID_AUTO, hyperthreading_allowed, CTLFLAG_RDTUN,
156 &hyperthreading_allowed, 0, "Use Intel HTT logical CPUs");
158 static struct topo_node topo_root;
160 static int pkg_id_shift;
161 static int node_id_shift;
162 static int core_id_shift;
163 static int disabled_cpus;
168 } static caches[MAX_CACHE_LEVELS];
171 mem_range_AP_init(void)
174 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
175 mem_range_softc.mr_op->initAP(&mem_range_softc);
179 * Round up to the next power of two, if necessary, and then
181 * Returns -1 if argument is zero.
187 return (fls(x << (1 - powerof2(x))) - 1);
191 * Add a cache level to the cache topology description.
194 add_deterministic_cache(int type, int level, int share_count)
200 printf("unexpected cache type %d\n", type);
203 if (type == 2) /* ignore instruction cache */
205 if (level == 0 || level > MAX_CACHE_LEVELS) {
206 printf("unexpected cache level %d\n", type);
210 if (caches[level - 1].present) {
211 printf("WARNING: multiple entries for L%u data cache\n", level);
212 printf("%u => %u\n", caches[level - 1].id_shift,
213 mask_width(share_count));
215 caches[level - 1].id_shift = mask_width(share_count);
216 caches[level - 1].present = 1;
218 if (caches[level - 1].id_shift > pkg_id_shift) {
219 printf("WARNING: L%u data cache covers more "
220 "APIC IDs than a package (%u > %u)\n", level,
221 caches[level - 1].id_shift, pkg_id_shift);
222 caches[level - 1].id_shift = pkg_id_shift;
224 if (caches[level - 1].id_shift < core_id_shift) {
225 printf("WARNING: L%u data cache covers fewer "
226 "APIC IDs than a core (%u < %u)\n", level,
227 caches[level - 1].id_shift, core_id_shift);
228 caches[level - 1].id_shift = core_id_shift;
235 * Determine topology of processing units and caches for AMD CPUs.
237 * - AMD CPUID Specification (Publication # 25481)
238 * - BKDG for AMD NPT Family 0Fh Processors (Publication # 32559)
239 * - BKDG For AMD Family 10h Processors (Publication # 31116)
240 * - BKDG For AMD Family 15h Models 00h-0Fh Processors (Publication # 42301)
241 * - BKDG For AMD Family 16h Models 00h-0Fh Processors (Publication # 48751)
249 int nodes_per_socket;
254 /* No multi-core capability. */
255 if ((amd_feature2 & AMDID2_CMP) == 0)
258 /* For families 10h and newer. */
259 pkg_id_shift = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
260 AMDID_COREID_SIZE_SHIFT;
262 /* For 0Fh family. */
263 if (pkg_id_shift == 0)
265 mask_width((cpu_procinfo2 & AMDID_CMP_CORES) + 1);
268 * Families prior to 16h define the following value as
269 * cores per compute unit and we don't really care about the AMD
270 * compute units at the moment. Perhaps we should treat them as
271 * cores and cores within the compute units as hardware threads,
272 * but that's up for debate.
273 * Later families define the value as threads per compute unit,
274 * so we are following AMD's nomenclature here.
276 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0 &&
277 CPUID_TO_FAMILY(cpu_id) >= 0x16) {
278 cpuid_count(0x8000001e, 0, p);
279 share_count = ((p[1] >> 8) & 0xff) + 1;
280 core_id_shift = mask_width(share_count);
283 * For Zen (17h), gather Nodes per Processor. Each node is a
284 * Zeppelin die; TR and EPYC CPUs will have multiple dies per
285 * package. Communication latency between dies is higher than
288 nodes_per_socket = ((p[2] >> 8) & 0x7) + 1;
289 node_id_shift = pkg_id_shift - mask_width(nodes_per_socket);
292 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0) {
294 cpuid_count(0x8000001d, i, p);
296 level = (p[0] >> 5) & 0x7;
297 share_count = 1 + ((p[0] >> 14) & 0xfff);
299 if (!add_deterministic_cache(type, level, share_count))
303 if (cpu_exthigh >= 0x80000005) {
304 cpuid_count(0x80000005, 0, p);
305 if (((p[2] >> 24) & 0xff) != 0) {
306 caches[0].id_shift = 0;
307 caches[0].present = 1;
310 if (cpu_exthigh >= 0x80000006) {
311 cpuid_count(0x80000006, 0, p);
312 if (((p[2] >> 16) & 0xffff) != 0) {
313 caches[1].id_shift = 0;
314 caches[1].present = 1;
316 if (((p[3] >> 18) & 0x3fff) != 0) {
317 nodes_per_socket = 1;
318 if ((amd_feature2 & AMDID2_NODE_ID) != 0) {
320 * Handle multi-node processors that
321 * have multiple chips, each with its
322 * own L3 cache, on the same die.
324 v = rdmsr(0xc001100c);
325 nodes_per_socket = 1 + ((v >> 3) & 0x7);
328 pkg_id_shift - mask_width(nodes_per_socket);
329 caches[2].present = 1;
336 * Determine topology of processing units for Intel CPUs
337 * using CPUID Leaf 1 and Leaf 4, if supported.
339 * - Intel 64 Architecture Processor Topology Enumeration
340 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
341 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
342 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
345 topo_probe_intel_0x4(void)
351 /* Both zero and one here mean one logical processor per package. */
352 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
353 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
354 if (max_logical <= 1)
357 if (cpu_high >= 0x4) {
358 cpuid_count(0x04, 0, p);
359 max_cores = ((p[0] >> 26) & 0x3f) + 1;
363 core_id_shift = mask_width(max_logical/max_cores);
364 KASSERT(core_id_shift >= 0,
365 ("intel topo: max_cores > max_logical\n"));
366 pkg_id_shift = core_id_shift + mask_width(max_cores);
370 * Determine topology of processing units for Intel CPUs
371 * using CPUID Leaf 11, if supported.
373 * - Intel 64 Architecture Processor Topology Enumeration
374 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
375 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
376 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
379 topo_probe_intel_0xb(void)
386 /* Fall back if CPU leaf 11 doesn't really exist. */
387 cpuid_count(0x0b, 0, p);
389 topo_probe_intel_0x4();
393 /* We only support three levels for now. */
395 cpuid_count(0x0b, i, p);
398 type = (p[2] >> 8) & 0xff;
403 /* TODO: check for duplicate (re-)assignment */
404 if (type == CPUID_TYPE_SMT)
405 core_id_shift = bits;
406 else if (type == CPUID_TYPE_CORE)
409 printf("unknown CPU level type %d\n", type);
412 if (pkg_id_shift < core_id_shift) {
413 printf("WARNING: core covers more APIC IDs than a package\n");
414 core_id_shift = pkg_id_shift;
419 * Determine topology of caches for Intel CPUs.
421 * - Intel 64 Architecture Processor Topology Enumeration
422 * - Intel 64 and IA-32 Architectures Software Developer’s Manual
423 * Volume 2A: Instruction Set Reference, A-M,
427 topo_probe_intel_caches(void)
435 if (cpu_high < 0x4) {
437 * Available cache level and sizes can be determined
438 * via CPUID leaf 2, but that requires a huge table of hardcoded
439 * values, so for now just assume L1 and L2 caches potentially
440 * shared only by HTT processing units, if HTT is present.
442 caches[0].id_shift = pkg_id_shift;
443 caches[0].present = 1;
444 caches[1].id_shift = pkg_id_shift;
445 caches[1].present = 1;
450 cpuid_count(0x4, i, p);
452 level = (p[0] >> 5) & 0x7;
453 share_count = 1 + ((p[0] >> 14) & 0xfff);
455 if (!add_deterministic_cache(type, level, share_count))
461 * Determine topology of processing units and caches for Intel CPUs.
463 * - Intel 64 Architecture Processor Topology Enumeration
466 topo_probe_intel(void)
470 * Note that 0x1 <= cpu_high < 4 case should be
471 * compatible with topo_probe_intel_0x4() logic when
472 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
473 * or it should trigger the fallback otherwise.
476 topo_probe_intel_0xb();
477 else if (cpu_high >= 0x1)
478 topo_probe_intel_0x4();
480 topo_probe_intel_caches();
484 * Topology information is queried only on BSP, on which this
485 * code runs and for which it can query CPUID information.
486 * Then topology is extrapolated on all packages using an
487 * assumption that APIC ID to hardware component ID mapping is
489 * That doesn't necesserily imply that the topology is uniform.
494 static int cpu_topo_probed = 0;
495 struct x86_topo_layer {
499 } topo_layers[MAX_CACHE_LEVELS + 4];
500 struct topo_node *parent;
501 struct topo_node *node;
510 CPU_ZERO(&logical_cpus_mask);
514 else if (cpu_vendor_id == CPU_VENDOR_AMD)
516 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
519 KASSERT(pkg_id_shift >= core_id_shift,
520 ("bug in APIC topology discovery"));
523 bzero(topo_layers, sizeof(topo_layers));
525 topo_layers[nlayers].type = TOPO_TYPE_PKG;
526 topo_layers[nlayers].id_shift = pkg_id_shift;
528 printf("Package ID shift: %u\n", topo_layers[nlayers].id_shift);
531 if (pkg_id_shift > node_id_shift && node_id_shift != 0) {
532 topo_layers[nlayers].type = TOPO_TYPE_GROUP;
533 topo_layers[nlayers].id_shift = node_id_shift;
535 printf("Node ID shift: %u\n",
536 topo_layers[nlayers].id_shift);
541 * Consider all caches to be within a package/chip
542 * and "in front" of all sub-components like
543 * cores and hardware threads.
545 for (i = MAX_CACHE_LEVELS - 1; i >= 0; --i) {
546 if (caches[i].present) {
547 if (node_id_shift != 0)
548 KASSERT(caches[i].id_shift <= node_id_shift,
549 ("bug in APIC topology discovery"));
550 KASSERT(caches[i].id_shift <= pkg_id_shift,
551 ("bug in APIC topology discovery"));
552 KASSERT(caches[i].id_shift >= core_id_shift,
553 ("bug in APIC topology discovery"));
555 topo_layers[nlayers].type = TOPO_TYPE_CACHE;
556 topo_layers[nlayers].subtype = i + 1;
557 topo_layers[nlayers].id_shift = caches[i].id_shift;
559 printf("L%u cache ID shift: %u\n",
560 topo_layers[nlayers].subtype,
561 topo_layers[nlayers].id_shift);
566 if (pkg_id_shift > core_id_shift) {
567 topo_layers[nlayers].type = TOPO_TYPE_CORE;
568 topo_layers[nlayers].id_shift = core_id_shift;
570 printf("Core ID shift: %u\n",
571 topo_layers[nlayers].id_shift);
575 topo_layers[nlayers].type = TOPO_TYPE_PU;
576 topo_layers[nlayers].id_shift = 0;
579 topo_init_root(&topo_root);
580 for (i = 0; i <= max_apic_id; ++i) {
581 if (!cpu_info[i].cpu_present)
585 for (layer = 0; layer < nlayers; ++layer) {
586 node_id = i >> topo_layers[layer].id_shift;
587 parent = topo_add_node_by_hwid(parent, node_id,
588 topo_layers[layer].type,
589 topo_layers[layer].subtype);
594 for (layer = 0; layer < nlayers; ++layer) {
595 node_id = boot_cpu_id >> topo_layers[layer].id_shift;
596 node = topo_find_node_by_hwid(parent, node_id,
597 topo_layers[layer].type,
598 topo_layers[layer].subtype);
599 topo_promote_child(node);
607 * Assign logical CPU IDs to local APICs.
612 struct topo_node *node;
615 smt_mask = (1u << core_id_shift) - 1;
618 * Assign CPU IDs to local APIC IDs and disable any CPUs
619 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
622 TOPO_FOREACH(node, &topo_root) {
623 if (node->type != TOPO_TYPE_PU)
626 if ((node->hwid & smt_mask) != (boot_cpu_id & smt_mask))
627 cpu_info[node->hwid].cpu_hyperthread = 1;
629 if (resource_disabled("lapic", node->hwid)) {
630 if (node->hwid != boot_cpu_id)
631 cpu_info[node->hwid].cpu_disabled = 1;
633 printf("Cannot disable BSP, APIC ID = %d\n",
637 if (!hyperthreading_allowed &&
638 cpu_info[node->hwid].cpu_hyperthread)
639 cpu_info[node->hwid].cpu_disabled = 1;
641 if (mp_ncpus >= MAXCPU)
642 cpu_info[node->hwid].cpu_disabled = 1;
644 if (cpu_info[node->hwid].cpu_disabled) {
649 cpu_apic_ids[mp_ncpus] = node->hwid;
650 apic_cpuids[node->hwid] = mp_ncpus;
651 topo_set_pu_id(node, mp_ncpus);
655 KASSERT(mp_maxid >= mp_ncpus - 1,
656 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
661 * Print various information about the SMP system hardware and setup.
664 cpu_mp_announce(void)
666 struct topo_node *node;
667 const char *hyperthread;
668 struct topo_analysis topology;
670 printf("FreeBSD/SMP: ");
671 if (topo_analyze(&topo_root, 1, &topology)) {
672 printf("%d package(s)", topology.entities[TOPO_LEVEL_PKG]);
673 if (topology.entities[TOPO_LEVEL_GROUP] > 1)
674 printf(" x %d groups",
675 topology.entities[TOPO_LEVEL_GROUP]);
676 if (topology.entities[TOPO_LEVEL_CACHEGROUP] > 1)
677 printf(" x %d cache groups",
678 topology.entities[TOPO_LEVEL_CACHEGROUP]);
679 if (topology.entities[TOPO_LEVEL_CORE] > 0)
680 printf(" x %d core(s)",
681 topology.entities[TOPO_LEVEL_CORE]);
682 if (topology.entities[TOPO_LEVEL_THREAD] > 1)
683 printf(" x %d hardware threads",
684 topology.entities[TOPO_LEVEL_THREAD]);
686 printf("Non-uniform topology");
691 printf("FreeBSD/SMP Online: ");
692 if (topo_analyze(&topo_root, 0, &topology)) {
693 printf("%d package(s)",
694 topology.entities[TOPO_LEVEL_PKG]);
695 if (topology.entities[TOPO_LEVEL_GROUP] > 1)
696 printf(" x %d groups",
697 topology.entities[TOPO_LEVEL_GROUP]);
698 if (topology.entities[TOPO_LEVEL_CACHEGROUP] > 1)
699 printf(" x %d cache groups",
700 topology.entities[TOPO_LEVEL_CACHEGROUP]);
701 if (topology.entities[TOPO_LEVEL_CORE] > 0)
702 printf(" x %d core(s)",
703 topology.entities[TOPO_LEVEL_CORE]);
704 if (topology.entities[TOPO_LEVEL_THREAD] > 1)
705 printf(" x %d hardware threads",
706 topology.entities[TOPO_LEVEL_THREAD]);
708 printf("Non-uniform topology");
716 TOPO_FOREACH(node, &topo_root) {
717 switch (node->type) {
719 printf("Package HW ID = %u\n", node->hwid);
722 printf("\tCore HW ID = %u\n", node->hwid);
725 if (cpu_info[node->hwid].cpu_hyperthread)
730 if (node->subtype == 0)
731 printf("\t\tCPU (AP%s): APIC ID: %u"
732 "(disabled)\n", hyperthread, node->hwid);
733 else if (node->id == 0)
734 printf("\t\tCPU0 (BSP): APIC ID: %u\n",
737 printf("\t\tCPU%u (AP%s): APIC ID: %u\n",
738 node->id, hyperthread, node->hwid);
748 * Add a scheduling group, a group of logical processors sharing
749 * a particular cache (and, thus having an affinity), to the scheduling
751 * This function recursively works on lower level caches.
754 x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
756 struct topo_node *node;
761 KASSERT(root->type == TOPO_TYPE_SYSTEM || root->type == TOPO_TYPE_CACHE ||
762 root->type == TOPO_TYPE_GROUP,
763 ("x86topo_add_sched_group: bad type: %u", root->type));
764 CPU_COPY(&root->cpuset, &cg_root->cg_mask);
765 cg_root->cg_count = root->cpu_count;
766 if (root->type == TOPO_TYPE_SYSTEM)
767 cg_root->cg_level = CG_SHARE_NONE;
769 cg_root->cg_level = root->subtype;
772 * Check how many core nodes we have under the given root node.
773 * If we have multiple logical processors, but not multiple
774 * cores, then those processors must be hardware threads.
778 while (node != NULL) {
779 if (node->type != TOPO_TYPE_CORE) {
780 node = topo_next_node(root, node);
785 node = topo_next_nonchild_node(root, node);
788 if (cg_root->cg_level != CG_SHARE_NONE &&
789 root->cpu_count > 1 && ncores < 2)
790 cg_root->cg_flags = CG_FLAG_SMT;
793 * Find out how many cache nodes we have under the given root node.
794 * We ignore cache nodes that cover all the same processors as the
795 * root node. Also, we do not descend below found cache nodes.
796 * That is, we count top-level "non-redundant" caches under the root
801 while (node != NULL) {
802 if ((node->type != TOPO_TYPE_GROUP &&
803 node->type != TOPO_TYPE_CACHE) ||
804 (root->type != TOPO_TYPE_SYSTEM &&
805 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
806 node = topo_next_node(root, node);
810 node = topo_next_nonchild_node(root, node);
813 cg_root->cg_child = smp_topo_alloc(nchildren);
814 cg_root->cg_children = nchildren;
817 * Now find again the same cache nodes as above and recursively
818 * build scheduling topologies for them.
822 while (node != NULL) {
823 if ((node->type != TOPO_TYPE_GROUP &&
824 node->type != TOPO_TYPE_CACHE) ||
825 (root->type != TOPO_TYPE_SYSTEM &&
826 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
827 node = topo_next_node(root, node);
830 cg_root->cg_child[i].cg_parent = cg_root;
831 x86topo_add_sched_group(node, &cg_root->cg_child[i]);
833 node = topo_next_nonchild_node(root, node);
838 * Build the MI scheduling topology from the discovered hardware topology.
843 struct cpu_group *cg_root;
846 return (smp_topo_none());
848 cg_root = smp_topo_alloc(1);
849 x86topo_add_sched_group(&topo_root, cg_root);
854 cpu_alloc(void *dummy __unused)
857 * Dynamically allocate the arrays that depend on the
860 cpu_info = malloc(sizeof(*cpu_info) * (max_apic_id + 1), M_CPUS,
862 apic_cpuids = malloc(sizeof(*apic_cpuids) * (max_apic_id + 1), M_CPUS,
865 SYSINIT(cpu_alloc, SI_SUB_CPU, SI_ORDER_FIRST, cpu_alloc, NULL);
868 * Add a logical CPU to the topology.
871 cpu_add(u_int apic_id, char boot_cpu)
874 if (apic_id > max_apic_id) {
875 panic("SMP: APIC ID %d too high", apic_id);
878 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %u added twice",
880 cpu_info[apic_id].cpu_present = 1;
882 KASSERT(boot_cpu_id == -1,
883 ("CPU %u claims to be BSP, but CPU %u already is", apic_id,
885 boot_cpu_id = apic_id;
886 cpu_info[apic_id].cpu_bsp = 1;
889 printf("SMP: Added CPU %u (%s)\n", apic_id, boot_cpu ? "BSP" :
894 cpu_mp_setmaxid(void)
898 * mp_ncpus and mp_maxid should be already set by calls to cpu_add().
899 * If there were no calls to cpu_add() assume this is a UP system.
910 * Always record BSP in CPU map so that the mbuf init code works
913 CPU_SETOF(0, &all_cpus);
914 return (mp_ncpus > 1);
918 * AP CPU's call this to initialize themselves.
921 init_secondary_tail(void)
926 * On real hardware, switch to x2apic mode if possible. Do it
927 * after aps_ready was signalled, to avoid manipulating the
928 * mode while BSP might still want to send some IPI to us
929 * (second startup IPI is ignored on modern hardware etc).
933 /* Initialize the PAT MSR. */
936 /* set up CPU registers and state */
942 /* set up FPU state on the AP */
949 if (cpu_ops.cpu_init)
952 /* A quick check from sanity claus */
953 cpuid = PCPU_GET(cpuid);
954 if (PCPU_GET(apic_id) != lapic_id()) {
955 printf("SMP: cpuid = %d\n", cpuid);
956 printf("SMP: actual apic_id = %d\n", lapic_id());
957 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
958 panic("cpuid mismatch! boom!!");
961 /* Initialize curthread. */
962 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
963 PCPU_SET(curthread, PCPU_GET(idlethread));
967 mtx_lock_spin(&ap_boot_mtx);
969 /* Init local apic for irq's */
972 /* Set memory range attributes for this CPU to match the BSP */
977 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
978 printf("SMP: AP CPU #%d Launched!\n", cpuid);
980 /* Determine if we are a logical CPU. */
981 if (cpu_info[PCPU_GET(apic_id)].cpu_hyperthread)
982 CPU_SET(cpuid, &logical_cpus_mask);
987 if (smp_cpus == mp_ncpus) {
988 /* enable IPI's, tlb shootdown, freezes etc */
989 atomic_store_rel_int(&smp_started, 1);
994 * Enable global pages TLB extension
995 * This also implicitly flushes the TLB
997 load_cr4(rcr4() | CR4_PGE);
998 if (pmap_pcid_enabled)
999 load_cr4(rcr4() | CR4_PCIDE);
1005 mtx_unlock_spin(&ap_boot_mtx);
1007 /* Wait until all the AP's are up. */
1008 while (atomic_load_acq_int(&smp_started) == 0)
1011 #ifndef EARLY_AP_STARTUP
1012 /* Start per-CPU event timers. */
1013 cpu_initclocks_ap();
1018 panic("scheduler returned us to %s", __func__);
1022 /*******************************************************************
1023 * local functions and data
1027 * We tell the I/O APIC code about all the CPUs we want to receive
1028 * interrupts. If we don't want certain CPUs to receive IRQs we
1029 * can simply not tell the I/O APIC code about them in this function.
1030 * We also do not tell it about the BSP since it tells itself about
1031 * the BSP internally to work with UP kernels and on UP machines.
1034 set_interrupt_apic_ids(void)
1038 for (i = 0; i < MAXCPU; i++) {
1039 apic_id = cpu_apic_ids[i];
1042 if (cpu_info[apic_id].cpu_bsp)
1044 if (cpu_info[apic_id].cpu_disabled)
1047 /* Don't let hyperthreads service interrupts. */
1048 if (cpu_info[apic_id].cpu_hyperthread)
1056 #ifdef COUNT_XINVLTLB_HITS
1057 u_int xhits_gbl[MAXCPU];
1058 u_int xhits_pg[MAXCPU];
1059 u_int xhits_rng[MAXCPU];
1060 static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1061 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1062 sizeof(xhits_gbl), "IU", "");
1063 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1064 sizeof(xhits_pg), "IU", "");
1065 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1066 sizeof(xhits_rng), "IU", "");
1071 u_int ipi_range_size;
1072 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1073 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1074 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1075 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1077 #endif /* COUNT_XINVLTLB_HITS */
1080 * Init and startup IPI.
1083 ipi_startup(int apic_id, int vector)
1087 * This attempts to follow the algorithm described in the
1088 * Intel Multiprocessor Specification v1.4 in section B.4.
1089 * For each IPI, we allow the local APIC ~20us to deliver the
1090 * IPI. If that times out, we panic.
1094 * first we do an INIT IPI: this INIT IPI might be run, resetting
1095 * and running the target CPU. OR this INIT IPI might be latched (P5
1096 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1099 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1100 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1101 lapic_ipi_wait(100);
1103 /* Explicitly deassert the INIT IPI. */
1104 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1105 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT,
1108 DELAY(10000); /* wait ~10mS */
1111 * next we do a STARTUP IPI: the previous INIT IPI might still be
1112 * latched, (P5 bug) this 1st STARTUP would then terminate
1113 * immediately, and the previously started INIT IPI would continue. OR
1114 * the previous INIT IPI has already run. and this STARTUP IPI will
1115 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1118 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1119 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1121 if (!lapic_ipi_wait(100))
1122 panic("Failed to deliver first STARTUP IPI to APIC %d",
1124 DELAY(200); /* wait ~200uS */
1127 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1128 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1129 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1130 * recognized after hardware RESET or INIT IPI.
1132 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1133 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1135 if (!lapic_ipi_wait(100))
1136 panic("Failed to deliver second STARTUP IPI to APIC %d",
1139 DELAY(200); /* wait ~200uS */
1143 * Send an IPI to specified CPU handling the bitmap logic.
1146 ipi_send_cpu(int cpu, u_int ipi)
1148 u_int bitmap, old_pending, new_pending;
1150 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1152 if (IPI_IS_BITMAPED(ipi)) {
1154 ipi = IPI_BITMAP_VECTOR;
1156 old_pending = cpu_ipi_pending[cpu];
1157 new_pending = old_pending | bitmap;
1158 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1159 old_pending, new_pending));
1163 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1167 ipi_bitmap_handler(struct trapframe frame)
1169 struct trapframe *oldframe;
1171 int cpu = PCPU_GET(cpuid);
1176 td->td_intr_nesting_level++;
1177 oldframe = td->td_intr_frame;
1178 td->td_intr_frame = &frame;
1179 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1180 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1182 (*ipi_preempt_counts[cpu])++;
1186 if (ipi_bitmap & (1 << IPI_AST)) {
1188 (*ipi_ast_counts[cpu])++;
1190 /* Nothing to do for AST */
1192 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1194 (*ipi_hardclock_counts[cpu])++;
1198 td->td_intr_frame = oldframe;
1199 td->td_intr_nesting_level--;
1204 * send an IPI to a set of cpus.
1207 ipi_selected(cpuset_t cpus, u_int ipi)
1212 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1213 * of help in order to understand what is the source.
1214 * Set the mask of receiving CPUs for this purpose.
1216 if (ipi == IPI_STOP_HARD)
1217 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &cpus);
1219 while ((cpu = CPU_FFS(&cpus)) != 0) {
1221 CPU_CLR(cpu, &cpus);
1222 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1223 ipi_send_cpu(cpu, ipi);
1228 * send an IPI to a specific CPU.
1231 ipi_cpu(int cpu, u_int ipi)
1235 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1236 * of help in order to understand what is the source.
1237 * Set the mask of receiving CPUs for this purpose.
1239 if (ipi == IPI_STOP_HARD)
1240 CPU_SET_ATOMIC(cpu, &ipi_stop_nmi_pending);
1242 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1243 ipi_send_cpu(cpu, ipi);
1247 * send an IPI to all CPUs EXCEPT myself
1250 ipi_all_but_self(u_int ipi)
1252 cpuset_t other_cpus;
1254 other_cpus = all_cpus;
1255 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1256 if (IPI_IS_BITMAPED(ipi)) {
1257 ipi_selected(other_cpus, ipi);
1262 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1263 * of help in order to understand what is the source.
1264 * Set the mask of receiving CPUs for this purpose.
1266 if (ipi == IPI_STOP_HARD)
1267 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &other_cpus);
1269 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1270 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1274 ipi_nmi_handler(void)
1279 * As long as there is not a simple way to know about a NMI's
1280 * source, if the bitmask for the current CPU is present in
1281 * the global pending bitword an IPI_STOP_HARD has been issued
1282 * and should be handled.
1284 cpuid = PCPU_GET(cpuid);
1285 if (!CPU_ISSET(cpuid, &ipi_stop_nmi_pending))
1288 CPU_CLR_ATOMIC(cpuid, &ipi_stop_nmi_pending);
1297 nmi_call_kdb_smp(u_int type, struct trapframe *frame)
1302 cpu = PCPU_GET(cpuid);
1303 if (atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1)) {
1304 nmi_call_kdb(cpu, type, frame);
1307 savectx(&stoppcbs[cpu]);
1308 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1309 while (!atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1))
1313 atomic_store_rel_int(&nmi_kdb_lock, 0);
1315 cpustop_handler_post(cpu);
1320 * Handle an IPI_STOP by saving our current context and spinning until we
1324 cpustop_handler(void)
1328 cpu = PCPU_GET(cpuid);
1330 savectx(&stoppcbs[cpu]);
1332 /* Indicate that we are stopped */
1333 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1335 /* Wait for restart */
1336 while (!CPU_ISSET(cpu, &started_cpus))
1339 cpustop_handler_post(cpu);
1343 cpustop_handler_post(u_int cpu)
1346 CPU_CLR_ATOMIC(cpu, &started_cpus);
1347 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1350 * We don't broadcast TLB invalidations to other CPUs when they are
1351 * stopped. Hence, we clear the TLB before resuming.
1355 #if defined(__amd64__) && defined(DDB)
1356 amd64_db_resume_dbreg();
1359 if (cpu == 0 && cpustop_restartfunc != NULL) {
1360 cpustop_restartfunc();
1361 cpustop_restartfunc = NULL;
1366 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1370 cpususpend_handler(void)
1374 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED);
1376 cpu = PCPU_GET(cpuid);
1377 if (savectx(&susppcbs[cpu]->sp_pcb)) {
1379 fpususpend(susppcbs[cpu]->sp_fpususpend);
1381 npxsuspend(susppcbs[cpu]->sp_fpususpend);
1384 CPU_SET_ATOMIC(cpu, &suspended_cpus);
1386 * Hack for xen, which does not use resumectx() so never
1387 * uses the next clause: set resuming_cpus early so that
1388 * resume_cpus() can wait on the same bitmap for acpi and
1389 * xen. resuming_cpus now means eventually_resumable_cpus.
1391 CPU_SET_ATOMIC(cpu, &resuming_cpus);
1394 fpuresume(susppcbs[cpu]->sp_fpususpend);
1396 npxresume(susppcbs[cpu]->sp_fpususpend);
1400 PCPU_SET(switchtime, 0);
1401 PCPU_SET(switchticks, ticks);
1403 /* Indicate that we are resuming */
1404 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1407 /* Wait for resume directive */
1408 while (!CPU_ISSET(cpu, &toresume_cpus))
1412 /* Finish removing the identity mapping of low memory for this AP. */
1416 if (cpu_ops.cpu_resume)
1417 cpu_ops.cpu_resume();
1423 /* Resume MCA and local APIC */
1428 /* Indicate that we are resumed */
1429 CPU_CLR_ATOMIC(cpu, &resuming_cpus);
1430 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1431 CPU_CLR_ATOMIC(cpu, &toresume_cpus);
1436 invlcache_handler(void)
1438 uint32_t generation;
1441 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
1442 #endif /* COUNT_IPIS */
1445 * Reading the generation here allows greater parallelism
1446 * since wbinvd is a serializing instruction. Without the
1447 * temporary, we'd wait for wbinvd to complete, then the read
1448 * would execute, then the dependent write, which must then
1449 * complete before return from interrupt.
1451 generation = smp_tlb_generation;
1453 PCPU_SET(smp_tlb_done, generation);
1457 * This is called once the rest of the system is up and running and we're
1458 * ready to let the AP's out of the pen.
1461 release_aps(void *dummy __unused)
1466 atomic_store_rel_int(&aps_ready, 1);
1467 while (smp_started == 0)
1470 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1474 * Setup interrupt counters for IPI handlers.
1477 mp_ipi_intrcnt(void *dummy)
1483 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1484 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1485 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1486 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1487 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1488 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1489 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
1490 intrcnt_add(buf, &ipi_invlcache_counts[i]);
1491 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1492 intrcnt_add(buf, &ipi_preempt_counts[i]);
1493 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1494 intrcnt_add(buf, &ipi_ast_counts[i]);
1495 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1496 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1497 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1498 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1501 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
1505 * Flush the TLB on other CPU's
1508 /* Variables needed for SMP tlb shootdown. */
1509 static vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
1510 pmap_t smp_tlb_pmap;
1511 volatile uint32_t smp_tlb_generation;
1514 #define read_eflags() read_rflags()
1518 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
1519 vm_offset_t addr1, vm_offset_t addr2)
1521 cpuset_t other_cpus;
1522 volatile uint32_t *p_cpudone;
1523 uint32_t generation;
1526 /* It is not necessary to signal other CPUs while in the debugger. */
1527 if (kdb_active || panicstr != NULL)
1531 * Check for other cpus. Return if none.
1533 if (CPU_ISFULLSET(&mask)) {
1537 CPU_CLR(PCPU_GET(cpuid), &mask);
1538 if (CPU_EMPTY(&mask))
1542 if (!(read_eflags() & PSL_I))
1543 panic("%s: interrupts disabled", __func__);
1544 mtx_lock_spin(&smp_ipi_mtx);
1545 smp_tlb_addr1 = addr1;
1546 smp_tlb_addr2 = addr2;
1547 smp_tlb_pmap = pmap;
1548 generation = ++smp_tlb_generation;
1549 if (CPU_ISFULLSET(&mask)) {
1550 ipi_all_but_self(vector);
1551 other_cpus = all_cpus;
1552 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1555 while ((cpu = CPU_FFS(&mask)) != 0) {
1557 CPU_CLR(cpu, &mask);
1558 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
1560 ipi_send_cpu(cpu, vector);
1563 while ((cpu = CPU_FFS(&other_cpus)) != 0) {
1565 CPU_CLR(cpu, &other_cpus);
1566 p_cpudone = &cpuid_to_pcpu[cpu]->pc_smp_tlb_done;
1567 while (*p_cpudone != generation)
1570 mtx_unlock_spin(&smp_ipi_mtx);
1574 smp_masked_invltlb(cpuset_t mask, pmap_t pmap)
1578 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0);
1579 #ifdef COUNT_XINVLTLB_HITS
1586 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
1590 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, NULL, addr, 0);
1591 #ifdef COUNT_XINVLTLB_HITS
1598 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
1602 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, NULL,
1604 #ifdef COUNT_XINVLTLB_HITS
1606 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1612 smp_cache_flush(void)
1616 smp_targeted_tlb_shootdown(all_cpus, IPI_INVLCACHE, NULL,
1622 * Handlers for TLB related IPIs
1625 invltlb_handler(void)
1627 uint32_t generation;
1629 #ifdef COUNT_XINVLTLB_HITS
1630 xhits_gbl[PCPU_GET(cpuid)]++;
1631 #endif /* COUNT_XINVLTLB_HITS */
1633 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1634 #endif /* COUNT_IPIS */
1637 * Reading the generation here allows greater parallelism
1638 * since invalidating the TLB is a serializing operation.
1640 generation = smp_tlb_generation;
1641 if (smp_tlb_pmap == kernel_pmap)
1645 PCPU_SET(smp_tlb_done, generation);
1649 invlpg_handler(void)
1651 uint32_t generation;
1653 #ifdef COUNT_XINVLTLB_HITS
1654 xhits_pg[PCPU_GET(cpuid)]++;
1655 #endif /* COUNT_XINVLTLB_HITS */
1657 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1658 #endif /* COUNT_IPIS */
1660 generation = smp_tlb_generation; /* Overlap with serialization */
1661 invlpg(smp_tlb_addr1);
1662 PCPU_SET(smp_tlb_done, generation);
1666 invlrng_handler(void)
1668 vm_offset_t addr, addr2;
1669 uint32_t generation;
1671 #ifdef COUNT_XINVLTLB_HITS
1672 xhits_rng[PCPU_GET(cpuid)]++;
1673 #endif /* COUNT_XINVLTLB_HITS */
1675 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
1676 #endif /* COUNT_IPIS */
1678 addr = smp_tlb_addr1;
1679 addr2 = smp_tlb_addr2;
1680 generation = smp_tlb_generation; /* Overlap with serialization */
1684 } while (addr < addr2);
1686 PCPU_SET(smp_tlb_done, generation);