2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
35 #include "opt_kstack_pages.h"
37 #include "opt_sched.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/cons.h> /* cngetc() */
44 #include <sys/cpuset.h>
49 #include <sys/kernel.h>
52 #include <sys/malloc.h>
53 #include <sys/memrange.h>
54 #include <sys/mutex.h>
57 #include <sys/sched.h>
59 #include <sys/sysctl.h>
62 #include <vm/vm_param.h>
64 #include <vm/vm_kern.h>
65 #include <vm/vm_extern.h>
67 #include <x86/apicreg.h>
68 #include <machine/clock.h>
69 #include <machine/cputypes.h>
71 #include <machine/md_var.h>
72 #include <machine/pcb.h>
73 #include <machine/psl.h>
74 #include <machine/smp.h>
75 #include <machine/specialreg.h>
76 #include <machine/cpu.h>
78 #define WARMBOOT_TARGET 0
79 #define WARMBOOT_OFF (KERNBASE + 0x0467)
80 #define WARMBOOT_SEG (KERNBASE + 0x0469)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 /* lock region used by kernel profiling */
90 int mp_naps; /* # of Applications processors */
91 int boot_cpu_id = -1; /* designated BSP */
93 extern struct pcpu __pcpu[];
95 /* AP uses this during bootstrap. Do not staticize. */
99 /* Free these after use */
100 void *bootstacks[MAXCPU];
103 struct pcb stoppcbs[MAXCPU];
104 struct susppcb **susppcbs;
107 /* Interrupt counts. */
108 static u_long *ipi_preempt_counts[MAXCPU];
109 static u_long *ipi_ast_counts[MAXCPU];
110 u_long *ipi_invltlb_counts[MAXCPU];
111 u_long *ipi_invlrng_counts[MAXCPU];
112 u_long *ipi_invlpg_counts[MAXCPU];
113 u_long *ipi_invlcache_counts[MAXCPU];
114 u_long *ipi_rendezvous_counts[MAXCPU];
115 static u_long *ipi_hardclock_counts[MAXCPU];
118 /* Default cpu_ops implementation. */
119 struct cpu_ops cpu_ops;
122 * Local data and functions.
125 static volatile cpuset_t ipi_stop_nmi_pending;
127 /* used to hold the AP's until we are ready to release them */
128 struct mtx ap_boot_mtx;
130 /* Set to 1 once we're ready to let the APs out of the pen. */
131 volatile int aps_ready = 0;
134 * Store data from cpu_add() until later in the boot when we actually setup
137 struct cpu_info cpu_info[MAX_APIC_ID + 1];
138 int apic_cpuids[MAX_APIC_ID + 1];
139 int cpu_apic_ids[MAXCPU];
141 /* Holds pending bitmap based IPIs per CPU */
142 volatile u_int cpu_ipi_pending[MAXCPU];
144 static void release_aps(void *dummy);
145 static void cpustop_handler_post(u_int cpu);
147 static int hyperthreading_allowed = 1;
148 SYSCTL_INT(_machdep, OID_AUTO, hyperthreading_allowed, CTLFLAG_RDTUN,
149 &hyperthreading_allowed, 0, "Use Intel HTT logical CPUs");
151 static struct topo_node topo_root;
153 static int pkg_id_shift;
154 static int core_id_shift;
155 static int disabled_cpus;
160 } static caches[MAX_CACHE_LEVELS];
163 mem_range_AP_init(void)
166 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
167 mem_range_softc.mr_op->initAP(&mem_range_softc);
171 * Round up to the next power of two, if necessary, and then
173 * Returns -1 if argument is zero.
179 return (fls(x << (1 - powerof2(x))) - 1);
183 * Add a cache level to the cache topology description.
186 add_deterministic_cache(int type, int level, int share_count)
192 printf("unexpected cache type %d\n", type);
195 if (type == 2) /* ignore instruction cache */
197 if (level == 0 || level > MAX_CACHE_LEVELS) {
198 printf("unexpected cache level %d\n", type);
202 if (caches[level - 1].present) {
203 printf("WARNING: multiple entries for L%u data cache\n", level);
204 printf("%u => %u\n", caches[level - 1].id_shift,
205 mask_width(share_count));
207 caches[level - 1].id_shift = mask_width(share_count);
208 caches[level - 1].present = 1;
210 if (caches[level - 1].id_shift > pkg_id_shift) {
211 printf("WARNING: L%u data cache covers more "
212 "APIC IDs than a package (%u > %u)\n", level,
213 caches[level - 1].id_shift, pkg_id_shift);
214 caches[level - 1].id_shift = pkg_id_shift;
216 if (caches[level - 1].id_shift < core_id_shift) {
217 printf("WARNING: L%u data cache covers fewer "
218 "APIC IDs than a core (%u < %u)\n", level,
219 caches[level - 1].id_shift, core_id_shift);
220 caches[level - 1].id_shift = core_id_shift;
227 * Determine topology of processing units and caches for AMD CPUs.
229 * - AMD CPUID Specification (Publication # 25481)
230 * - BKDG for AMD NPT Family 0Fh Processors (Publication # 32559)
231 * - BKDG For AMD Family 10h Processors (Publication # 31116)
232 * - BKDG For AMD Family 15h Models 00h-0Fh Processors (Publication # 42301)
233 * - BKDG For AMD Family 16h Models 00h-0Fh Processors (Publication # 48751)
244 /* No multi-core capability. */
245 if ((amd_feature2 & AMDID2_CMP) == 0)
248 /* For families 10h and newer. */
249 pkg_id_shift = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
250 AMDID_COREID_SIZE_SHIFT;
252 /* For 0Fh family. */
253 if (pkg_id_shift == 0)
255 mask_width((cpu_procinfo2 & AMDID_CMP_CORES) + 1);
258 * Families prior to 16h define the following value as
259 * cores per compute unit and we don't really care about the AMD
260 * compute units at the moment. Perhaps we should treat them as
261 * cores and cores within the compute units as hardware threads,
262 * but that's up for debate.
263 * Later families define the value as threads per compute unit,
264 * so we are following AMD's nomenclature here.
266 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0 &&
267 CPUID_TO_FAMILY(cpu_id) >= 0x16) {
268 cpuid_count(0x8000001e, 0, p);
269 share_count = ((p[1] >> 8) & 0xff) + 1;
270 core_id_shift = mask_width(share_count);
273 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0) {
275 cpuid_count(0x8000001d, i, p);
277 level = (p[0] >> 5) & 0x7;
278 share_count = 1 + ((p[0] >> 14) & 0xfff);
280 if (!add_deterministic_cache(type, level, share_count))
284 if (cpu_exthigh >= 0x80000005) {
285 cpuid_count(0x80000005, 0, p);
286 if (((p[2] >> 24) & 0xff) != 0) {
287 caches[0].id_shift = 0;
288 caches[0].present = 1;
291 if (cpu_exthigh >= 0x80000006) {
292 cpuid_count(0x80000006, 0, p);
293 if (((p[2] >> 16) & 0xffff) != 0) {
294 caches[1].id_shift = 0;
295 caches[1].present = 1;
297 if (((p[3] >> 18) & 0x3fff) != 0) {
300 * TODO: Account for dual-node processors
301 * where each node within a package has its own
304 caches[2].id_shift = pkg_id_shift;
305 caches[2].present = 1;
312 * Determine topology of processing units for Intel CPUs
313 * using CPUID Leaf 1 and Leaf 4, if supported.
315 * - Intel 64 Architecture Processor Topology Enumeration
316 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
317 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
318 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
321 topo_probe_intel_0x4(void)
327 /* Both zero and one here mean one logical processor per package. */
328 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
329 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
330 if (max_logical <= 1)
333 if (cpu_high >= 0x4) {
334 cpuid_count(0x04, 0, p);
335 max_cores = ((p[0] >> 26) & 0x3f) + 1;
339 core_id_shift = mask_width(max_logical/max_cores);
340 KASSERT(core_id_shift >= 0,
341 ("intel topo: max_cores > max_logical\n"));
342 pkg_id_shift = core_id_shift + mask_width(max_cores);
346 * Determine topology of processing units for Intel CPUs
347 * using CPUID Leaf 11, if supported.
349 * - Intel 64 Architecture Processor Topology Enumeration
350 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
351 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
352 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
355 topo_probe_intel_0xb(void)
362 /* Fall back if CPU leaf 11 doesn't really exist. */
363 cpuid_count(0x0b, 0, p);
365 topo_probe_intel_0x4();
369 /* We only support three levels for now. */
371 cpuid_count(0x0b, i, p);
374 type = (p[2] >> 8) & 0xff;
379 /* TODO: check for duplicate (re-)assignment */
380 if (type == CPUID_TYPE_SMT)
381 core_id_shift = bits;
382 else if (type == CPUID_TYPE_CORE)
385 printf("unknown CPU level type %d\n", type);
388 if (pkg_id_shift < core_id_shift) {
389 printf("WARNING: core covers more APIC IDs than a package\n");
390 core_id_shift = pkg_id_shift;
395 * Determine topology of caches for Intel CPUs.
397 * - Intel 64 Architecture Processor Topology Enumeration
398 * - Intel 64 and IA-32 Architectures Software Developer’s Manual
399 * Volume 2A: Instruction Set Reference, A-M,
403 topo_probe_intel_caches(void)
411 if (cpu_high < 0x4) {
413 * Available cache level and sizes can be determined
414 * via CPUID leaf 2, but that requires a huge table of hardcoded
415 * values, so for now just assume L1 and L2 caches potentially
416 * shared only by HTT processing units, if HTT is present.
418 caches[0].id_shift = pkg_id_shift;
419 caches[0].present = 1;
420 caches[1].id_shift = pkg_id_shift;
421 caches[1].present = 1;
426 cpuid_count(0x4, i, p);
428 level = (p[0] >> 5) & 0x7;
429 share_count = 1 + ((p[0] >> 14) & 0xfff);
431 if (!add_deterministic_cache(type, level, share_count))
437 * Determine topology of processing units and caches for Intel CPUs.
439 * - Intel 64 Architecture Processor Topology Enumeration
442 topo_probe_intel(void)
446 * Note that 0x1 <= cpu_high < 4 case should be
447 * compatible with topo_probe_intel_0x4() logic when
448 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
449 * or it should trigger the fallback otherwise.
452 topo_probe_intel_0xb();
453 else if (cpu_high >= 0x1)
454 topo_probe_intel_0x4();
456 topo_probe_intel_caches();
460 * Topology information is queried only on BSP, on which this
461 * code runs and for which it can query CPUID information.
462 * Then topology is extrapolated on all packages using an
463 * assumption that APIC ID to hardware component ID mapping is
465 * That doesn't necesserily imply that the topology is uniform.
470 static int cpu_topo_probed = 0;
471 struct x86_topo_layer {
475 } topo_layers[MAX_CACHE_LEVELS + 3];
476 struct topo_node *parent;
477 struct topo_node *node;
486 CPU_ZERO(&logical_cpus_mask);
490 else if (cpu_vendor_id == CPU_VENDOR_AMD)
492 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
495 KASSERT(pkg_id_shift >= core_id_shift,
496 ("bug in APIC topology discovery"));
499 bzero(topo_layers, sizeof(topo_layers));
501 topo_layers[nlayers].type = TOPO_TYPE_PKG;
502 topo_layers[nlayers].id_shift = pkg_id_shift;
504 printf("Package ID shift: %u\n", topo_layers[nlayers].id_shift);
508 * Consider all caches to be within a package/chip
509 * and "in front" of all sub-components like
510 * cores and hardware threads.
512 for (i = MAX_CACHE_LEVELS - 1; i >= 0; --i) {
513 if (caches[i].present) {
514 KASSERT(caches[i].id_shift <= pkg_id_shift,
515 ("bug in APIC topology discovery"));
516 KASSERT(caches[i].id_shift >= core_id_shift,
517 ("bug in APIC topology discovery"));
519 topo_layers[nlayers].type = TOPO_TYPE_CACHE;
520 topo_layers[nlayers].subtype = i + 1;
521 topo_layers[nlayers].id_shift = caches[i].id_shift;
523 printf("L%u cache ID shift: %u\n",
524 topo_layers[nlayers].subtype,
525 topo_layers[nlayers].id_shift);
530 if (pkg_id_shift > core_id_shift) {
531 topo_layers[nlayers].type = TOPO_TYPE_CORE;
532 topo_layers[nlayers].id_shift = core_id_shift;
534 printf("Core ID shift: %u\n",
535 topo_layers[nlayers].id_shift);
539 topo_layers[nlayers].type = TOPO_TYPE_PU;
540 topo_layers[nlayers].id_shift = 0;
543 topo_init_root(&topo_root);
544 for (i = 0; i <= MAX_APIC_ID; ++i) {
545 if (!cpu_info[i].cpu_present)
549 for (layer = 0; layer < nlayers; ++layer) {
550 node_id = i >> topo_layers[layer].id_shift;
551 parent = topo_add_node_by_hwid(parent, node_id,
552 topo_layers[layer].type,
553 topo_layers[layer].subtype);
558 for (layer = 0; layer < nlayers; ++layer) {
559 node_id = boot_cpu_id >> topo_layers[layer].id_shift;
560 node = topo_find_node_by_hwid(parent, node_id,
561 topo_layers[layer].type,
562 topo_layers[layer].subtype);
563 topo_promote_child(node);
571 * Assign logical CPU IDs to local APICs.
576 struct topo_node *node;
579 smt_mask = (1u << core_id_shift) - 1;
582 * Assign CPU IDs to local APIC IDs and disable any CPUs
583 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
586 TOPO_FOREACH(node, &topo_root) {
587 if (node->type != TOPO_TYPE_PU)
590 if ((node->hwid & smt_mask) != (boot_cpu_id & smt_mask))
591 cpu_info[node->hwid].cpu_hyperthread = 1;
593 if (resource_disabled("lapic", node->hwid)) {
594 if (node->hwid != boot_cpu_id)
595 cpu_info[node->hwid].cpu_disabled = 1;
597 printf("Cannot disable BSP, APIC ID = %d\n",
601 if (!hyperthreading_allowed &&
602 cpu_info[node->hwid].cpu_hyperthread)
603 cpu_info[node->hwid].cpu_disabled = 1;
605 if (mp_ncpus >= MAXCPU)
606 cpu_info[node->hwid].cpu_disabled = 1;
608 if (cpu_info[node->hwid].cpu_disabled) {
613 cpu_apic_ids[mp_ncpus] = node->hwid;
614 apic_cpuids[node->hwid] = mp_ncpus;
615 topo_set_pu_id(node, mp_ncpus);
619 KASSERT(mp_maxid >= mp_ncpus - 1,
620 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
625 * Print various information about the SMP system hardware and setup.
628 cpu_mp_announce(void)
630 struct topo_node *node;
631 const char *hyperthread;
636 printf("FreeBSD/SMP: ");
637 if (topo_analyze(&topo_root, 1, &pkg_count,
638 &cores_per_pkg, &thrs_per_core)) {
639 printf("%d package(s)", pkg_count);
640 if (cores_per_pkg > 0)
641 printf(" x %d core(s)", cores_per_pkg);
642 if (thrs_per_core > 1)
643 printf(" x %d hardware threads", thrs_per_core);
645 printf("Non-uniform topology");
650 printf("FreeBSD/SMP Online: ");
651 if (topo_analyze(&topo_root, 0, &pkg_count,
652 &cores_per_pkg, &thrs_per_core)) {
653 printf("%d package(s)", pkg_count);
654 if (cores_per_pkg > 0)
655 printf(" x %d core(s)", cores_per_pkg);
656 if (thrs_per_core > 1)
657 printf(" x %d hardware threads", thrs_per_core);
659 printf("Non-uniform topology");
667 TOPO_FOREACH(node, &topo_root) {
668 switch (node->type) {
670 printf("Package HW ID = %u\n", node->hwid);
673 printf("\tCore HW ID = %u\n", node->hwid);
676 if (cpu_info[node->hwid].cpu_hyperthread)
681 if (node->subtype == 0)
682 printf("\t\tCPU (AP%s): APIC ID: %u"
683 "(disabled)\n", hyperthread, node->hwid);
684 else if (node->id == 0)
685 printf("\t\tCPU0 (BSP): APIC ID: %u\n",
688 printf("\t\tCPU%u (AP%s): APIC ID: %u\n",
689 node->id, hyperthread, node->hwid);
699 * Add a scheduling group, a group of logical processors sharing
700 * a particular cache (and, thus having an affinity), to the scheduling
702 * This function recursively works on lower level caches.
705 x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
707 struct topo_node *node;
712 KASSERT(root->type == TOPO_TYPE_SYSTEM || root->type == TOPO_TYPE_CACHE,
713 ("x86topo_add_sched_group: bad type: %u", root->type));
714 CPU_COPY(&root->cpuset, &cg_root->cg_mask);
715 cg_root->cg_count = root->cpu_count;
716 if (root->type == TOPO_TYPE_SYSTEM)
717 cg_root->cg_level = CG_SHARE_NONE;
719 cg_root->cg_level = root->subtype;
722 * Check how many core nodes we have under the given root node.
723 * If we have multiple logical processors, but not multiple
724 * cores, then those processors must be hardware threads.
728 while (node != NULL) {
729 if (node->type != TOPO_TYPE_CORE) {
730 node = topo_next_node(root, node);
735 node = topo_next_nonchild_node(root, node);
738 if (cg_root->cg_level != CG_SHARE_NONE &&
739 root->cpu_count > 1 && ncores < 2)
740 cg_root->cg_flags = CG_FLAG_SMT;
743 * Find out how many cache nodes we have under the given root node.
744 * We ignore cache nodes that cover all the same processors as the
745 * root node. Also, we do not descend below found cache nodes.
746 * That is, we count top-level "non-redundant" caches under the root
751 while (node != NULL) {
752 if (node->type != TOPO_TYPE_CACHE ||
753 (root->type != TOPO_TYPE_SYSTEM &&
754 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
755 node = topo_next_node(root, node);
759 node = topo_next_nonchild_node(root, node);
762 cg_root->cg_child = smp_topo_alloc(nchildren);
763 cg_root->cg_children = nchildren;
766 * Now find again the same cache nodes as above and recursively
767 * build scheduling topologies for them.
771 while (node != NULL) {
772 if (node->type != TOPO_TYPE_CACHE ||
773 (root->type != TOPO_TYPE_SYSTEM &&
774 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
775 node = topo_next_node(root, node);
778 cg_root->cg_child[i].cg_parent = cg_root;
779 x86topo_add_sched_group(node, &cg_root->cg_child[i]);
781 node = topo_next_nonchild_node(root, node);
786 * Build the MI scheduling topology from the discovered hardware topology.
791 struct cpu_group *cg_root;
794 return (smp_topo_none());
796 cg_root = smp_topo_alloc(1);
797 x86topo_add_sched_group(&topo_root, cg_root);
803 * Add a logical CPU to the topology.
806 cpu_add(u_int apic_id, char boot_cpu)
809 if (apic_id > MAX_APIC_ID) {
810 panic("SMP: APIC ID %d too high", apic_id);
813 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
815 cpu_info[apic_id].cpu_present = 1;
817 KASSERT(boot_cpu_id == -1,
818 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
820 boot_cpu_id = apic_id;
821 cpu_info[apic_id].cpu_bsp = 1;
823 if (mp_ncpus < MAXCPU) {
825 mp_maxid = mp_ncpus - 1;
828 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
833 cpu_mp_setmaxid(void)
837 * mp_ncpus and mp_maxid should be already set by calls to cpu_add().
838 * If there were no calls to cpu_add() assume this is a UP system.
849 * Always record BSP in CPU map so that the mbuf init code works
852 CPU_SETOF(0, &all_cpus);
853 return (mp_ncpus > 1);
857 * AP CPU's call this to initialize themselves.
860 init_secondary_tail(void)
865 * On real hardware, switch to x2apic mode if possible. Do it
866 * after aps_ready was signalled, to avoid manipulating the
867 * mode while BSP might still want to send some IPI to us
868 * (second startup IPI is ignored on modern hardware etc).
872 /* Initialize the PAT MSR. */
875 /* set up CPU registers and state */
881 /* set up FPU state on the AP */
888 if (cpu_ops.cpu_init)
891 /* A quick check from sanity claus */
892 cpuid = PCPU_GET(cpuid);
893 if (PCPU_GET(apic_id) != lapic_id()) {
894 printf("SMP: cpuid = %d\n", cpuid);
895 printf("SMP: actual apic_id = %d\n", lapic_id());
896 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
897 panic("cpuid mismatch! boom!!");
900 /* Initialize curthread. */
901 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
902 PCPU_SET(curthread, PCPU_GET(idlethread));
906 mtx_lock_spin(&ap_boot_mtx);
908 /* Init local apic for irq's */
911 /* Set memory range attributes for this CPU to match the BSP */
916 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
917 printf("SMP: AP CPU #%d Launched!\n", cpuid);
919 /* Determine if we are a logical CPU. */
920 if (cpu_info[PCPU_GET(apic_id)].cpu_hyperthread)
921 CPU_SET(cpuid, &logical_cpus_mask);
926 if (smp_cpus == mp_ncpus) {
927 /* enable IPI's, tlb shootdown, freezes etc */
928 atomic_store_rel_int(&smp_started, 1);
933 * Enable global pages TLB extension
934 * This also implicitly flushes the TLB
936 load_cr4(rcr4() | CR4_PGE);
937 if (pmap_pcid_enabled)
938 load_cr4(rcr4() | CR4_PCIDE);
944 mtx_unlock_spin(&ap_boot_mtx);
946 /* Wait until all the AP's are up. */
947 while (atomic_load_acq_int(&smp_started) == 0)
950 #ifndef EARLY_AP_STARTUP
951 /* Start per-CPU event timers. */
957 panic("scheduler returned us to %s", __func__);
961 /*******************************************************************
962 * local functions and data
966 * We tell the I/O APIC code about all the CPUs we want to receive
967 * interrupts. If we don't want certain CPUs to receive IRQs we
968 * can simply not tell the I/O APIC code about them in this function.
969 * We also do not tell it about the BSP since it tells itself about
970 * the BSP internally to work with UP kernels and on UP machines.
973 set_interrupt_apic_ids(void)
977 for (i = 0; i < MAXCPU; i++) {
978 apic_id = cpu_apic_ids[i];
981 if (cpu_info[apic_id].cpu_bsp)
983 if (cpu_info[apic_id].cpu_disabled)
986 /* Don't let hyperthreads service interrupts. */
987 if (cpu_info[apic_id].cpu_hyperthread)
995 #ifdef COUNT_XINVLTLB_HITS
996 u_int xhits_gbl[MAXCPU];
997 u_int xhits_pg[MAXCPU];
998 u_int xhits_rng[MAXCPU];
999 static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1000 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1001 sizeof(xhits_gbl), "IU", "");
1002 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1003 sizeof(xhits_pg), "IU", "");
1004 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1005 sizeof(xhits_rng), "IU", "");
1010 u_int ipi_range_size;
1011 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1012 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1013 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1014 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1016 #endif /* COUNT_XINVLTLB_HITS */
1019 * Init and startup IPI.
1022 ipi_startup(int apic_id, int vector)
1026 * This attempts to follow the algorithm described in the
1027 * Intel Multiprocessor Specification v1.4 in section B.4.
1028 * For each IPI, we allow the local APIC ~20us to deliver the
1029 * IPI. If that times out, we panic.
1033 * first we do an INIT IPI: this INIT IPI might be run, resetting
1034 * and running the target CPU. OR this INIT IPI might be latched (P5
1035 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1038 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1039 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1040 lapic_ipi_wait(100);
1042 /* Explicitly deassert the INIT IPI. */
1043 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1044 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT,
1047 DELAY(10000); /* wait ~10mS */
1050 * next we do a STARTUP IPI: the previous INIT IPI might still be
1051 * latched, (P5 bug) this 1st STARTUP would then terminate
1052 * immediately, and the previously started INIT IPI would continue. OR
1053 * the previous INIT IPI has already run. and this STARTUP IPI will
1054 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1057 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1058 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1060 if (!lapic_ipi_wait(100))
1061 panic("Failed to deliver first STARTUP IPI to APIC %d",
1063 DELAY(200); /* wait ~200uS */
1066 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1067 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1068 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1069 * recognized after hardware RESET or INIT IPI.
1071 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1072 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1074 if (!lapic_ipi_wait(100))
1075 panic("Failed to deliver second STARTUP IPI to APIC %d",
1078 DELAY(200); /* wait ~200uS */
1082 * Send an IPI to specified CPU handling the bitmap logic.
1085 ipi_send_cpu(int cpu, u_int ipi)
1087 u_int bitmap, old_pending, new_pending;
1089 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1091 if (IPI_IS_BITMAPED(ipi)) {
1093 ipi = IPI_BITMAP_VECTOR;
1095 old_pending = cpu_ipi_pending[cpu];
1096 new_pending = old_pending | bitmap;
1097 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1098 old_pending, new_pending));
1102 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1106 ipi_bitmap_handler(struct trapframe frame)
1108 struct trapframe *oldframe;
1110 int cpu = PCPU_GET(cpuid);
1115 td->td_intr_nesting_level++;
1116 oldframe = td->td_intr_frame;
1117 td->td_intr_frame = &frame;
1118 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1119 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1121 (*ipi_preempt_counts[cpu])++;
1125 if (ipi_bitmap & (1 << IPI_AST)) {
1127 (*ipi_ast_counts[cpu])++;
1129 /* Nothing to do for AST */
1131 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1133 (*ipi_hardclock_counts[cpu])++;
1137 td->td_intr_frame = oldframe;
1138 td->td_intr_nesting_level--;
1143 * send an IPI to a set of cpus.
1146 ipi_selected(cpuset_t cpus, u_int ipi)
1151 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1152 * of help in order to understand what is the source.
1153 * Set the mask of receiving CPUs for this purpose.
1155 if (ipi == IPI_STOP_HARD)
1156 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &cpus);
1158 while ((cpu = CPU_FFS(&cpus)) != 0) {
1160 CPU_CLR(cpu, &cpus);
1161 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1162 ipi_send_cpu(cpu, ipi);
1167 * send an IPI to a specific CPU.
1170 ipi_cpu(int cpu, u_int ipi)
1174 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1175 * of help in order to understand what is the source.
1176 * Set the mask of receiving CPUs for this purpose.
1178 if (ipi == IPI_STOP_HARD)
1179 CPU_SET_ATOMIC(cpu, &ipi_stop_nmi_pending);
1181 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1182 ipi_send_cpu(cpu, ipi);
1186 * send an IPI to all CPUs EXCEPT myself
1189 ipi_all_but_self(u_int ipi)
1191 cpuset_t other_cpus;
1193 other_cpus = all_cpus;
1194 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1195 if (IPI_IS_BITMAPED(ipi)) {
1196 ipi_selected(other_cpus, ipi);
1201 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1202 * of help in order to understand what is the source.
1203 * Set the mask of receiving CPUs for this purpose.
1205 if (ipi == IPI_STOP_HARD)
1206 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &other_cpus);
1208 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1209 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1213 ipi_nmi_handler(void)
1218 * As long as there is not a simple way to know about a NMI's
1219 * source, if the bitmask for the current CPU is present in
1220 * the global pending bitword an IPI_STOP_HARD has been issued
1221 * and should be handled.
1223 cpuid = PCPU_GET(cpuid);
1224 if (!CPU_ISSET(cpuid, &ipi_stop_nmi_pending))
1227 CPU_CLR_ATOMIC(cpuid, &ipi_stop_nmi_pending);
1236 nmi_call_kdb_smp(u_int type, struct trapframe *frame)
1241 cpu = PCPU_GET(cpuid);
1242 if (atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1)) {
1243 nmi_call_kdb(cpu, type, frame);
1246 savectx(&stoppcbs[cpu]);
1247 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1248 while (!atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1))
1252 atomic_store_rel_int(&nmi_kdb_lock, 0);
1254 cpustop_handler_post(cpu);
1259 * Handle an IPI_STOP by saving our current context and spinning until we
1263 cpustop_handler(void)
1267 cpu = PCPU_GET(cpuid);
1269 savectx(&stoppcbs[cpu]);
1271 /* Indicate that we are stopped */
1272 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1274 /* Wait for restart */
1275 while (!CPU_ISSET(cpu, &started_cpus))
1278 cpustop_handler_post(cpu);
1282 cpustop_handler_post(u_int cpu)
1285 CPU_CLR_ATOMIC(cpu, &started_cpus);
1286 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1289 * We don't broadcast TLB invalidations to other CPUs when they are
1290 * stopped. Hence, we clear the TLB before resuming.
1294 #if defined(__amd64__) && defined(DDB)
1295 amd64_db_resume_dbreg();
1298 if (cpu == 0 && cpustop_restartfunc != NULL) {
1299 cpustop_restartfunc();
1300 cpustop_restartfunc = NULL;
1305 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1309 cpususpend_handler(void)
1313 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED);
1315 cpu = PCPU_GET(cpuid);
1316 if (savectx(&susppcbs[cpu]->sp_pcb)) {
1318 fpususpend(susppcbs[cpu]->sp_fpususpend);
1320 npxsuspend(susppcbs[cpu]->sp_fpususpend);
1323 CPU_SET_ATOMIC(cpu, &suspended_cpus);
1326 fpuresume(susppcbs[cpu]->sp_fpususpend);
1328 npxresume(susppcbs[cpu]->sp_fpususpend);
1332 PCPU_SET(switchtime, 0);
1333 PCPU_SET(switchticks, ticks);
1335 /* Indicate that we are resumed */
1336 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1339 /* Wait for resume */
1340 while (!CPU_ISSET(cpu, &started_cpus))
1343 if (cpu_ops.cpu_resume)
1344 cpu_ops.cpu_resume();
1350 /* Resume MCA and local APIC */
1355 /* Indicate that we are resumed */
1356 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1357 CPU_CLR_ATOMIC(cpu, &started_cpus);
1362 invlcache_handler(void)
1364 uint32_t generation;
1367 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
1368 #endif /* COUNT_IPIS */
1371 * Reading the generation here allows greater parallelism
1372 * since wbinvd is a serializing instruction. Without the
1373 * temporary, we'd wait for wbinvd to complete, then the read
1374 * would execute, then the dependent write, which must then
1375 * complete before return from interrupt.
1377 generation = smp_tlb_generation;
1379 PCPU_SET(smp_tlb_done, generation);
1383 * This is called once the rest of the system is up and running and we're
1384 * ready to let the AP's out of the pen.
1387 release_aps(void *dummy __unused)
1392 atomic_store_rel_int(&aps_ready, 1);
1393 while (smp_started == 0)
1396 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1400 * Setup interrupt counters for IPI handlers.
1403 mp_ipi_intrcnt(void *dummy)
1409 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1410 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1411 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1412 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1413 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1414 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1415 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
1416 intrcnt_add(buf, &ipi_invlcache_counts[i]);
1417 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1418 intrcnt_add(buf, &ipi_preempt_counts[i]);
1419 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1420 intrcnt_add(buf, &ipi_ast_counts[i]);
1421 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1422 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1423 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1424 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1427 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
1431 * Flush the TLB on other CPU's
1434 /* Variables needed for SMP tlb shootdown. */
1435 static vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
1436 pmap_t smp_tlb_pmap;
1437 volatile uint32_t smp_tlb_generation;
1440 #define read_eflags() read_rflags()
1444 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
1445 vm_offset_t addr1, vm_offset_t addr2)
1447 cpuset_t other_cpus;
1448 volatile uint32_t *p_cpudone;
1449 uint32_t generation;
1452 /* It is not necessary to signal other CPUs while in the debugger. */
1453 if (kdb_active || panicstr != NULL)
1457 * Check for other cpus. Return if none.
1459 if (CPU_ISFULLSET(&mask)) {
1463 CPU_CLR(PCPU_GET(cpuid), &mask);
1464 if (CPU_EMPTY(&mask))
1468 if (!(read_eflags() & PSL_I))
1469 panic("%s: interrupts disabled", __func__);
1470 mtx_lock_spin(&smp_ipi_mtx);
1471 smp_tlb_addr1 = addr1;
1472 smp_tlb_addr2 = addr2;
1473 smp_tlb_pmap = pmap;
1474 generation = ++smp_tlb_generation;
1475 if (CPU_ISFULLSET(&mask)) {
1476 ipi_all_but_self(vector);
1477 other_cpus = all_cpus;
1478 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1481 while ((cpu = CPU_FFS(&mask)) != 0) {
1483 CPU_CLR(cpu, &mask);
1484 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
1486 ipi_send_cpu(cpu, vector);
1489 while ((cpu = CPU_FFS(&other_cpus)) != 0) {
1491 CPU_CLR(cpu, &other_cpus);
1492 p_cpudone = &cpuid_to_pcpu[cpu]->pc_smp_tlb_done;
1493 while (*p_cpudone != generation)
1496 mtx_unlock_spin(&smp_ipi_mtx);
1500 smp_masked_invltlb(cpuset_t mask, pmap_t pmap)
1504 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0);
1505 #ifdef COUNT_XINVLTLB_HITS
1512 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
1516 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, NULL, addr, 0);
1517 #ifdef COUNT_XINVLTLB_HITS
1524 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
1528 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, NULL,
1530 #ifdef COUNT_XINVLTLB_HITS
1532 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1538 smp_cache_flush(void)
1542 smp_targeted_tlb_shootdown(all_cpus, IPI_INVLCACHE, NULL,
1548 * Handlers for TLB related IPIs
1551 invltlb_handler(void)
1553 uint32_t generation;
1555 #ifdef COUNT_XINVLTLB_HITS
1556 xhits_gbl[PCPU_GET(cpuid)]++;
1557 #endif /* COUNT_XINVLTLB_HITS */
1559 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1560 #endif /* COUNT_IPIS */
1563 * Reading the generation here allows greater parallelism
1564 * since invalidating the TLB is a serializing operation.
1566 generation = smp_tlb_generation;
1567 if (smp_tlb_pmap == kernel_pmap)
1571 PCPU_SET(smp_tlb_done, generation);
1575 invlpg_handler(void)
1577 uint32_t generation;
1579 #ifdef COUNT_XINVLTLB_HITS
1580 xhits_pg[PCPU_GET(cpuid)]++;
1581 #endif /* COUNT_XINVLTLB_HITS */
1583 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1584 #endif /* COUNT_IPIS */
1586 generation = smp_tlb_generation; /* Overlap with serialization */
1587 invlpg(smp_tlb_addr1);
1588 PCPU_SET(smp_tlb_done, generation);
1592 invlrng_handler(void)
1594 vm_offset_t addr, addr2;
1595 uint32_t generation;
1597 #ifdef COUNT_XINVLTLB_HITS
1598 xhits_rng[PCPU_GET(cpuid)]++;
1599 #endif /* COUNT_XINVLTLB_HITS */
1601 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
1602 #endif /* COUNT_IPIS */
1604 addr = smp_tlb_addr1;
1605 addr2 = smp_tlb_addr2;
1606 generation = smp_tlb_generation; /* Overlap with serialization */
1610 } while (addr < addr2);
1612 PCPU_SET(smp_tlb_done, generation);