2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
35 #include "opt_kstack_pages.h"
37 #include "opt_sched.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/cons.h> /* cngetc() */
44 #include <sys/cpuset.h>
48 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/memrange.h>
53 #include <sys/mutex.h>
56 #include <sys/sched.h>
58 #include <sys/sysctl.h>
61 #include <vm/vm_param.h>
63 #include <vm/vm_kern.h>
64 #include <vm/vm_extern.h>
66 #include <x86/apicreg.h>
67 #include <machine/clock.h>
68 #include <machine/cputypes.h>
70 #include <machine/md_var.h>
71 #include <machine/pcb.h>
72 #include <machine/psl.h>
73 #include <machine/smp.h>
74 #include <machine/specialreg.h>
75 #include <machine/cpu.h>
77 #define WARMBOOT_TARGET 0
78 #define WARMBOOT_OFF (KERNBASE + 0x0467)
79 #define WARMBOOT_SEG (KERNBASE + 0x0469)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 /* lock region used by kernel profiling */
89 int mp_naps; /* # of Applications processors */
90 int boot_cpu_id = -1; /* designated BSP */
92 extern struct pcpu __pcpu[];
94 /* AP uses this during bootstrap. Do not staticize. */
98 /* Free these after use */
99 void *bootstacks[MAXCPU];
102 struct pcb stoppcbs[MAXCPU];
103 struct susppcb **susppcbs;
106 /* Interrupt counts. */
107 static u_long *ipi_preempt_counts[MAXCPU];
108 static u_long *ipi_ast_counts[MAXCPU];
109 u_long *ipi_invltlb_counts[MAXCPU];
110 u_long *ipi_invlrng_counts[MAXCPU];
111 u_long *ipi_invlpg_counts[MAXCPU];
112 u_long *ipi_invlcache_counts[MAXCPU];
113 u_long *ipi_rendezvous_counts[MAXCPU];
114 static u_long *ipi_hardclock_counts[MAXCPU];
117 /* Default cpu_ops implementation. */
118 struct cpu_ops cpu_ops;
121 * Local data and functions.
124 static volatile cpuset_t ipi_stop_nmi_pending;
126 /* used to hold the AP's until we are ready to release them */
127 struct mtx ap_boot_mtx;
129 /* Set to 1 once we're ready to let the APs out of the pen. */
130 volatile int aps_ready = 0;
133 * Store data from cpu_add() until later in the boot when we actually setup
136 struct cpu_info cpu_info[MAX_APIC_ID + 1];
137 int apic_cpuids[MAX_APIC_ID + 1];
138 int cpu_apic_ids[MAXCPU];
140 /* Holds pending bitmap based IPIs per CPU */
141 volatile u_int cpu_ipi_pending[MAXCPU];
143 static void release_aps(void *dummy);
144 static void cpustop_handler_post(u_int cpu);
146 static int hyperthreading_allowed = 1;
147 SYSCTL_INT(_machdep, OID_AUTO, hyperthreading_allowed, CTLFLAG_RDTUN,
148 &hyperthreading_allowed, 0, "Use Intel HTT logical CPUs");
150 static struct topo_node topo_root;
152 static int pkg_id_shift;
153 static int core_id_shift;
154 static int disabled_cpus;
159 } static caches[MAX_CACHE_LEVELS];
162 mem_range_AP_init(void)
165 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
166 mem_range_softc.mr_op->initAP(&mem_range_softc);
170 * Round up to the next power of two, if necessary, and then
172 * Returns -1 if argument is zero.
178 return (fls(x << (1 - powerof2(x))) - 1);
182 * Add a cache level to the cache topology description.
185 add_deterministic_cache(int type, int level, int share_count)
191 printf("unexpected cache type %d\n", type);
194 if (type == 2) /* ignore instruction cache */
196 if (level == 0 || level > MAX_CACHE_LEVELS) {
197 printf("unexpected cache level %d\n", type);
201 if (caches[level - 1].present) {
202 printf("WARNING: multiple entries for L%u data cache\n", level);
203 printf("%u => %u\n", caches[level - 1].id_shift,
204 mask_width(share_count));
206 caches[level - 1].id_shift = mask_width(share_count);
207 caches[level - 1].present = 1;
209 if (caches[level - 1].id_shift > pkg_id_shift) {
210 printf("WARNING: L%u data cache covers more "
211 "APIC IDs than a package\n", level);
212 printf("%u > %u\n", caches[level - 1].id_shift, pkg_id_shift);
213 caches[level - 1].id_shift = pkg_id_shift;
215 if (caches[level - 1].id_shift < core_id_shift) {
216 printf("WARNING: L%u data cache covers less "
217 "APIC IDs than a core\n", level);
218 printf("%u < %u\n", caches[level - 1].id_shift, core_id_shift);
219 caches[level - 1].id_shift = core_id_shift;
226 * Determine topology of processing units and caches for AMD CPUs.
228 * - AMD CPUID Specification (Publication # 25481)
229 * - BKDG For AMD Family 10h Processors (Publication # 31116), section 2.15
230 * - BKDG for AMD NPT Family 0Fh Processors (Publication # 32559)
231 * XXX At the moment the code does not recognize grouping of AMD CMT threads,
232 * if supported, into cores, so each thread is treated as being in its own
233 * core. In other words, each logical CPU is considered to be a core.
244 /* No multi-core capability. */
245 if ((amd_feature2 & AMDID2_CMP) == 0)
248 /* For families 10h and newer. */
249 pkg_id_shift = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
250 AMDID_COREID_SIZE_SHIFT;
252 /* For 0Fh family. */
253 if (pkg_id_shift == 0)
255 mask_width((cpu_procinfo2 & AMDID_CMP_CORES) + 1);
257 if ((amd_feature2 & AMDID2_TOPOLOGY) != 0) {
259 cpuid_count(0x8000001d, i, p);
261 level = (p[0] >> 5) & 0x7;
262 share_count = 1 + ((p[0] >> 14) & 0xfff);
264 if (!add_deterministic_cache(type, level, share_count))
268 if (cpu_exthigh >= 0x80000005) {
269 cpuid_count(0x80000005, 0, p);
270 if (((p[2] >> 24) & 0xff) != 0) {
271 caches[0].id_shift = 0;
272 caches[0].present = 1;
275 if (cpu_exthigh >= 0x80000006) {
276 cpuid_count(0x80000006, 0, p);
277 if (((p[2] >> 16) & 0xffff) != 0) {
278 caches[1].id_shift = 0;
279 caches[1].present = 1;
281 if (((p[3] >> 18) & 0x3fff) != 0) {
284 * TODO: Account for dual-node processors
285 * where each node within a package has its own
288 caches[2].id_shift = pkg_id_shift;
289 caches[2].present = 1;
296 * Determine topology of processing units for Intel CPUs
297 * using CPUID Leaf 1 and Leaf 4, if supported.
299 * - Intel 64 Architecture Processor Topology Enumeration
300 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
301 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
302 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
305 topo_probe_intel_0x4(void)
311 /* Both zero and one here mean one logical processor per package. */
312 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
313 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
314 if (max_logical <= 1)
317 if (cpu_high >= 0x4) {
318 cpuid_count(0x04, 0, p);
319 max_cores = ((p[0] >> 26) & 0x3f) + 1;
323 core_id_shift = mask_width(max_logical/max_cores);
324 KASSERT(core_id_shift >= 0,
325 ("intel topo: max_cores > max_logical\n"));
326 pkg_id_shift = core_id_shift + mask_width(max_cores);
330 * Determine topology of processing units for Intel CPUs
331 * using CPUID Leaf 11, if supported.
333 * - Intel 64 Architecture Processor Topology Enumeration
334 * - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
335 * Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
336 * FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
339 topo_probe_intel_0xb(void)
346 /* Fall back if CPU leaf 11 doesn't really exist. */
347 cpuid_count(0x0b, 0, p);
349 topo_probe_intel_0x4();
353 /* We only support three levels for now. */
355 cpuid_count(0x0b, i, p);
358 type = (p[2] >> 8) & 0xff;
363 /* TODO: check for duplicate (re-)assignment */
364 if (type == CPUID_TYPE_SMT)
365 core_id_shift = bits;
366 else if (type == CPUID_TYPE_CORE)
369 printf("unknown CPU level type %d\n", type);
372 if (pkg_id_shift < core_id_shift) {
373 printf("WARNING: core covers more APIC IDs than a package\n");
374 core_id_shift = pkg_id_shift;
379 * Determine topology of caches for Intel CPUs.
381 * - Intel 64 Architecture Processor Topology Enumeration
382 * - Intel 64 and IA-32 Architectures Software Developer’s Manual
383 * Volume 2A: Instruction Set Reference, A-M,
387 topo_probe_intel_caches(void)
395 if (cpu_high < 0x4) {
397 * Available cache level and sizes can be determined
398 * via CPUID leaf 2, but that requires a huge table of hardcoded
399 * values, so for now just assume L1 and L2 caches potentially
400 * shared only by HTT processing units, if HTT is present.
402 caches[0].id_shift = pkg_id_shift;
403 caches[0].present = 1;
404 caches[1].id_shift = pkg_id_shift;
405 caches[1].present = 1;
410 cpuid_count(0x4, i, p);
412 level = (p[0] >> 5) & 0x7;
413 share_count = 1 + ((p[0] >> 14) & 0xfff);
415 if (!add_deterministic_cache(type, level, share_count))
421 * Determine topology of processing units and caches for Intel CPUs.
423 * - Intel 64 Architecture Processor Topology Enumeration
426 topo_probe_intel(void)
430 * Note that 0x1 <= cpu_high < 4 case should be
431 * compatible with topo_probe_intel_0x4() logic when
432 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
433 * or it should trigger the fallback otherwise.
436 topo_probe_intel_0xb();
437 else if (cpu_high >= 0x1)
438 topo_probe_intel_0x4();
440 topo_probe_intel_caches();
444 * Topology information is queried only on BSP, on which this
445 * code runs and for which it can query CPUID information.
446 * Then topology is extrapolated on all packages using an
447 * assumption that APIC ID to hardware component ID mapping is
449 * That doesn't necesserily imply that the topology is uniform.
454 static int cpu_topo_probed = 0;
455 struct x86_topo_layer {
459 } topo_layers[MAX_CACHE_LEVELS + 3];
460 struct topo_node *parent;
461 struct topo_node *node;
470 CPU_ZERO(&logical_cpus_mask);
474 else if (cpu_vendor_id == CPU_VENDOR_AMD)
476 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
479 KASSERT(pkg_id_shift >= core_id_shift,
480 ("bug in APIC topology discovery"));
483 bzero(topo_layers, sizeof(topo_layers));
485 topo_layers[nlayers].type = TOPO_TYPE_PKG;
486 topo_layers[nlayers].id_shift = pkg_id_shift;
488 printf("Package ID shift: %u\n", topo_layers[nlayers].id_shift);
492 * Consider all caches to be within a package/chip
493 * and "in front" of all sub-components like
494 * cores and hardware threads.
496 for (i = MAX_CACHE_LEVELS - 1; i >= 0; --i) {
497 if (caches[i].present) {
498 KASSERT(caches[i].id_shift <= pkg_id_shift,
499 ("bug in APIC topology discovery"));
500 KASSERT(caches[i].id_shift >= core_id_shift,
501 ("bug in APIC topology discovery"));
503 topo_layers[nlayers].type = TOPO_TYPE_CACHE;
504 topo_layers[nlayers].subtype = i + 1;
505 topo_layers[nlayers].id_shift = caches[i].id_shift;
507 printf("L%u cache ID shift: %u\n",
508 topo_layers[nlayers].subtype,
509 topo_layers[nlayers].id_shift);
514 if (pkg_id_shift > core_id_shift) {
515 topo_layers[nlayers].type = TOPO_TYPE_CORE;
516 topo_layers[nlayers].id_shift = core_id_shift;
518 printf("Core ID shift: %u\n",
519 topo_layers[nlayers].id_shift);
523 topo_layers[nlayers].type = TOPO_TYPE_PU;
524 topo_layers[nlayers].id_shift = 0;
527 topo_init_root(&topo_root);
528 for (i = 0; i <= MAX_APIC_ID; ++i) {
529 if (!cpu_info[i].cpu_present)
533 for (layer = 0; layer < nlayers; ++layer) {
534 node_id = i >> topo_layers[layer].id_shift;
535 parent = topo_add_node_by_hwid(parent, node_id,
536 topo_layers[layer].type,
537 topo_layers[layer].subtype);
542 for (layer = 0; layer < nlayers; ++layer) {
543 node_id = boot_cpu_id >> topo_layers[layer].id_shift;
544 node = topo_find_node_by_hwid(parent, node_id,
545 topo_layers[layer].type,
546 topo_layers[layer].subtype);
547 topo_promote_child(node);
555 * Assign logical CPU IDs to local APICs.
560 struct topo_node *node;
563 smt_mask = (1u << core_id_shift) - 1;
566 * Assign CPU IDs to local APIC IDs and disable any CPUs
567 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
570 TOPO_FOREACH(node, &topo_root) {
571 if (node->type != TOPO_TYPE_PU)
574 if ((node->hwid & smt_mask) != (boot_cpu_id & smt_mask))
575 cpu_info[node->hwid].cpu_hyperthread = 1;
577 if (resource_disabled("lapic", node->hwid)) {
578 if (node->hwid != boot_cpu_id)
579 cpu_info[node->hwid].cpu_disabled = 1;
581 printf("Cannot disable BSP, APIC ID = %d\n",
585 if (!hyperthreading_allowed &&
586 cpu_info[node->hwid].cpu_hyperthread)
587 cpu_info[node->hwid].cpu_disabled = 1;
589 if (mp_ncpus >= MAXCPU)
590 cpu_info[node->hwid].cpu_disabled = 1;
592 if (cpu_info[node->hwid].cpu_disabled) {
597 cpu_apic_ids[mp_ncpus] = node->hwid;
598 apic_cpuids[node->hwid] = mp_ncpus;
599 topo_set_pu_id(node, mp_ncpus);
603 KASSERT(mp_maxid >= mp_ncpus - 1,
604 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
609 * Print various information about the SMP system hardware and setup.
612 cpu_mp_announce(void)
614 struct topo_node *node;
615 const char *hyperthread;
620 printf("FreeBSD/SMP: ");
621 if (topo_analyze(&topo_root, 1, &pkg_count,
622 &cores_per_pkg, &thrs_per_core)) {
623 printf("%d package(s)", pkg_count);
624 if (cores_per_pkg > 0)
625 printf(" x %d core(s)", cores_per_pkg);
626 if (thrs_per_core > 1)
627 printf(" x %d hardware threads", thrs_per_core);
629 printf("Non-uniform topology");
634 printf("FreeBSD/SMP Online: ");
635 if (topo_analyze(&topo_root, 0, &pkg_count,
636 &cores_per_pkg, &thrs_per_core)) {
637 printf("%d package(s)", pkg_count);
638 if (cores_per_pkg > 0)
639 printf(" x %d core(s)", cores_per_pkg);
640 if (thrs_per_core > 1)
641 printf(" x %d hardware threads", thrs_per_core);
643 printf("Non-uniform topology");
651 TOPO_FOREACH(node, &topo_root) {
652 switch (node->type) {
654 printf("Package HW ID = %u\n", node->hwid);
657 printf("\tCore HW ID = %u\n", node->hwid);
660 if (cpu_info[node->hwid].cpu_hyperthread)
665 if (node->subtype == 0)
666 printf("\t\tCPU (AP%s): APIC ID: %u"
667 "(disabled)\n", hyperthread, node->hwid);
668 else if (node->id == 0)
669 printf("\t\tCPU0 (BSP): APIC ID: %u\n",
672 printf("\t\tCPU%u (AP%s): APIC ID: %u\n",
673 node->id, hyperthread, node->hwid);
683 * Add a scheduling group, a group of logical processors sharing
684 * a particular cache (and, thus having an affinity), to the scheduling
686 * This function recursively works on lower level caches.
689 x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
691 struct topo_node *node;
696 KASSERT(root->type == TOPO_TYPE_SYSTEM || root->type == TOPO_TYPE_CACHE,
697 ("x86topo_add_sched_group: bad type: %u", root->type));
698 CPU_COPY(&root->cpuset, &cg_root->cg_mask);
699 cg_root->cg_count = root->cpu_count;
700 if (root->type == TOPO_TYPE_SYSTEM)
701 cg_root->cg_level = CG_SHARE_NONE;
703 cg_root->cg_level = root->subtype;
706 * Check how many core nodes we have under the given root node.
707 * If we have multiple logical processors, but not multiple
708 * cores, then those processors must be hardware threads.
712 while (node != NULL) {
713 if (node->type != TOPO_TYPE_CORE) {
714 node = topo_next_node(root, node);
719 node = topo_next_nonchild_node(root, node);
722 if (cg_root->cg_level != CG_SHARE_NONE &&
723 root->cpu_count > 1 && ncores < 2)
724 cg_root->cg_flags = CG_FLAG_SMT;
727 * Find out how many cache nodes we have under the given root node.
728 * We ignore cache nodes that cover all the same processors as the
729 * root node. Also, we do not descend below found cache nodes.
730 * That is, we count top-level "non-redundant" caches under the root
735 while (node != NULL) {
736 if (node->type != TOPO_TYPE_CACHE ||
737 (root->type != TOPO_TYPE_SYSTEM &&
738 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
739 node = topo_next_node(root, node);
743 node = topo_next_nonchild_node(root, node);
746 cg_root->cg_child = smp_topo_alloc(nchildren);
747 cg_root->cg_children = nchildren;
750 * Now find again the same cache nodes as above and recursively
751 * build scheduling topologies for them.
755 while (node != NULL) {
756 if (node->type != TOPO_TYPE_CACHE ||
757 (root->type != TOPO_TYPE_SYSTEM &&
758 CPU_CMP(&node->cpuset, &root->cpuset) == 0)) {
759 node = topo_next_node(root, node);
762 cg_root->cg_child[i].cg_parent = cg_root;
763 x86topo_add_sched_group(node, &cg_root->cg_child[i]);
765 node = topo_next_nonchild_node(root, node);
770 * Build the MI scheduling topology from the discovered hardware topology.
775 struct cpu_group *cg_root;
778 return (smp_topo_none());
780 cg_root = smp_topo_alloc(1);
781 x86topo_add_sched_group(&topo_root, cg_root);
787 * Add a logical CPU to the topology.
790 cpu_add(u_int apic_id, char boot_cpu)
793 if (apic_id > MAX_APIC_ID) {
794 panic("SMP: APIC ID %d too high", apic_id);
797 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
799 cpu_info[apic_id].cpu_present = 1;
801 KASSERT(boot_cpu_id == -1,
802 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
804 boot_cpu_id = apic_id;
805 cpu_info[apic_id].cpu_bsp = 1;
807 if (mp_ncpus < MAXCPU) {
809 mp_maxid = mp_ncpus - 1;
812 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
817 cpu_mp_setmaxid(void)
821 * mp_ncpus and mp_maxid should be already set by calls to cpu_add().
822 * If there were no calls to cpu_add() assume this is a UP system.
833 * Always record BSP in CPU map so that the mbuf init code works
836 CPU_SETOF(0, &all_cpus);
837 return (mp_ncpus > 1);
841 * AP CPU's call this to initialize themselves.
844 init_secondary_tail(void)
849 * On real hardware, switch to x2apic mode if possible. Do it
850 * after aps_ready was signalled, to avoid manipulating the
851 * mode while BSP might still want to send some IPI to us
852 * (second startup IPI is ignored on modern hardware etc).
856 /* Initialize the PAT MSR. */
859 /* set up CPU registers and state */
865 /* set up FPU state on the AP */
872 if (cpu_ops.cpu_init)
875 /* A quick check from sanity claus */
876 cpuid = PCPU_GET(cpuid);
877 if (PCPU_GET(apic_id) != lapic_id()) {
878 printf("SMP: cpuid = %d\n", cpuid);
879 printf("SMP: actual apic_id = %d\n", lapic_id());
880 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
881 panic("cpuid mismatch! boom!!");
884 /* Initialize curthread. */
885 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
886 PCPU_SET(curthread, PCPU_GET(idlethread));
890 mtx_lock_spin(&ap_boot_mtx);
892 /* Init local apic for irq's */
895 /* Set memory range attributes for this CPU to match the BSP */
900 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
901 printf("SMP: AP CPU #%d Launched!\n", cpuid);
903 /* Determine if we are a logical CPU. */
904 if (cpu_info[PCPU_GET(apic_id)].cpu_hyperthread)
905 CPU_SET(cpuid, &logical_cpus_mask);
910 if (smp_cpus == mp_ncpus) {
911 /* enable IPI's, tlb shootdown, freezes etc */
912 atomic_store_rel_int(&smp_started, 1);
917 * Enable global pages TLB extension
918 * This also implicitly flushes the TLB
920 load_cr4(rcr4() | CR4_PGE);
921 if (pmap_pcid_enabled)
922 load_cr4(rcr4() | CR4_PCIDE);
928 mtx_unlock_spin(&ap_boot_mtx);
930 /* Wait until all the AP's are up. */
931 while (atomic_load_acq_int(&smp_started) == 0)
934 #ifndef EARLY_AP_STARTUP
935 /* Start per-CPU event timers. */
941 panic("scheduler returned us to %s", __func__);
945 /*******************************************************************
946 * local functions and data
950 * We tell the I/O APIC code about all the CPUs we want to receive
951 * interrupts. If we don't want certain CPUs to receive IRQs we
952 * can simply not tell the I/O APIC code about them in this function.
953 * We also do not tell it about the BSP since it tells itself about
954 * the BSP internally to work with UP kernels and on UP machines.
957 set_interrupt_apic_ids(void)
961 for (i = 0; i < MAXCPU; i++) {
962 apic_id = cpu_apic_ids[i];
965 if (cpu_info[apic_id].cpu_bsp)
967 if (cpu_info[apic_id].cpu_disabled)
970 /* Don't let hyperthreads service interrupts. */
971 if (cpu_info[apic_id].cpu_hyperthread)
979 #ifdef COUNT_XINVLTLB_HITS
980 u_int xhits_gbl[MAXCPU];
981 u_int xhits_pg[MAXCPU];
982 u_int xhits_rng[MAXCPU];
983 static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
984 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
985 sizeof(xhits_gbl), "IU", "");
986 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
987 sizeof(xhits_pg), "IU", "");
988 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
989 sizeof(xhits_rng), "IU", "");
994 u_int ipi_range_size;
995 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
996 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
997 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
998 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1000 #endif /* COUNT_XINVLTLB_HITS */
1003 * Init and startup IPI.
1006 ipi_startup(int apic_id, int vector)
1010 * This attempts to follow the algorithm described in the
1011 * Intel Multiprocessor Specification v1.4 in section B.4.
1012 * For each IPI, we allow the local APIC ~20us to deliver the
1013 * IPI. If that times out, we panic.
1017 * first we do an INIT IPI: this INIT IPI might be run, resetting
1018 * and running the target CPU. OR this INIT IPI might be latched (P5
1019 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1022 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1023 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1024 lapic_ipi_wait(100);
1026 /* Explicitly deassert the INIT IPI. */
1027 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1028 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT,
1031 DELAY(10000); /* wait ~10mS */
1034 * next we do a STARTUP IPI: the previous INIT IPI might still be
1035 * latched, (P5 bug) this 1st STARTUP would then terminate
1036 * immediately, and the previously started INIT IPI would continue. OR
1037 * the previous INIT IPI has already run. and this STARTUP IPI will
1038 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1041 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1042 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1044 if (!lapic_ipi_wait(100))
1045 panic("Failed to deliver first STARTUP IPI to APIC %d",
1047 DELAY(200); /* wait ~200uS */
1050 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1051 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1052 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1053 * recognized after hardware RESET or INIT IPI.
1055 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1056 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1058 if (!lapic_ipi_wait(100))
1059 panic("Failed to deliver second STARTUP IPI to APIC %d",
1062 DELAY(200); /* wait ~200uS */
1066 * Send an IPI to specified CPU handling the bitmap logic.
1069 ipi_send_cpu(int cpu, u_int ipi)
1071 u_int bitmap, old_pending, new_pending;
1073 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1075 if (IPI_IS_BITMAPED(ipi)) {
1077 ipi = IPI_BITMAP_VECTOR;
1079 old_pending = cpu_ipi_pending[cpu];
1080 new_pending = old_pending | bitmap;
1081 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1082 old_pending, new_pending));
1086 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1090 ipi_bitmap_handler(struct trapframe frame)
1092 struct trapframe *oldframe;
1094 int cpu = PCPU_GET(cpuid);
1099 td->td_intr_nesting_level++;
1100 oldframe = td->td_intr_frame;
1101 td->td_intr_frame = &frame;
1102 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1103 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1105 (*ipi_preempt_counts[cpu])++;
1109 if (ipi_bitmap & (1 << IPI_AST)) {
1111 (*ipi_ast_counts[cpu])++;
1113 /* Nothing to do for AST */
1115 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1117 (*ipi_hardclock_counts[cpu])++;
1121 td->td_intr_frame = oldframe;
1122 td->td_intr_nesting_level--;
1127 * send an IPI to a set of cpus.
1130 ipi_selected(cpuset_t cpus, u_int ipi)
1135 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1136 * of help in order to understand what is the source.
1137 * Set the mask of receiving CPUs for this purpose.
1139 if (ipi == IPI_STOP_HARD)
1140 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &cpus);
1142 while ((cpu = CPU_FFS(&cpus)) != 0) {
1144 CPU_CLR(cpu, &cpus);
1145 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1146 ipi_send_cpu(cpu, ipi);
1151 * send an IPI to a specific CPU.
1154 ipi_cpu(int cpu, u_int ipi)
1158 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1159 * of help in order to understand what is the source.
1160 * Set the mask of receiving CPUs for this purpose.
1162 if (ipi == IPI_STOP_HARD)
1163 CPU_SET_ATOMIC(cpu, &ipi_stop_nmi_pending);
1165 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1166 ipi_send_cpu(cpu, ipi);
1170 * send an IPI to all CPUs EXCEPT myself
1173 ipi_all_but_self(u_int ipi)
1175 cpuset_t other_cpus;
1177 other_cpus = all_cpus;
1178 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1179 if (IPI_IS_BITMAPED(ipi)) {
1180 ipi_selected(other_cpus, ipi);
1185 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1186 * of help in order to understand what is the source.
1187 * Set the mask of receiving CPUs for this purpose.
1189 if (ipi == IPI_STOP_HARD)
1190 CPU_OR_ATOMIC(&ipi_stop_nmi_pending, &other_cpus);
1192 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1193 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1197 ipi_nmi_handler(void)
1202 * As long as there is not a simple way to know about a NMI's
1203 * source, if the bitmask for the current CPU is present in
1204 * the global pending bitword an IPI_STOP_HARD has been issued
1205 * and should be handled.
1207 cpuid = PCPU_GET(cpuid);
1208 if (!CPU_ISSET(cpuid, &ipi_stop_nmi_pending))
1211 CPU_CLR_ATOMIC(cpuid, &ipi_stop_nmi_pending);
1220 nmi_call_kdb_smp(u_int type, struct trapframe *frame)
1225 cpu = PCPU_GET(cpuid);
1226 if (atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1)) {
1227 nmi_call_kdb(cpu, type, frame);
1230 savectx(&stoppcbs[cpu]);
1231 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1232 while (!atomic_cmpset_acq_int(&nmi_kdb_lock, 0, 1))
1236 atomic_store_rel_int(&nmi_kdb_lock, 0);
1238 cpustop_handler_post(cpu);
1243 * Handle an IPI_STOP by saving our current context and spinning until we
1247 cpustop_handler(void)
1251 cpu = PCPU_GET(cpuid);
1253 savectx(&stoppcbs[cpu]);
1255 /* Indicate that we are stopped */
1256 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1258 /* Wait for restart */
1259 while (!CPU_ISSET(cpu, &started_cpus))
1262 cpustop_handler_post(cpu);
1266 cpustop_handler_post(u_int cpu)
1269 CPU_CLR_ATOMIC(cpu, &started_cpus);
1270 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1272 #if defined(__amd64__) && defined(DDB)
1273 amd64_db_resume_dbreg();
1276 if (cpu == 0 && cpustop_restartfunc != NULL) {
1277 cpustop_restartfunc();
1278 cpustop_restartfunc = NULL;
1283 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1287 cpususpend_handler(void)
1291 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED);
1293 cpu = PCPU_GET(cpuid);
1294 if (savectx(&susppcbs[cpu]->sp_pcb)) {
1296 fpususpend(susppcbs[cpu]->sp_fpususpend);
1298 npxsuspend(susppcbs[cpu]->sp_fpususpend);
1301 CPU_SET_ATOMIC(cpu, &suspended_cpus);
1304 fpuresume(susppcbs[cpu]->sp_fpususpend);
1306 npxresume(susppcbs[cpu]->sp_fpususpend);
1310 PCPU_SET(switchtime, 0);
1311 PCPU_SET(switchticks, ticks);
1313 /* Indicate that we are resumed */
1314 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1317 /* Wait for resume */
1318 while (!CPU_ISSET(cpu, &started_cpus))
1321 if (cpu_ops.cpu_resume)
1322 cpu_ops.cpu_resume();
1328 /* Resume MCA and local APIC */
1333 /* Indicate that we are resumed */
1334 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1335 CPU_CLR_ATOMIC(cpu, &started_cpus);
1340 invlcache_handler(void)
1342 uint32_t generation;
1345 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
1346 #endif /* COUNT_IPIS */
1349 * Reading the generation here allows greater parallelism
1350 * since wbinvd is a serializing instruction. Without the
1351 * temporary, we'd wait for wbinvd to complete, then the read
1352 * would execute, then the dependent write, which must then
1353 * complete before return from interrupt.
1355 generation = smp_tlb_generation;
1357 PCPU_SET(smp_tlb_done, generation);
1361 * This is called once the rest of the system is up and running and we're
1362 * ready to let the AP's out of the pen.
1365 release_aps(void *dummy __unused)
1370 atomic_store_rel_int(&aps_ready, 1);
1371 while (smp_started == 0)
1374 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1378 * Setup interrupt counters for IPI handlers.
1381 mp_ipi_intrcnt(void *dummy)
1387 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1388 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1389 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1390 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1391 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1392 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1393 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
1394 intrcnt_add(buf, &ipi_invlcache_counts[i]);
1395 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1396 intrcnt_add(buf, &ipi_preempt_counts[i]);
1397 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1398 intrcnt_add(buf, &ipi_ast_counts[i]);
1399 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1400 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1401 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1402 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1405 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
1409 * Flush the TLB on other CPU's
1412 /* Variables needed for SMP tlb shootdown. */
1413 static vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
1414 pmap_t smp_tlb_pmap;
1415 volatile uint32_t smp_tlb_generation;
1418 #define read_eflags() read_rflags()
1422 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
1423 vm_offset_t addr1, vm_offset_t addr2)
1425 cpuset_t other_cpus;
1426 volatile uint32_t *p_cpudone;
1427 uint32_t generation;
1431 * Check for other cpus. Return if none.
1433 if (CPU_ISFULLSET(&mask)) {
1437 CPU_CLR(PCPU_GET(cpuid), &mask);
1438 if (CPU_EMPTY(&mask))
1442 if (!(read_eflags() & PSL_I))
1443 panic("%s: interrupts disabled", __func__);
1444 mtx_lock_spin(&smp_ipi_mtx);
1445 smp_tlb_addr1 = addr1;
1446 smp_tlb_addr2 = addr2;
1447 smp_tlb_pmap = pmap;
1448 generation = ++smp_tlb_generation;
1449 if (CPU_ISFULLSET(&mask)) {
1450 ipi_all_but_self(vector);
1451 other_cpus = all_cpus;
1452 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1455 while ((cpu = CPU_FFS(&mask)) != 0) {
1457 CPU_CLR(cpu, &mask);
1458 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
1460 ipi_send_cpu(cpu, vector);
1463 while ((cpu = CPU_FFS(&other_cpus)) != 0) {
1465 CPU_CLR(cpu, &other_cpus);
1466 p_cpudone = &cpuid_to_pcpu[cpu]->pc_smp_tlb_done;
1467 while (*p_cpudone != generation)
1470 mtx_unlock_spin(&smp_ipi_mtx);
1474 smp_masked_invltlb(cpuset_t mask, pmap_t pmap)
1478 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0);
1479 #ifdef COUNT_XINVLTLB_HITS
1486 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
1490 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, NULL, addr, 0);
1491 #ifdef COUNT_XINVLTLB_HITS
1498 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
1502 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, NULL,
1504 #ifdef COUNT_XINVLTLB_HITS
1506 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1512 smp_cache_flush(void)
1516 smp_targeted_tlb_shootdown(all_cpus, IPI_INVLCACHE, NULL,
1522 * Handlers for TLB related IPIs
1525 invltlb_handler(void)
1527 uint32_t generation;
1529 #ifdef COUNT_XINVLTLB_HITS
1530 xhits_gbl[PCPU_GET(cpuid)]++;
1531 #endif /* COUNT_XINVLTLB_HITS */
1533 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1534 #endif /* COUNT_IPIS */
1537 * Reading the generation here allows greater parallelism
1538 * since invalidating the TLB is a serializing operation.
1540 generation = smp_tlb_generation;
1541 if (smp_tlb_pmap == kernel_pmap)
1545 PCPU_SET(smp_tlb_done, generation);
1549 invlpg_handler(void)
1551 uint32_t generation;
1553 #ifdef COUNT_XINVLTLB_HITS
1554 xhits_pg[PCPU_GET(cpuid)]++;
1555 #endif /* COUNT_XINVLTLB_HITS */
1557 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1558 #endif /* COUNT_IPIS */
1560 generation = smp_tlb_generation; /* Overlap with serialization */
1561 invlpg(smp_tlb_addr1);
1562 PCPU_SET(smp_tlb_done, generation);
1566 invlrng_handler(void)
1568 vm_offset_t addr, addr2;
1569 uint32_t generation;
1571 #ifdef COUNT_XINVLTLB_HITS
1572 xhits_rng[PCPU_GET(cpuid)]++;
1573 #endif /* COUNT_XINVLTLB_HITS */
1575 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
1576 #endif /* COUNT_IPIS */
1578 addr = smp_tlb_addr1;
1579 addr2 = smp_tlb_addr2;
1580 generation = smp_tlb_generation; /* Overlap with serialization */
1584 } while (addr < addr2);
1586 PCPU_SET(smp_tlb_done, generation);