sys/x86/x86/tsc.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 1998-2003 Poul-Henning Kamp
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include "opt_clock.h"
  33
  34 #include <sys/param.h>
  35 #include <sys/bus.h>
  36 #include <sys/cpu.h>
  37 #include <sys/eventhandler.h>
  38 #include <sys/limits.h>
  39 #include <sys/malloc.h>
  40 #include <sys/systm.h>
  41 #include <sys/sysctl.h>
  42 #include <sys/time.h>
  43 #include <sys/timetc.h>
  44 #include <sys/kernel.h>
  45 #include <sys/power.h>
  46 #include <sys/smp.h>
  47 #include <sys/vdso.h>
  48 #include <machine/clock.h>
  49 #include <machine/cputypes.h>
  50 #include <machine/md_var.h>
  51 #include <machine/specialreg.h>
  52 #include <x86/vmware.h>
  53 #include <dev/acpica/acpi_hpet.h>
  54 #include <contrib/dev/acpica/include/acpi.h>
  55
  56 #include "cpufreq_if.h"
  57
  58 uint64_t        tsc_freq;
  59 int             tsc_is_invariant;
  60 int             tsc_perf_stat;
  61
  62 static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag;
  63
  64 SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN,
  65     &tsc_is_invariant, 0, "Indicates whether the TSC is P-state invariant");
  66
  67 #ifdef SMP
  68 int     smp_tsc;
  69 SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc, CTLFLAG_RDTUN, &smp_tsc, 0,
  70     "Indicates whether the TSC is safe to use in SMP mode");
  71
  72 int     smp_tsc_adjust = 0;
  73 SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc_adjust, CTLFLAG_RDTUN,
  74     &smp_tsc_adjust, 0, "Try to adjust TSC on APs to match BSP");
  75 #endif
  76
  77 static int      tsc_shift = 1;
  78 SYSCTL_INT(_kern_timecounter, OID_AUTO, tsc_shift, CTLFLAG_RDTUN,
  79     &tsc_shift, 0, "Shift to pre-apply for the maximum TSC frequency");
  80
  81 static int      tsc_disabled;
  82 SYSCTL_INT(_machdep, OID_AUTO, disable_tsc, CTLFLAG_RDTUN, &tsc_disabled, 0,
  83     "Disable x86 Time Stamp Counter");
  84
  85 static int      tsc_skip_calibration;
  86 SYSCTL_INT(_machdep, OID_AUTO, disable_tsc_calibration, CTLFLAG_RDTUN |
  87     CTLFLAG_NOFETCH, &tsc_skip_calibration, 0,
  88     "Disable TSC frequency calibration");
  89
  90 static void tsc_freq_changed(void *arg, const struct cf_level *level,
  91     int status);
  92 static void tsc_freq_changing(void *arg, const struct cf_level *level,
  93     int *status);
  94 static unsigned tsc_get_timecount(struct timecounter *tc);
  95 static inline unsigned tsc_get_timecount_low(struct timecounter *tc);
  96 static unsigned tsc_get_timecount_lfence(struct timecounter *tc);
  97 static unsigned tsc_get_timecount_low_lfence(struct timecounter *tc);
  98 static unsigned tsc_get_timecount_mfence(struct timecounter *tc);
  99 static unsigned tsc_get_timecount_low_mfence(struct timecounter *tc);
 100 static void tsc_levels_changed(void *arg, int unit);
 101 static uint32_t x86_tsc_vdso_timehands(struct vdso_timehands *vdso_th,
 102     struct timecounter *tc);
 103 #ifdef COMPAT_FREEBSD32
 104 static uint32_t x86_tsc_vdso_timehands32(struct vdso_timehands32 *vdso_th32,
 105     struct timecounter *tc);
 106 #endif
 107
 108 static struct timecounter tsc_timecounter = {
 109         .tc_get_timecount =             tsc_get_timecount,
 110         .tc_counter_mask =              ~0u,
 111         .tc_name =                      "TSC",
 112         .tc_quality =                   800,    /* adjusted in code */
 113         .tc_fill_vdso_timehands =       x86_tsc_vdso_timehands,
 114 #ifdef COMPAT_FREEBSD32
 115         .tc_fill_vdso_timehands32 =     x86_tsc_vdso_timehands32,
 116 #endif
 117 };
 118
 119 static void
 120 tsc_freq_vmware(void)
 121 {
 122         u_int regs[4];
 123
 124         if (hv_high >= 0x40000010) {
 125                 do_cpuid(0x40000010, regs);
 126                 tsc_freq = regs[0] * 1000;
 127         } else {
 128                 vmware_hvcall(VMW_HVCMD_GETHZ, regs);
 129                 if (regs[1] != UINT_MAX)
 130                         tsc_freq = regs[0] | ((uint64_t)regs[1] << 32);
 131         }
 132         tsc_is_invariant = 1;
 133 }
 134
 135 /*
 136  * Calculate TSC frequency using information from the CPUID leaf 0x15
 137  * 'Time Stamp Counter and Nominal Core Crystal Clock'.  If leaf 0x15
 138  * is not functional, as it is on Skylake/Kabylake, try 0x16 'Processor
 139  * Frequency Information'.  Leaf 0x16 is described in the SDM as
 140  * informational only, but if 0x15 did not work, and TSC calibration
 141  * is disabled, it is the best we can get at all.  It should still be
 142  * an improvement over the parsing of the CPU model name in
 143  * tsc_freq_intel(), when available.
 144  */
 145 static bool
 146 tsc_freq_cpuid(void)
 147 {
 148         u_int regs[4];
 149
 150         if (cpu_high < 0x15)
 151                 return (false);
 152         do_cpuid(0x15, regs);
 153         if (regs[0] != 0 && regs[1] != 0 && regs[2] != 0) {
 154                 tsc_freq = (uint64_t)regs[2] * regs[1] / regs[0];
 155                 return (true);
 156         }
 157
 158         if (cpu_high < 0x16)
 159                 return (false);
 160         do_cpuid(0x16, regs);
 161         if (regs[0] != 0) {
 162                 tsc_freq = (uint64_t)regs[0] * 1000000;
 163                 return (true);
 164         }
 165
 166         return (false);
 167 }
 168
 169 static void
 170 tsc_freq_intel(void)
 171 {
 172         char brand[48];
 173         u_int regs[4];
 174         uint64_t freq;
 175         char *p;
 176         u_int i;
 177
 178         /*
 179          * Intel Processor Identification and the CPUID Instruction
 180          * Application Note 485.
 181          * http://www.intel.com/assets/pdf/appnote/241618.pdf
 182          */
 183         if (cpu_exthigh >= 0x80000004) {
 184                 p = brand;
 185                 for (i = 0x80000002; i < 0x80000005; i++) {
 186                         do_cpuid(i, regs);
 187                         memcpy(p, regs, sizeof(regs));
 188                         p += sizeof(regs);
 189                 }
 190                 p = NULL;
 191                 for (i = 0; i < sizeof(brand) - 1; i++)
 192                         if (brand[i] == 'H' && brand[i + 1] == 'z')
 193                                 p = brand + i;
 194                 if (p != NULL) {
 195                         p -= 5;
 196                         switch (p[4]) {
 197                         case 'M':
 198                                 i = 1;
 199                                 break;
 200                         case 'G':
 201                                 i = 1000;
 202                                 break;
 203                         case 'T':
 204                                 i = 1000000;
 205                                 break;
 206                         default:
 207                                 return;
 208                         }
 209 #define C2D(c)  ((c) - '0')
 210                         if (p[1] == '.') {
 211                                 freq = C2D(p[0]) * 1000;
 212                                 freq += C2D(p[2]) * 100;
 213                                 freq += C2D(p[3]) * 10;
 214                                 freq *= i * 1000;
 215                         } else {
 216                                 freq = C2D(p[0]) * 1000;
 217                                 freq += C2D(p[1]) * 100;
 218                                 freq += C2D(p[2]) * 10;
 219                                 freq += C2D(p[3]);
 220                                 freq *= i * 1000000;
 221                         }
 222 #undef C2D
 223                         tsc_freq = freq;
 224                 }
 225         }
 226 }
 227
 228 static void
 229 probe_tsc_freq(void)
 230 {
 231         uint64_t tsc1, tsc2;
 232         uint16_t bootflags;
 233
 234         if (cpu_power_ecx & CPUID_PERF_STAT) {
 235                 /*
 236                  * XXX Some emulators expose host CPUID without actual support
 237                  * for these MSRs.  We must test whether they really work.
 238                  */
 239                 wrmsr(MSR_MPERF, 0);
 240                 wrmsr(MSR_APERF, 0);
 241                 DELAY(10);
 242                 if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0)
 243                         tsc_perf_stat = 1;
 244         }
 245
 246         if (vm_guest == VM_GUEST_VMWARE) {
 247                 tsc_freq_vmware();
 248                 return;
 249         }
 250
 251         switch (cpu_vendor_id) {
 252         case CPU_VENDOR_AMD:
 253         case CPU_VENDOR_HYGON:
 254                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
 255                     (vm_guest == VM_GUEST_NO &&
 256                     CPUID_TO_FAMILY(cpu_id) >= 0x10))
 257                         tsc_is_invariant = 1;
 258                 if (cpu_feature & CPUID_SSE2) {
 259                         tsc_timecounter.tc_get_timecount =
 260                             tsc_get_timecount_mfence;
 261                 }
 262                 break;
 263         case CPU_VENDOR_INTEL:
 264                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
 265                     (vm_guest == VM_GUEST_NO &&
 266                     ((CPUID_TO_FAMILY(cpu_id) == 0x6 &&
 267                     CPUID_TO_MODEL(cpu_id) >= 0xe) ||
 268                     (CPUID_TO_FAMILY(cpu_id) == 0xf &&
 269                     CPUID_TO_MODEL(cpu_id) >= 0x3))))
 270                         tsc_is_invariant = 1;
 271                 if (cpu_feature & CPUID_SSE2) {
 272                         tsc_timecounter.tc_get_timecount =
 273                             tsc_get_timecount_lfence;
 274                 }
 275                 break;
 276         case CPU_VENDOR_CENTAUR:
 277                 if (vm_guest == VM_GUEST_NO &&
 278                     CPUID_TO_FAMILY(cpu_id) == 0x6 &&
 279                     CPUID_TO_MODEL(cpu_id) >= 0xf &&
 280                     (rdmsr(0x1203) & 0x100000000ULL) == 0)
 281                         tsc_is_invariant = 1;
 282                 if (cpu_feature & CPUID_SSE2) {
 283                         tsc_timecounter.tc_get_timecount =
 284                             tsc_get_timecount_lfence;
 285                 }
 286                 break;
 287         }
 288
 289         if (!TUNABLE_INT_FETCH("machdep.disable_tsc_calibration",
 290             &tsc_skip_calibration)) {
 291                 /*
 292                  * User did not give the order about calibration.
 293                  * If he did, we do not try to guess.
 294                  *
 295                  * Otherwise, if ACPI FADT reports that the platform
 296                  * is legacy-free and CPUID provides TSC frequency,
 297                  * use it.  The calibration could fail anyway since
 298                  * ISA timer can be absent or power gated.
 299                  */
 300                 if (acpi_get_fadt_bootflags(&bootflags) &&
 301                     (bootflags & ACPI_FADT_LEGACY_DEVICES) == 0 &&
 302                     tsc_freq_cpuid()) {
 303                         printf("Skipping TSC calibration since no legacy "
 304                             "devices reported by FADT and CPUID works\n");
 305                         tsc_skip_calibration = 1;
 306                 }
 307         }
 308         if (tsc_skip_calibration) {
 309                 if (tsc_freq_cpuid())
 310                         ;
 311                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
 312                         tsc_freq_intel();
 313         } else {
 314                 if (bootverbose)
 315                         printf("Calibrating TSC clock ... ");
 316                 tsc1 = rdtsc();
 317                 DELAY(1000000);
 318                 tsc2 = rdtsc();
 319                 tsc_freq = tsc2 - tsc1;
 320         }
 321         if (bootverbose)
 322                 printf("TSC clock: %ju Hz\n", (intmax_t)tsc_freq);
 323 }
 324
 325 void
 326 init_TSC(void)
 327 {
 328
 329         if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled)
 330                 return;
 331
 332 #ifdef __i386__
 333         /* The TSC is known to be broken on certain CPUs. */
 334         switch (cpu_vendor_id) {
 335         case CPU_VENDOR_AMD:
 336                 switch (cpu_id & 0xFF0) {
 337                 case 0x500:
 338                         /* K5 Model 0 */
 339                         return;
 340                 }
 341                 break;
 342         case CPU_VENDOR_CENTAUR:
 343                 switch (cpu_id & 0xff0) {
 344                 case 0x540:
 345                         /*
 346                          * http://www.centtech.com/c6_data_sheet.pdf
 347                          *
 348                          * I-12 RDTSC may return incoherent values in EDX:EAX
 349                          * I-13 RDTSC hangs when certain event counters are used
 350                          */
 351                         return;
 352                 }
 353                 break;
 354         case CPU_VENDOR_NSC:
 355                 switch (cpu_id & 0xff0) {
 356                 case 0x540:
 357                         if ((cpu_id & CPUID_STEPPING) == 0)
 358                                 return;
 359                         break;
 360                 }
 361                 break;
 362         }
 363 #endif
 364
 365         probe_tsc_freq();
 366
 367         /*
 368          * Inform CPU accounting about our boot-time clock rate.  This will
 369          * be updated if someone loads a cpufreq driver after boot that
 370          * discovers a new max frequency.
 371          */
 372         if (tsc_freq != 0)
 373                 set_cputicker(rdtsc, tsc_freq, !tsc_is_invariant);
 374
 375         if (tsc_is_invariant)
 376                 return;
 377
 378         /* Register to find out about changes in CPU frequency. */
 379         tsc_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change,
 380             tsc_freq_changing, NULL, EVENTHANDLER_PRI_FIRST);
 381         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
 382             tsc_freq_changed, NULL, EVENTHANDLER_PRI_FIRST);
 383         tsc_levels_tag = EVENTHANDLER_REGISTER(cpufreq_levels_changed,
 384             tsc_levels_changed, NULL, EVENTHANDLER_PRI_ANY);
 385 }
 386
 387 #ifdef SMP
 388
 389 /*
 390  * RDTSC is not a serializing instruction, and does not drain
 391  * instruction stream, so we need to drain the stream before executing
 392  * it.  It could be fixed by use of RDTSCP, except the instruction is
 393  * not available everywhere.
 394  *
 395  * Use CPUID for draining in the boot-time SMP constistency test.  The
 396  * timecounters use MFENCE for AMD CPUs, and LFENCE for others (Intel
 397  * and VIA) when SSE2 is present, and nothing on older machines which
 398  * also do not issue RDTSC prematurely.  There, testing for SSE2 and
 399  * vendor is too cumbersome, and we learn about TSC presence from CPUID.
 400  *
 401  * Do not use do_cpuid(), since we do not need CPUID results, which
 402  * have to be written into memory with do_cpuid().
 403  */
 404 #define TSC_READ(x)                                                     \
 405 static void                                                             \
 406 tsc_read_##x(void *arg)                                                 \
 407 {                                                                       \
 408         uint64_t *tsc = arg;                                            \
 409         u_int cpu = PCPU_GET(cpuid);                                    \
 410                                                                         \
 411         __asm __volatile("cpuid" : : : "eax", "ebx", "ecx", "edx");     \
 412         tsc[cpu * 3 + x] = rdtsc();                                     \
 413 }
 414 TSC_READ(0)
 415 TSC_READ(1)
 416 TSC_READ(2)
 417 #undef TSC_READ
 418
 419 #define N       1000
 420
 421 static void
 422 comp_smp_tsc(void *arg)
 423 {
 424         uint64_t *tsc;
 425         int64_t d1, d2;
 426         u_int cpu = PCPU_GET(cpuid);
 427         u_int i, j, size;
 428
 429         size = (mp_maxid + 1) * 3;
 430         for (i = 0, tsc = arg; i < N; i++, tsc += size)
 431                 CPU_FOREACH(j) {
 432                         if (j == cpu)
 433                                 continue;
 434                         d1 = tsc[cpu * 3 + 1] - tsc[j * 3];
 435                         d2 = tsc[cpu * 3 + 2] - tsc[j * 3 + 1];
 436                         if (d1 <= 0 || d2 <= 0) {
 437                                 smp_tsc = 0;
 438                                 return;
 439                         }
 440                 }
 441 }
 442
 443 static void
 444 adj_smp_tsc(void *arg)
 445 {
 446         uint64_t *tsc;
 447         int64_t d, min, max;
 448         u_int cpu = PCPU_GET(cpuid);
 449         u_int first, i, size;
 450
 451         first = CPU_FIRST();
 452         if (cpu == first)
 453                 return;
 454         min = INT64_MIN;
 455         max = INT64_MAX;
 456         size = (mp_maxid + 1) * 3;
 457         for (i = 0, tsc = arg; i < N; i++, tsc += size) {
 458                 d = tsc[first * 3] - tsc[cpu * 3 + 1];
 459                 if (d > min)
 460                         min = d;
 461                 d = tsc[first * 3 + 1] - tsc[cpu * 3 + 2];
 462                 if (d > min)
 463                         min = d;
 464                 d = tsc[first * 3 + 1] - tsc[cpu * 3];
 465                 if (d < max)
 466                         max = d;
 467                 d = tsc[first * 3 + 2] - tsc[cpu * 3 + 1];
 468                 if (d < max)
 469                         max = d;
 470         }
 471         if (min > max)
 472                 return;
 473         d = min / 2 + max / 2;
 474         __asm __volatile (
 475                 "movl $0x10, %%ecx\n\t"
 476                 "rdmsr\n\t"
 477                 "addl %%edi, %%eax\n\t"
 478                 "adcl %%esi, %%edx\n\t"
 479                 "wrmsr\n"
 480                 : /* No output */
 481                 : "D" ((uint32_t)d), "S" ((uint32_t)(d >> 32))
 482                 : "ax", "cx", "dx", "cc"
 483         );
 484 }
 485
 486 static int
 487 test_tsc(int adj_max_count)
 488 {
 489         uint64_t *data, *tsc;
 490         u_int i, size, adj;
 491
 492         if ((!smp_tsc && !tsc_is_invariant) || vm_guest)
 493                 return (-100);
 494         size = (mp_maxid + 1) * 3;
 495         data = malloc(sizeof(*data) * size * N, M_TEMP, M_WAITOK);
 496         adj = 0;
 497 retry:
 498         for (i = 0, tsc = data; i < N; i++, tsc += size)
 499                 smp_rendezvous(tsc_read_0, tsc_read_1, tsc_read_2, tsc);
 500         smp_tsc = 1;    /* XXX */
 501         smp_rendezvous(smp_no_rendezvous_barrier, comp_smp_tsc,
 502             smp_no_rendezvous_barrier, data);
 503         if (!smp_tsc && adj < adj_max_count) {
 504                 adj++;
 505                 smp_rendezvous(smp_no_rendezvous_barrier, adj_smp_tsc,
 506                     smp_no_rendezvous_barrier, data);
 507                 goto retry;
 508         }
 509         free(data, M_TEMP);
 510         if (bootverbose)
 511                 printf("SMP: %sed TSC synchronization test%s\n",
 512                     smp_tsc ? "pass" : "fail",
 513                     adj > 0 ? " after adjustment" : "");
 514         if (smp_tsc && tsc_is_invariant) {
 515                 switch (cpu_vendor_id) {
 516                 case CPU_VENDOR_AMD:
 517                 case CPU_VENDOR_HYGON:
 518                         /*
 519                          * Starting with Family 15h processors, TSC clock
 520                          * source is in the north bridge.  Check whether
 521                          * we have a single-socket/multi-core platform.
 522                          * XXX Need more work for complex cases.
 523                          */
 524                         if (CPUID_TO_FAMILY(cpu_id) < 0x15 ||
 525                             (amd_feature2 & AMDID2_CMP) == 0 ||
 526                             smp_cpus > (cpu_procinfo2 & AMDID_CMP_CORES) + 1)
 527                                 break;
 528                         return (1000);
 529                 case CPU_VENDOR_INTEL:
 530                         /*
 531                          * XXX Assume Intel platforms have synchronized TSCs.
 532                          */
 533                         return (1000);
 534                 }
 535                 return (800);
 536         }
 537         return (-100);
 538 }
 539
 540 #undef N
 541
 542 #endif /* SMP */
 543
 544 static void
 545 init_TSC_tc(void)
 546 {
 547         uint64_t max_freq;
 548         int shift;
 549
 550         if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled)
 551                 return;
 552
 553         /*
 554          * Limit timecounter frequency to fit in an int and prevent it from
 555          * overflowing too fast.
 556          */
 557         max_freq = UINT_MAX;
 558
 559         /*
 560          * We can not use the TSC if we support APM.  Precise timekeeping
 561          * on an APM'ed machine is at best a fools pursuit, since
 562          * any and all of the time spent in various SMM code can't
 563          * be reliably accounted for.  Reading the RTC is your only
 564          * source of reliable time info.  The i8254 loses too, of course,
 565          * but we need to have some kind of time...
 566          * We don't know at this point whether APM is going to be used
 567          * or not, nor when it might be activated.  Play it safe.
 568          */
 569         if (power_pm_get_type() == POWER_PM_TYPE_APM) {
 570                 tsc_timecounter.tc_quality = -1000;
 571                 if (bootverbose)
 572                         printf("TSC timecounter disabled: APM enabled.\n");
 573                 goto init;
 574         }
 575
 576         /*
 577          * Intel CPUs without a C-state invariant TSC can stop the TSC
 578          * in either C2 or C3.  Disable use of C2 and C3 while using
 579          * the TSC as the timecounter.  The timecounter can be changed
 580          * to enable C2 and C3.
 581          *
 582          * Note that the TSC is used as the cputicker for computing
 583          * thread runtime regardless of the timecounter setting, so
 584          * using an alternate timecounter and enabling C2 or C3 can
 585          * result incorrect runtimes for kernel idle threads (but not
 586          * for any non-idle threads).
 587          */
 588         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
 589             (amd_pminfo & AMDPM_TSC_INVARIANT) == 0) {
 590                 tsc_timecounter.tc_flags |= TC_FLAGS_C2STOP;
 591                 if (bootverbose)
 592                         printf("TSC timecounter disables C2 and C3.\n");
 593         }
 594
 595         /*
 596          * We can not use the TSC in SMP mode unless the TSCs on all CPUs
 597          * are synchronized.  If the user is sure that the system has
 598          * synchronized TSCs, set kern.timecounter.smp_tsc tunable to a
 599          * non-zero value.  The TSC seems unreliable in virtualized SMP
 600          * environments, so it is set to a negative quality in those cases.
 601          */
 602 #ifdef SMP
 603         if (mp_ncpus > 1)
 604                 tsc_timecounter.tc_quality = test_tsc(smp_tsc_adjust);
 605         else
 606 #endif /* SMP */
 607         if (tsc_is_invariant)
 608                 tsc_timecounter.tc_quality = 1000;
 609         max_freq >>= tsc_shift;
 610
 611 init:
 612         for (shift = 0; shift <= 31 && (tsc_freq >> shift) > max_freq; shift++)
 613                 ;
 614         if ((cpu_feature & CPUID_SSE2) != 0 && mp_ncpus > 1) {
 615                 if (cpu_vendor_id == CPU_VENDOR_AMD ||
 616                     cpu_vendor_id == CPU_VENDOR_HYGON) {
 617                         tsc_timecounter.tc_get_timecount = shift > 0 ?
 618                             tsc_get_timecount_low_mfence :
 619                             tsc_get_timecount_mfence;
 620                 } else {
 621                         tsc_timecounter.tc_get_timecount = shift > 0 ?
 622                             tsc_get_timecount_low_lfence :
 623                             tsc_get_timecount_lfence;
 624                 }
 625         } else {
 626                 tsc_timecounter.tc_get_timecount = shift > 0 ?
 627                     tsc_get_timecount_low : tsc_get_timecount;
 628         }
 629         if (shift > 0) {
 630                 tsc_timecounter.tc_name = "TSC-low";
 631                 if (bootverbose)
 632                         printf("TSC timecounter discards lower %d bit(s)\n",
 633                             shift);
 634         }
 635         if (tsc_freq != 0) {
 636                 tsc_timecounter.tc_frequency = tsc_freq >> shift;
 637                 tsc_timecounter.tc_priv = (void *)(intptr_t)shift;
 638                 tc_init(&tsc_timecounter);
 639         }
 640 }
 641 SYSINIT(tsc_tc, SI_SUB_SMP, SI_ORDER_ANY, init_TSC_tc, NULL);
 642
 643 void
 644 resume_TSC(void)
 645 {
 646 #ifdef SMP
 647         int quality;
 648
 649         /* If TSC was not good on boot, it is unlikely to become good now. */
 650         if (tsc_timecounter.tc_quality < 0)
 651                 return;
 652         /* Nothing to do with UP. */
 653         if (mp_ncpus < 2)
 654                 return;
 655
 656         /*
 657          * If TSC was good, a single synchronization should be enough,
 658          * but honour smp_tsc_adjust if it's set.
 659          */
 660         quality = test_tsc(MAX(smp_tsc_adjust, 1));
 661         if (quality != tsc_timecounter.tc_quality) {
 662                 printf("TSC timecounter quality changed: %d -> %d\n",
 663                     tsc_timecounter.tc_quality, quality);
 664                 tsc_timecounter.tc_quality = quality;
 665         }
 666 #endif /* SMP */
 667 }
 668
 669 /*
 670  * When cpufreq levels change, find out about the (new) max frequency.  We
 671  * use this to update CPU accounting in case it got a lower estimate at boot.
 672  */
 673 static void
 674 tsc_levels_changed(void *arg, int unit)
 675 {
 676         device_t cf_dev;
 677         struct cf_level *levels;
 678         int count, error;
 679         uint64_t max_freq;
 680
 681         /* Only use values from the first CPU, assuming all are equal. */
 682         if (unit != 0)
 683                 return;
 684
 685         /* Find the appropriate cpufreq device instance. */
 686         cf_dev = devclass_get_device(devclass_find("cpufreq"), unit);
 687         if (cf_dev == NULL) {
 688                 printf("tsc_levels_changed() called but no cpufreq device?\n");
 689                 return;
 690         }
 691
 692         /* Get settings from the device and find the max frequency. */
 693         count = 64;
 694         levels = malloc(count * sizeof(*levels), M_TEMP, M_NOWAIT);
 695         if (levels == NULL)
 696                 return;
 697         error = CPUFREQ_LEVELS(cf_dev, levels, &count);
 698         if (error == 0 && count != 0) {
 699                 max_freq = (uint64_t)levels[0].total_set.freq * 1000000;
 700                 set_cputicker(rdtsc, max_freq, 1);
 701         } else
 702                 printf("tsc_levels_changed: no max freq found\n");
 703         free(levels, M_TEMP);
 704 }
 705
 706 /*
 707  * If the TSC timecounter is in use, veto the pending change.  It may be
 708  * possible in the future to handle a dynamically-changing timecounter rate.
 709  */
 710 static void
 711 tsc_freq_changing(void *arg, const struct cf_level *level, int *status)
 712 {
 713
 714         if (*status != 0 || timecounter != &tsc_timecounter)
 715                 return;
 716
 717         printf("timecounter TSC must not be in use when "
 718             "changing frequencies; change denied\n");
 719         *status = EBUSY;
 720 }
 721
 722 /* Update TSC freq with the value indicated by the caller. */
 723 static void
 724 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
 725 {
 726         uint64_t freq;
 727
 728         /* If there was an error during the transition, don't do anything. */
 729         if (tsc_disabled || status != 0)
 730                 return;
 731
 732         /* Total setting for this level gives the new frequency in MHz. */
 733         freq = (uint64_t)level->total_set.freq * 1000000;
 734         atomic_store_rel_64(&tsc_freq, freq);
 735         tsc_timecounter.tc_frequency =
 736             freq >> (int)(intptr_t)tsc_timecounter.tc_priv;
 737 }
 738
 739 static int
 740 sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
 741 {
 742         int error;
 743         uint64_t freq;
 744
 745         freq = atomic_load_acq_64(&tsc_freq);
 746         if (freq == 0)
 747                 return (EOPNOTSUPP);
 748         error = sysctl_handle_64(oidp, &freq, 0, req);
 749         if (error == 0 && req->newptr != NULL) {
 750                 atomic_store_rel_64(&tsc_freq, freq);
 751                 atomic_store_rel_64(&tsc_timecounter.tc_frequency,
 752                     freq >> (int)(intptr_t)tsc_timecounter.tc_priv);
 753         }
 754         return (error);
 755 }
 756
 757 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq,
 758     CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 759     0, 0, sysctl_machdep_tsc_freq, "QU",
 760     "Time Stamp Counter frequency");
 761
 762 static u_int
 763 tsc_get_timecount(struct timecounter *tc __unused)
 764 {
 765
 766         return (rdtsc32());
 767 }
 768
 769 static inline u_int
 770 tsc_get_timecount_low(struct timecounter *tc)
 771 {
 772         uint32_t rv;
 773
 774         __asm __volatile("rdtsc; shrd %%cl, %%edx, %0"
 775             : "=a" (rv) : "c" ((int)(intptr_t)tc->tc_priv) : "edx");
 776         return (rv);
 777 }
 778
 779 static u_int
 780 tsc_get_timecount_lfence(struct timecounter *tc __unused)
 781 {
 782
 783         lfence();
 784         return (rdtsc32());
 785 }
 786
 787 static u_int
 788 tsc_get_timecount_low_lfence(struct timecounter *tc)
 789 {
 790
 791         lfence();
 792         return (tsc_get_timecount_low(tc));
 793 }
 794
 795 static u_int
 796 tsc_get_timecount_mfence(struct timecounter *tc __unused)
 797 {
 798
 799         mfence();
 800         return (rdtsc32());
 801 }
 802
 803 static u_int
 804 tsc_get_timecount_low_mfence(struct timecounter *tc)
 805 {
 806
 807         mfence();
 808         return (tsc_get_timecount_low(tc));
 809 }
 810
 811 static uint32_t
 812 x86_tsc_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc)
 813 {
 814
 815         vdso_th->th_algo = VDSO_TH_ALGO_X86_TSC;
 816         vdso_th->th_x86_shift = (int)(intptr_t)tc->tc_priv;
 817         vdso_th->th_x86_hpet_idx = 0xffffffff;
 818         bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
 819         return (1);
 820 }
 821
 822 #ifdef COMPAT_FREEBSD32
 823 static uint32_t
 824 x86_tsc_vdso_timehands32(struct vdso_timehands32 *vdso_th32,
 825     struct timecounter *tc)
 826 {
 827
 828         vdso_th32->th_algo = VDSO_TH_ALGO_X86_TSC;
 829         vdso_th32->th_x86_shift = (int)(intptr_t)tc->tc_priv;
 830         vdso_th32->th_x86_hpet_idx = 0xffffffff;
 831         bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res));
 832         return (1);
 833 }
 834 #endif