2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1998-2003 Poul-Henning Kamp
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include "opt_clock.h"
34 #include <sys/param.h>
37 #include <sys/eventhandler.h>
38 #include <sys/limits.h>
39 #include <sys/malloc.h>
40 #include <sys/systm.h>
41 #include <sys/sysctl.h>
43 #include <sys/timetc.h>
44 #include <sys/kernel.h>
45 #include <sys/power.h>
48 #include <machine/clock.h>
49 #include <machine/cputypes.h>
50 #include <machine/md_var.h>
51 #include <machine/specialreg.h>
52 #include <x86/vmware.h>
53 #include <dev/acpica/acpi_hpet.h>
54 #include <contrib/dev/acpica/include/acpi.h>
56 #include "cpufreq_if.h"
62 static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag;
64 SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN,
65 &tsc_is_invariant, 0, "Indicates whether the TSC is P-state invariant");
69 SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc, CTLFLAG_RDTUN, &smp_tsc, 0,
70 "Indicates whether the TSC is safe to use in SMP mode");
72 int smp_tsc_adjust = 0;
73 SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc_adjust, CTLFLAG_RDTUN,
74 &smp_tsc_adjust, 0, "Try to adjust TSC on APs to match BSP");
77 static int tsc_shift = 1;
78 SYSCTL_INT(_kern_timecounter, OID_AUTO, tsc_shift, CTLFLAG_RDTUN,
79 &tsc_shift, 0, "Shift to pre-apply for the maximum TSC frequency");
81 static int tsc_disabled;
82 SYSCTL_INT(_machdep, OID_AUTO, disable_tsc, CTLFLAG_RDTUN, &tsc_disabled, 0,
83 "Disable x86 Time Stamp Counter");
85 static int tsc_skip_calibration;
86 SYSCTL_INT(_machdep, OID_AUTO, disable_tsc_calibration, CTLFLAG_RDTUN,
87 &tsc_skip_calibration, 0,
88 "Disable TSC frequency calibration");
90 static void tsc_freq_changed(void *arg, const struct cf_level *level,
92 static void tsc_freq_changing(void *arg, const struct cf_level *level,
94 static u_int tsc_get_timecount(struct timecounter *tc);
95 static inline u_int tsc_get_timecount_low(struct timecounter *tc);
96 static u_int tsc_get_timecount_lfence(struct timecounter *tc);
97 static u_int tsc_get_timecount_low_lfence(struct timecounter *tc);
98 static u_int tsc_get_timecount_mfence(struct timecounter *tc);
99 static u_int tsc_get_timecount_low_mfence(struct timecounter *tc);
100 static u_int tscp_get_timecount(struct timecounter *tc);
101 static u_int tscp_get_timecount_low(struct timecounter *tc);
102 static void tsc_levels_changed(void *arg, int unit);
103 static uint32_t x86_tsc_vdso_timehands(struct vdso_timehands *vdso_th,
104 struct timecounter *tc);
105 #ifdef COMPAT_FREEBSD32
106 static uint32_t x86_tsc_vdso_timehands32(struct vdso_timehands32 *vdso_th32,
107 struct timecounter *tc);
110 static struct timecounter tsc_timecounter = {
111 .tc_get_timecount = tsc_get_timecount,
112 .tc_counter_mask = ~0u,
114 .tc_quality = 800, /* adjusted in code */
115 .tc_fill_vdso_timehands = x86_tsc_vdso_timehands,
116 #ifdef COMPAT_FREEBSD32
117 .tc_fill_vdso_timehands32 = x86_tsc_vdso_timehands32,
122 tsc_freq_vmware(void)
126 if (hv_high >= 0x40000010) {
127 do_cpuid(0x40000010, regs);
128 tsc_freq = regs[0] * 1000;
130 vmware_hvcall(VMW_HVCMD_GETHZ, regs);
131 if (regs[1] != UINT_MAX)
132 tsc_freq = regs[0] | ((uint64_t)regs[1] << 32);
134 tsc_is_invariant = 1;
138 * Calculate TSC frequency using information from the CPUID leaf 0x15
139 * 'Time Stamp Counter and Nominal Core Crystal Clock'. If leaf 0x15
140 * is not functional, as it is on Skylake/Kabylake, try 0x16 'Processor
141 * Frequency Information'. Leaf 0x16 is described in the SDM as
142 * informational only, but if 0x15 did not work, and TSC calibration
143 * is disabled, it is the best we can get at all. It should still be
144 * an improvement over the parsing of the CPU model name in
145 * tsc_freq_intel(), when available.
148 tsc_freq_cpuid(uint64_t *res)
154 do_cpuid(0x15, regs);
155 if (regs[0] != 0 && regs[1] != 0 && regs[2] != 0) {
156 *res = (uint64_t)regs[2] * regs[1] / regs[0];
162 do_cpuid(0x16, regs);
164 *res = (uint64_t)regs[0] * 1000000;
181 * Intel Processor Identification and the CPUID Instruction
182 * Application Note 485.
183 * http://www.intel.com/assets/pdf/appnote/241618.pdf
185 if (cpu_exthigh >= 0x80000004) {
187 for (i = 0x80000002; i < 0x80000005; i++) {
189 memcpy(p, regs, sizeof(regs));
193 for (i = 0; i < sizeof(brand) - 1; i++)
194 if (brand[i] == 'H' && brand[i + 1] == 'z')
211 #define C2D(c) ((c) - '0')
213 freq = C2D(p[0]) * 1000;
214 freq += C2D(p[2]) * 100;
215 freq += C2D(p[3]) * 10;
218 freq = C2D(p[0]) * 1000;
219 freq += C2D(p[1]) * 100;
220 freq += C2D(p[2]) * 10;
233 uint64_t tmp_freq, tsc1, tsc2;
234 int no_cpuid_override;
236 if (cpu_power_ecx & CPUID_PERF_STAT) {
238 * XXX Some emulators expose host CPUID without actual support
239 * for these MSRs. We must test whether they really work.
244 if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0)
248 if (vm_guest == VM_GUEST_VMWARE) {
253 switch (cpu_vendor_id) {
255 case CPU_VENDOR_HYGON:
256 if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
257 (vm_guest == VM_GUEST_NO &&
258 CPUID_TO_FAMILY(cpu_id) >= 0x10))
259 tsc_is_invariant = 1;
260 if (cpu_feature & CPUID_SSE2) {
261 tsc_timecounter.tc_get_timecount =
262 tsc_get_timecount_mfence;
265 case CPU_VENDOR_INTEL:
266 if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
267 (vm_guest == VM_GUEST_NO &&
268 ((CPUID_TO_FAMILY(cpu_id) == 0x6 &&
269 CPUID_TO_MODEL(cpu_id) >= 0xe) ||
270 (CPUID_TO_FAMILY(cpu_id) == 0xf &&
271 CPUID_TO_MODEL(cpu_id) >= 0x3))))
272 tsc_is_invariant = 1;
273 if (cpu_feature & CPUID_SSE2) {
274 tsc_timecounter.tc_get_timecount =
275 tsc_get_timecount_lfence;
278 case CPU_VENDOR_CENTAUR:
279 if (vm_guest == VM_GUEST_NO &&
280 CPUID_TO_FAMILY(cpu_id) == 0x6 &&
281 CPUID_TO_MODEL(cpu_id) >= 0xf &&
282 (rdmsr(0x1203) & 0x100000000ULL) == 0)
283 tsc_is_invariant = 1;
284 if (cpu_feature & CPUID_SSE2) {
285 tsc_timecounter.tc_get_timecount =
286 tsc_get_timecount_lfence;
291 if (tsc_skip_calibration) {
292 if (tsc_freq_cpuid(&tmp_freq))
294 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
300 printf("Calibrating TSC clock ... ");
304 tsc_freq = tsc2 - tsc1;
307 * If the difference between calibrated frequency and
308 * the frequency reported by CPUID 0x15/0x16 leafs
309 * differ significantly, this probably means that
310 * calibration is bogus. It happens on machines
311 * without 8254 timer. The BIOS rarely properly
312 * reports it in FADT boot flags, so just compare the
313 * frequencies directly.
315 if (tsc_freq_cpuid(&tmp_freq) && qabs(tsc_freq - tmp_freq) >
316 uqmin(tsc_freq, tmp_freq)) {
317 no_cpuid_override = 0;
318 TUNABLE_INT_FETCH("machdep.disable_tsc_cpuid_override",
320 if (!no_cpuid_override) {
323 "TSC clock: calibration freq %ju Hz, CPUID freq %ju Hz%s\n",
326 no_cpuid_override ? "" :
327 ", doing CPUID override");
334 printf("TSC clock: %ju Hz\n", (intmax_t)tsc_freq);
341 if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled)
345 /* The TSC is known to be broken on certain CPUs. */
346 switch (cpu_vendor_id) {
348 switch (cpu_id & 0xFF0) {
354 case CPU_VENDOR_CENTAUR:
355 switch (cpu_id & 0xff0) {
358 * http://www.centtech.com/c6_data_sheet.pdf
360 * I-12 RDTSC may return incoherent values in EDX:EAX
361 * I-13 RDTSC hangs when certain event counters are used
367 switch (cpu_id & 0xff0) {
369 if ((cpu_id & CPUID_STEPPING) == 0)
380 * Inform CPU accounting about our boot-time clock rate. This will
381 * be updated if someone loads a cpufreq driver after boot that
382 * discovers a new max frequency.
385 set_cputicker(rdtsc, tsc_freq, !tsc_is_invariant);
387 if (tsc_is_invariant)
390 /* Register to find out about changes in CPU frequency. */
391 tsc_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change,
392 tsc_freq_changing, NULL, EVENTHANDLER_PRI_FIRST);
393 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
394 tsc_freq_changed, NULL, EVENTHANDLER_PRI_FIRST);
395 tsc_levels_tag = EVENTHANDLER_REGISTER(cpufreq_levels_changed,
396 tsc_levels_changed, NULL, EVENTHANDLER_PRI_ANY);
402 * RDTSC is not a serializing instruction, and does not drain
403 * instruction stream, so we need to drain the stream before executing
404 * it. It could be fixed by use of RDTSCP, except the instruction is
405 * not available everywhere.
407 * Use CPUID for draining in the boot-time SMP constistency test. The
408 * timecounters use MFENCE for AMD CPUs, and LFENCE for others (Intel
409 * and VIA) when SSE2 is present, and nothing on older machines which
410 * also do not issue RDTSC prematurely. There, testing for SSE2 and
411 * vendor is too cumbersome, and we learn about TSC presence from CPUID.
413 * Do not use do_cpuid(), since we do not need CPUID results, which
414 * have to be written into memory with do_cpuid().
416 #define TSC_READ(x) \
418 tsc_read_##x(void *arg) \
420 uint64_t *tsc = arg; \
421 u_int cpu = PCPU_GET(cpuid); \
423 __asm __volatile("cpuid" : : : "eax", "ebx", "ecx", "edx"); \
424 tsc[cpu * 3 + x] = rdtsc(); \
434 comp_smp_tsc(void *arg)
438 u_int cpu = PCPU_GET(cpuid);
441 size = (mp_maxid + 1) * 3;
442 for (i = 0, tsc = arg; i < N; i++, tsc += size)
446 d1 = tsc[cpu * 3 + 1] - tsc[j * 3];
447 d2 = tsc[cpu * 3 + 2] - tsc[j * 3 + 1];
448 if (d1 <= 0 || d2 <= 0) {
456 adj_smp_tsc(void *arg)
460 u_int cpu = PCPU_GET(cpuid);
461 u_int first, i, size;
468 size = (mp_maxid + 1) * 3;
469 for (i = 0, tsc = arg; i < N; i++, tsc += size) {
470 d = tsc[first * 3] - tsc[cpu * 3 + 1];
473 d = tsc[first * 3 + 1] - tsc[cpu * 3 + 2];
476 d = tsc[first * 3 + 1] - tsc[cpu * 3];
479 d = tsc[first * 3 + 2] - tsc[cpu * 3 + 1];
485 d = min / 2 + max / 2;
487 "movl $0x10, %%ecx\n\t"
489 "addl %%edi, %%eax\n\t"
490 "adcl %%esi, %%edx\n\t"
493 : "D" ((uint32_t)d), "S" ((uint32_t)(d >> 32))
494 : "ax", "cx", "dx", "cc"
499 test_tsc(int adj_max_count)
501 uint64_t *data, *tsc;
504 if ((!smp_tsc && !tsc_is_invariant))
507 * Misbehavior of TSC under VirtualBox has been observed. In
508 * particular, threads doing small (~1 second) sleeps may miss their
509 * wakeup and hang around in sleep state, causing hangs on shutdown.
511 if (vm_guest == VM_GUEST_VBOX)
514 size = (mp_maxid + 1) * 3;
515 data = malloc(sizeof(*data) * size * N, M_TEMP, M_WAITOK);
518 for (i = 0, tsc = data; i < N; i++, tsc += size)
519 smp_rendezvous(tsc_read_0, tsc_read_1, tsc_read_2, tsc);
520 smp_tsc = 1; /* XXX */
521 smp_rendezvous(smp_no_rendezvous_barrier, comp_smp_tsc,
522 smp_no_rendezvous_barrier, data);
523 if (!smp_tsc && adj < adj_max_count) {
525 smp_rendezvous(smp_no_rendezvous_barrier, adj_smp_tsc,
526 smp_no_rendezvous_barrier, data);
531 printf("SMP: %sed TSC synchronization test%s\n",
532 smp_tsc ? "pass" : "fail",
533 adj > 0 ? " after adjustment" : "");
534 if (smp_tsc && tsc_is_invariant) {
535 switch (cpu_vendor_id) {
537 case CPU_VENDOR_HYGON:
539 * Processor Programming Reference (PPR) for AMD
540 * Family 17h states that the TSC uses a common
541 * reference for all sockets, cores and threads.
543 if (CPUID_TO_FAMILY(cpu_id) >= 0x17)
546 * Starting with Family 15h processors, TSC clock
547 * source is in the north bridge. Check whether
548 * we have a single-socket/multi-core platform.
549 * XXX Need more work for complex cases.
551 if (CPUID_TO_FAMILY(cpu_id) < 0x15 ||
552 (amd_feature2 & AMDID2_CMP) == 0 ||
553 smp_cpus > (cpu_procinfo2 & AMDID_CMP_CORES) + 1)
556 case CPU_VENDOR_INTEL:
558 * XXX Assume Intel platforms have synchronized TSCs.
577 if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled)
581 * Limit timecounter frequency to fit in an int and prevent it from
582 * overflowing too fast.
587 * We can not use the TSC if we support APM. Precise timekeeping
588 * on an APM'ed machine is at best a fools pursuit, since
589 * any and all of the time spent in various SMM code can't
590 * be reliably accounted for. Reading the RTC is your only
591 * source of reliable time info. The i8254 loses too, of course,
592 * but we need to have some kind of time...
593 * We don't know at this point whether APM is going to be used
594 * or not, nor when it might be activated. Play it safe.
596 if (power_pm_get_type() == POWER_PM_TYPE_APM) {
597 tsc_timecounter.tc_quality = -1000;
599 printf("TSC timecounter disabled: APM enabled.\n");
604 * Intel CPUs without a C-state invariant TSC can stop the TSC
605 * in either C2 or C3. Disable use of C2 and C3 while using
606 * the TSC as the timecounter. The timecounter can be changed
607 * to enable C2 and C3.
609 * Note that the TSC is used as the cputicker for computing
610 * thread runtime regardless of the timecounter setting, so
611 * using an alternate timecounter and enabling C2 or C3 can
612 * result incorrect runtimes for kernel idle threads (but not
613 * for any non-idle threads).
615 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
616 (amd_pminfo & AMDPM_TSC_INVARIANT) == 0) {
617 tsc_timecounter.tc_flags |= TC_FLAGS_C2STOP;
619 printf("TSC timecounter disables C2 and C3.\n");
623 * We can not use the TSC in SMP mode unless the TSCs on all CPUs
624 * are synchronized. If the user is sure that the system has
625 * synchronized TSCs, set kern.timecounter.smp_tsc tunable to a
626 * non-zero value. The TSC seems unreliable in virtualized SMP
627 * environments, so it is set to a negative quality in those cases.
631 tsc_timecounter.tc_quality = test_tsc(smp_tsc_adjust);
634 if (tsc_is_invariant)
635 tsc_timecounter.tc_quality = 1000;
636 max_freq >>= tsc_shift;
639 for (shift = 0; shift <= 31 && (tsc_freq >> shift) > max_freq; shift++)
643 * Timecounter implementation selection, top to bottom:
644 * - If RDTSCP is available, use RDTSCP.
645 * - If fence instructions are provided (SSE2), use LFENCE;RDTSC
646 * on Intel, and MFENCE;RDTSC on AMD.
647 * - For really old CPUs, just use RDTSC.
649 if ((amd_feature & AMDID_RDTSCP) != 0) {
650 tsc_timecounter.tc_get_timecount = shift > 0 ?
651 tscp_get_timecount_low : tscp_get_timecount;
652 } else if ((cpu_feature & CPUID_SSE2) != 0 && mp_ncpus > 1) {
653 if (cpu_vendor_id == CPU_VENDOR_AMD ||
654 cpu_vendor_id == CPU_VENDOR_HYGON) {
655 tsc_timecounter.tc_get_timecount = shift > 0 ?
656 tsc_get_timecount_low_mfence :
657 tsc_get_timecount_mfence;
659 tsc_timecounter.tc_get_timecount = shift > 0 ?
660 tsc_get_timecount_low_lfence :
661 tsc_get_timecount_lfence;
664 tsc_timecounter.tc_get_timecount = shift > 0 ?
665 tsc_get_timecount_low : tsc_get_timecount;
668 tsc_timecounter.tc_name = "TSC-low";
670 printf("TSC timecounter discards lower %d bit(s)\n",
674 tsc_timecounter.tc_frequency = tsc_freq >> shift;
675 tsc_timecounter.tc_priv = (void *)(intptr_t)shift;
676 tc_init(&tsc_timecounter);
679 SYSINIT(tsc_tc, SI_SUB_SMP, SI_ORDER_ANY, init_TSC_tc, NULL);
687 /* If TSC was not good on boot, it is unlikely to become good now. */
688 if (tsc_timecounter.tc_quality < 0)
690 /* Nothing to do with UP. */
695 * If TSC was good, a single synchronization should be enough,
696 * but honour smp_tsc_adjust if it's set.
698 quality = test_tsc(MAX(smp_tsc_adjust, 1));
699 if (quality != tsc_timecounter.tc_quality) {
700 printf("TSC timecounter quality changed: %d -> %d\n",
701 tsc_timecounter.tc_quality, quality);
702 tsc_timecounter.tc_quality = quality;
708 * When cpufreq levels change, find out about the (new) max frequency. We
709 * use this to update CPU accounting in case it got a lower estimate at boot.
712 tsc_levels_changed(void *arg, int unit)
715 struct cf_level *levels;
719 /* Only use values from the first CPU, assuming all are equal. */
723 /* Find the appropriate cpufreq device instance. */
724 cf_dev = devclass_get_device(devclass_find("cpufreq"), unit);
725 if (cf_dev == NULL) {
726 printf("tsc_levels_changed() called but no cpufreq device?\n");
730 /* Get settings from the device and find the max frequency. */
732 levels = malloc(count * sizeof(*levels), M_TEMP, M_NOWAIT);
735 error = CPUFREQ_LEVELS(cf_dev, levels, &count);
736 if (error == 0 && count != 0) {
737 max_freq = (uint64_t)levels[0].total_set.freq * 1000000;
738 set_cputicker(rdtsc, max_freq, 1);
740 printf("tsc_levels_changed: no max freq found\n");
741 free(levels, M_TEMP);
745 * If the TSC timecounter is in use, veto the pending change. It may be
746 * possible in the future to handle a dynamically-changing timecounter rate.
749 tsc_freq_changing(void *arg, const struct cf_level *level, int *status)
752 if (*status != 0 || timecounter != &tsc_timecounter)
755 printf("timecounter TSC must not be in use when "
756 "changing frequencies; change denied\n");
760 /* Update TSC freq with the value indicated by the caller. */
762 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
766 /* If there was an error during the transition, don't do anything. */
767 if (tsc_disabled || status != 0)
770 /* Total setting for this level gives the new frequency in MHz. */
771 freq = (uint64_t)level->total_set.freq * 1000000;
772 atomic_store_rel_64(&tsc_freq, freq);
773 tsc_timecounter.tc_frequency =
774 freq >> (int)(intptr_t)tsc_timecounter.tc_priv;
778 sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
783 freq = atomic_load_acq_64(&tsc_freq);
786 error = sysctl_handle_64(oidp, &freq, 0, req);
787 if (error == 0 && req->newptr != NULL) {
788 atomic_store_rel_64(&tsc_freq, freq);
789 atomic_store_rel_64(&tsc_timecounter.tc_frequency,
790 freq >> (int)(intptr_t)tsc_timecounter.tc_priv);
795 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq,
796 CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
797 0, 0, sysctl_machdep_tsc_freq, "QU",
798 "Time Stamp Counter frequency");
801 tsc_get_timecount(struct timecounter *tc __unused)
808 tscp_get_timecount(struct timecounter *tc __unused)
815 tsc_get_timecount_low(struct timecounter *tc)
819 __asm __volatile("rdtsc; shrd %%cl, %%edx, %0"
820 : "=a" (rv) : "c" ((int)(intptr_t)tc->tc_priv) : "edx");
825 tscp_get_timecount_low(struct timecounter *tc)
829 __asm __volatile("rdtscp; movl %1, %%ecx; shrd %%cl, %%edx, %0"
830 : "=&a" (rv) : "m" (tc->tc_priv) : "ecx", "edx");
835 tsc_get_timecount_lfence(struct timecounter *tc __unused)
843 tsc_get_timecount_low_lfence(struct timecounter *tc)
847 return (tsc_get_timecount_low(tc));
851 tsc_get_timecount_mfence(struct timecounter *tc __unused)
859 tsc_get_timecount_low_mfence(struct timecounter *tc)
863 return (tsc_get_timecount_low(tc));
867 x86_tsc_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc)
870 vdso_th->th_algo = VDSO_TH_ALGO_X86_TSC;
871 vdso_th->th_x86_shift = (int)(intptr_t)tc->tc_priv;
872 vdso_th->th_x86_hpet_idx = 0xffffffff;
873 bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
877 #ifdef COMPAT_FREEBSD32
879 x86_tsc_vdso_timehands32(struct vdso_timehands32 *vdso_th32,
880 struct timecounter *tc)
883 vdso_th32->th_algo = VDSO_TH_ALGO_X86_TSC;
884 vdso_th32->th_x86_shift = (int)(intptr_t)tc->tc_priv;
885 vdso_th32->th_x86_hpet_idx = 0xffffffff;
886 bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res));