sys/x86/x86/tsc.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 1998-2003 Poul-Henning Kamp
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include "opt_clock.h"
  33
  34 #include <sys/param.h>
  35 #include <sys/bus.h>
  36 #include <sys/cpu.h>
  37 #include <sys/eventhandler.h>
  38 #include <sys/limits.h>
  39 #include <sys/malloc.h>
  40 #include <sys/systm.h>
  41 #include <sys/sysctl.h>
  42 #include <sys/time.h>
  43 #include <sys/timetc.h>
  44 #include <sys/kernel.h>
  45 #include <sys/power.h>
  46 #include <sys/smp.h>
  47 #include <sys/vdso.h>
  48 #include <machine/clock.h>
  49 #include <machine/cputypes.h>
  50 #include <machine/md_var.h>
  51 #include <machine/specialreg.h>
  52 #include <x86/vmware.h>
  53 #include <dev/acpica/acpi_hpet.h>
  54 #include <contrib/dev/acpica/include/acpi.h>
  55
  56 #include "cpufreq_if.h"
  57
  58 uint64_t        tsc_freq;
  59 int             tsc_is_invariant;
  60 int             tsc_perf_stat;
  61
  62 static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag;
  63
  64 SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN,
  65     &tsc_is_invariant, 0, "Indicates whether the TSC is P-state invariant");
  66
  67 #ifdef SMP
  68 int     smp_tsc;
  69 SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc, CTLFLAG_RDTUN, &smp_tsc, 0,
  70     "Indicates whether the TSC is safe to use in SMP mode");
  71
  72 int     smp_tsc_adjust = 0;
  73 SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc_adjust, CTLFLAG_RDTUN,
  74     &smp_tsc_adjust, 0, "Try to adjust TSC on APs to match BSP");
  75 #endif
  76
  77 static int      tsc_shift = 1;
  78 SYSCTL_INT(_kern_timecounter, OID_AUTO, tsc_shift, CTLFLAG_RDTUN,
  79     &tsc_shift, 0, "Shift to pre-apply for the maximum TSC frequency");
  80
  81 static int      tsc_disabled;
  82 SYSCTL_INT(_machdep, OID_AUTO, disable_tsc, CTLFLAG_RDTUN, &tsc_disabled, 0,
  83     "Disable x86 Time Stamp Counter");
  84
  85 static int      tsc_skip_calibration;
  86 SYSCTL_INT(_machdep, OID_AUTO, disable_tsc_calibration, CTLFLAG_RDTUN |
  87     CTLFLAG_NOFETCH, &tsc_skip_calibration, 0,
  88     "Disable TSC frequency calibration");
  89
  90 static void tsc_freq_changed(void *arg, const struct cf_level *level,
  91     int status);
  92 static void tsc_freq_changing(void *arg, const struct cf_level *level,
  93     int *status);
  94 static unsigned tsc_get_timecount(struct timecounter *tc);
  95 static inline unsigned tsc_get_timecount_low(struct timecounter *tc);
  96 static unsigned tsc_get_timecount_lfence(struct timecounter *tc);
  97 static unsigned tsc_get_timecount_low_lfence(struct timecounter *tc);
  98 static unsigned tsc_get_timecount_mfence(struct timecounter *tc);
  99 static unsigned tsc_get_timecount_low_mfence(struct timecounter *tc);
 100 static void tsc_levels_changed(void *arg, int unit);
 101 static uint32_t x86_tsc_vdso_timehands(struct vdso_timehands *vdso_th,
 102     struct timecounter *tc);
 103 #ifdef COMPAT_FREEBSD32
 104 static uint32_t x86_tsc_vdso_timehands32(struct vdso_timehands32 *vdso_th32,
 105     struct timecounter *tc);
 106 #endif
 107
 108 static struct timecounter tsc_timecounter = {
 109         .tc_get_timecount =             tsc_get_timecount,
 110         .tc_counter_mask =              ~0u,
 111         .tc_name =                      "TSC",
 112         .tc_quality =                   800,    /* adjusted in code */
 113         .tc_fill_vdso_timehands =       x86_tsc_vdso_timehands,
 114 #ifdef COMPAT_FREEBSD32
 115         .tc_fill_vdso_timehands32 =     x86_tsc_vdso_timehands32,
 116 #endif
 117 };
 118
 119 static void
 120 tsc_freq_vmware(void)
 121 {
 122         u_int regs[4];
 123
 124         if (hv_high >= 0x40000010) {
 125                 do_cpuid(0x40000010, regs);
 126                 tsc_freq = regs[0] * 1000;
 127         } else {
 128                 vmware_hvcall(VMW_HVCMD_GETHZ, regs);
 129                 if (regs[1] != UINT_MAX)
 130                         tsc_freq = regs[0] | ((uint64_t)regs[1] << 32);
 131         }
 132         tsc_is_invariant = 1;
 133 }
 134
 135 /*
 136  * Calculate TSC frequency using information from the CPUID leaf 0x15
 137  * 'Time Stamp Counter and Nominal Core Crystal Clock'.  If leaf 0x15
 138  * is not functional, as it is on Skylake/Kabylake, try 0x16 'Processor
 139  * Frequency Information'.  Leaf 0x16 is described in the SDM as
 140  * informational only, but if 0x15 did not work, and TSC calibration
 141  * is disabled, it is the best we can get at all.  It should still be
 142  * an improvement over the parsing of the CPU model name in
 143  * tsc_freq_intel(), when available.
 144  */
 145 static bool
 146 tsc_freq_cpuid(void)
 147 {
 148         u_int regs[4];
 149
 150         if (cpu_high < 0x15)
 151                 return (false);
 152         do_cpuid(0x15, regs);
 153         if (regs[0] != 0 && regs[1] != 0 && regs[2] != 0) {
 154                 tsc_freq = (uint64_t)regs[2] * regs[1] / regs[0];
 155                 return (true);
 156         }
 157
 158         if (cpu_high < 0x16)
 159                 return (false);
 160         do_cpuid(0x16, regs);
 161         if (regs[0] != 0) {
 162                 tsc_freq = (uint64_t)regs[0] * 1000000;
 163                 return (true);
 164         }
 165
 166         return (false);
 167 }
 168
 169 static void
 170 tsc_freq_intel(void)
 171 {
 172         char brand[48];
 173         u_int regs[4];
 174         uint64_t freq;
 175         char *p;
 176         u_int i;
 177
 178         /*
 179          * Intel Processor Identification and the CPUID Instruction
 180          * Application Note 485.
 181          * http://www.intel.com/assets/pdf/appnote/241618.pdf
 182          */
 183         if (cpu_exthigh >= 0x80000004) {
 184                 p = brand;
 185                 for (i = 0x80000002; i < 0x80000005; i++) {
 186                         do_cpuid(i, regs);
 187                         memcpy(p, regs, sizeof(regs));
 188                         p += sizeof(regs);
 189                 }
 190                 p = NULL;
 191                 for (i = 0; i < sizeof(brand) - 1; i++)
 192                         if (brand[i] == 'H' && brand[i + 1] == 'z')
 193                                 p = brand + i;
 194                 if (p != NULL) {
 195                         p -= 5;
 196                         switch (p[4]) {
 197                         case 'M':
 198                                 i = 1;
 199                                 break;
 200                         case 'G':
 201                                 i = 1000;
 202                                 break;
 203                         case 'T':
 204                                 i = 1000000;
 205                                 break;
 206                         default:
 207                                 return;
 208                         }
 209 #define C2D(c)  ((c) - '0')
 210                         if (p[1] == '.') {
 211                                 freq = C2D(p[0]) * 1000;
 212                                 freq += C2D(p[2]) * 100;
 213                                 freq += C2D(p[3]) * 10;
 214                                 freq *= i * 1000;
 215                         } else {
 216                                 freq = C2D(p[0]) * 1000;
 217                                 freq += C2D(p[1]) * 100;
 218                                 freq += C2D(p[2]) * 10;
 219                                 freq += C2D(p[3]);
 220                                 freq *= i * 1000000;
 221                         }
 222 #undef C2D
 223                         tsc_freq = freq;
 224                 }
 225         }
 226 }
 227
 228 static void
 229 probe_tsc_freq(void)
 230 {
 231         uint64_t tsc1, tsc2;
 232         uint16_t bootflags;
 233
 234         if (cpu_power_ecx & CPUID_PERF_STAT) {
 235                 /*
 236                  * XXX Some emulators expose host CPUID without actual support
 237                  * for these MSRs.  We must test whether they really work.
 238                  */
 239                 wrmsr(MSR_MPERF, 0);
 240                 wrmsr(MSR_APERF, 0);
 241                 DELAY(10);
 242                 if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0)
 243                         tsc_perf_stat = 1;
 244         }
 245
 246         if (vm_guest == VM_GUEST_VMWARE) {
 247                 tsc_freq_vmware();
 248                 return;
 249         }
 250
 251         switch (cpu_vendor_id) {
 252         case CPU_VENDOR_AMD:
 253                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
 254                     (vm_guest == VM_GUEST_NO &&
 255                     CPUID_TO_FAMILY(cpu_id) >= 0x10))
 256                         tsc_is_invariant = 1;
 257                 if (cpu_feature & CPUID_SSE2) {
 258                         tsc_timecounter.tc_get_timecount =
 259                             tsc_get_timecount_mfence;
 260                 }
 261                 break;
 262         case CPU_VENDOR_INTEL:
 263                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
 264                     (vm_guest == VM_GUEST_NO &&
 265                     ((CPUID_TO_FAMILY(cpu_id) == 0x6 &&
 266                     CPUID_TO_MODEL(cpu_id) >= 0xe) ||
 267                     (CPUID_TO_FAMILY(cpu_id) == 0xf &&
 268                     CPUID_TO_MODEL(cpu_id) >= 0x3))))
 269                         tsc_is_invariant = 1;
 270                 if (cpu_feature & CPUID_SSE2) {
 271                         tsc_timecounter.tc_get_timecount =
 272                             tsc_get_timecount_lfence;
 273                 }
 274                 break;
 275         case CPU_VENDOR_CENTAUR:
 276                 if (vm_guest == VM_GUEST_NO &&
 277                     CPUID_TO_FAMILY(cpu_id) == 0x6 &&
 278                     CPUID_TO_MODEL(cpu_id) >= 0xf &&
 279                     (rdmsr(0x1203) & 0x100000000ULL) == 0)
 280                         tsc_is_invariant = 1;
 281                 if (cpu_feature & CPUID_SSE2) {
 282                         tsc_timecounter.tc_get_timecount =
 283                             tsc_get_timecount_lfence;
 284                 }
 285                 break;
 286         }
 287
 288         if (!TUNABLE_INT_FETCH("machdep.disable_tsc_calibration",
 289             &tsc_skip_calibration)) {
 290                 /*
 291                  * User did not give the order about calibration.
 292                  * If he did, we do not try to guess.
 293                  *
 294                  * Otherwise, if ACPI FADT reports that the platform
 295                  * is legacy-free and CPUID provides TSC frequency,
 296                  * use it.  The calibration could fail anyway since
 297                  * ISA timer can be absent or power gated.
 298                  */
 299                 if (acpi_get_fadt_bootflags(&bootflags) &&
 300                     (bootflags & ACPI_FADT_LEGACY_DEVICES) == 0 &&
 301                     tsc_freq_cpuid()) {
 302                         printf("Skipping TSC calibration since no legacy "
 303                             "devices reported by FADT and CPUID works\n");
 304                         tsc_skip_calibration = 1;
 305                 }
 306         }
 307         if (tsc_skip_calibration) {
 308                 if (tsc_freq_cpuid())
 309                         ;
 310                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
 311                         tsc_freq_intel();
 312         } else {
 313                 if (bootverbose)
 314                         printf("Calibrating TSC clock ... ");
 315                 tsc1 = rdtsc();
 316                 DELAY(1000000);
 317                 tsc2 = rdtsc();
 318                 tsc_freq = tsc2 - tsc1;
 319         }
 320         if (bootverbose)
 321                 printf("TSC clock: %ju Hz\n", (intmax_t)tsc_freq);
 322 }
 323
 324 void
 325 init_TSC(void)
 326 {
 327
 328         if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled)
 329                 return;
 330
 331 #ifdef __i386__
 332         /* The TSC is known to be broken on certain CPUs. */
 333         switch (cpu_vendor_id) {
 334         case CPU_VENDOR_AMD:
 335                 switch (cpu_id & 0xFF0) {
 336                 case 0x500:
 337                         /* K5 Model 0 */
 338                         return;
 339                 }
 340                 break;
 341         case CPU_VENDOR_CENTAUR:
 342                 switch (cpu_id & 0xff0) {
 343                 case 0x540:
 344                         /*
 345                          * http://www.centtech.com/c6_data_sheet.pdf
 346                          *
 347                          * I-12 RDTSC may return incoherent values in EDX:EAX
 348                          * I-13 RDTSC hangs when certain event counters are used
 349                          */
 350                         return;
 351                 }
 352                 break;
 353         case CPU_VENDOR_NSC:
 354                 switch (cpu_id & 0xff0) {
 355                 case 0x540:
 356                         if ((cpu_id & CPUID_STEPPING) == 0)
 357                                 return;
 358                         break;
 359                 }
 360                 break;
 361         }
 362 #endif
 363
 364         probe_tsc_freq();
 365
 366         /*
 367          * Inform CPU accounting about our boot-time clock rate.  This will
 368          * be updated if someone loads a cpufreq driver after boot that
 369          * discovers a new max frequency.
 370          */
 371         if (tsc_freq != 0)
 372                 set_cputicker(rdtsc, tsc_freq, !tsc_is_invariant);
 373
 374         if (tsc_is_invariant)
 375                 return;
 376
 377         /* Register to find out about changes in CPU frequency. */
 378         tsc_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change,
 379             tsc_freq_changing, NULL, EVENTHANDLER_PRI_FIRST);
 380         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
 381             tsc_freq_changed, NULL, EVENTHANDLER_PRI_FIRST);
 382         tsc_levels_tag = EVENTHANDLER_REGISTER(cpufreq_levels_changed,
 383             tsc_levels_changed, NULL, EVENTHANDLER_PRI_ANY);
 384 }
 385
 386 #ifdef SMP
 387
 388 /*
 389  * RDTSC is not a serializing instruction, and does not drain
 390  * instruction stream, so we need to drain the stream before executing
 391  * it.  It could be fixed by use of RDTSCP, except the instruction is
 392  * not available everywhere.
 393  *
 394  * Use CPUID for draining in the boot-time SMP constistency test.  The
 395  * timecounters use MFENCE for AMD CPUs, and LFENCE for others (Intel
 396  * and VIA) when SSE2 is present, and nothing on older machines which
 397  * also do not issue RDTSC prematurely.  There, testing for SSE2 and
 398  * vendor is too cumbersome, and we learn about TSC presence from CPUID.
 399  *
 400  * Do not use do_cpuid(), since we do not need CPUID results, which
 401  * have to be written into memory with do_cpuid().
 402  */
 403 #define TSC_READ(x)                                                     \
 404 static void                                                             \
 405 tsc_read_##x(void *arg)                                                 \
 406 {                                                                       \
 407         uint64_t *tsc = arg;                                            \
 408         u_int cpu = PCPU_GET(cpuid);                                    \
 409                                                                         \
 410         __asm __volatile("cpuid" : : : "eax", "ebx", "ecx", "edx");     \
 411         tsc[cpu * 3 + x] = rdtsc();                                     \
 412 }
 413 TSC_READ(0)
 414 TSC_READ(1)
 415 TSC_READ(2)
 416 #undef TSC_READ
 417
 418 #define N       1000
 419
 420 static void
 421 comp_smp_tsc(void *arg)
 422 {
 423         uint64_t *tsc;
 424         int64_t d1, d2;
 425         u_int cpu = PCPU_GET(cpuid);
 426         u_int i, j, size;
 427
 428         size = (mp_maxid + 1) * 3;
 429         for (i = 0, tsc = arg; i < N; i++, tsc += size)
 430                 CPU_FOREACH(j) {
 431                         if (j == cpu)
 432                                 continue;
 433                         d1 = tsc[cpu * 3 + 1] - tsc[j * 3];
 434                         d2 = tsc[cpu * 3 + 2] - tsc[j * 3 + 1];
 435                         if (d1 <= 0 || d2 <= 0) {
 436                                 smp_tsc = 0;
 437                                 return;
 438                         }
 439                 }
 440 }
 441
 442 static void
 443 adj_smp_tsc(void *arg)
 444 {
 445         uint64_t *tsc;
 446         int64_t d, min, max;
 447         u_int cpu = PCPU_GET(cpuid);
 448         u_int first, i, size;
 449
 450         first = CPU_FIRST();
 451         if (cpu == first)
 452                 return;
 453         min = INT64_MIN;
 454         max = INT64_MAX;
 455         size = (mp_maxid + 1) * 3;
 456         for (i = 0, tsc = arg; i < N; i++, tsc += size) {
 457                 d = tsc[first * 3] - tsc[cpu * 3 + 1];
 458                 if (d > min)
 459                         min = d;
 460                 d = tsc[first * 3 + 1] - tsc[cpu * 3 + 2];
 461                 if (d > min)
 462                         min = d;
 463                 d = tsc[first * 3 + 1] - tsc[cpu * 3];
 464                 if (d < max)
 465                         max = d;
 466                 d = tsc[first * 3 + 2] - tsc[cpu * 3 + 1];
 467                 if (d < max)
 468                         max = d;
 469         }
 470         if (min > max)
 471                 return;
 472         d = min / 2 + max / 2;
 473         __asm __volatile (
 474                 "movl $0x10, %%ecx\n\t"
 475                 "rdmsr\n\t"
 476                 "addl %%edi, %%eax\n\t"
 477                 "adcl %%esi, %%edx\n\t"
 478                 "wrmsr\n"
 479                 : /* No output */
 480                 : "D" ((uint32_t)d), "S" ((uint32_t)(d >> 32))
 481                 : "ax", "cx", "dx", "cc"
 482         );
 483 }
 484
 485 static int
 486 test_tsc(int adj_max_count)
 487 {
 488         uint64_t *data, *tsc;
 489         u_int i, size, adj;
 490
 491         if ((!smp_tsc && !tsc_is_invariant) || vm_guest)
 492                 return (-100);
 493         size = (mp_maxid + 1) * 3;
 494         data = malloc(sizeof(*data) * size * N, M_TEMP, M_WAITOK);
 495         adj = 0;
 496 retry:
 497         for (i = 0, tsc = data; i < N; i++, tsc += size)
 498                 smp_rendezvous(tsc_read_0, tsc_read_1, tsc_read_2, tsc);
 499         smp_tsc = 1;    /* XXX */
 500         smp_rendezvous(smp_no_rendezvous_barrier, comp_smp_tsc,
 501             smp_no_rendezvous_barrier, data);
 502         if (!smp_tsc && adj < adj_max_count) {
 503                 adj++;
 504                 smp_rendezvous(smp_no_rendezvous_barrier, adj_smp_tsc,
 505                     smp_no_rendezvous_barrier, data);
 506                 goto retry;
 507         }
 508         free(data, M_TEMP);
 509         if (bootverbose)
 510                 printf("SMP: %sed TSC synchronization test%s\n",
 511                     smp_tsc ? "pass" : "fail",
 512                     adj > 0 ? " after adjustment" : "");
 513         if (smp_tsc && tsc_is_invariant) {
 514                 switch (cpu_vendor_id) {
 515                 case CPU_VENDOR_AMD:
 516                         /*
 517                          * Starting with Family 15h processors, TSC clock
 518                          * source is in the north bridge.  Check whether
 519                          * we have a single-socket/multi-core platform.
 520                          * XXX Need more work for complex cases.
 521                          */
 522                         if (CPUID_TO_FAMILY(cpu_id) < 0x15 ||
 523                             (amd_feature2 & AMDID2_CMP) == 0 ||
 524                             smp_cpus > (cpu_procinfo2 & AMDID_CMP_CORES) + 1)
 525                                 break;
 526                         return (1000);
 527                 case CPU_VENDOR_INTEL:
 528                         /*
 529                          * XXX Assume Intel platforms have synchronized TSCs.
 530                          */
 531                         return (1000);
 532                 }
 533                 return (800);
 534         }
 535         return (-100);
 536 }
 537
 538 #undef N
 539
 540 #endif /* SMP */
 541
 542 static void
 543 init_TSC_tc(void)
 544 {
 545         uint64_t max_freq;
 546         int shift;
 547
 548         if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled)
 549                 return;
 550
 551         /*
 552          * Limit timecounter frequency to fit in an int and prevent it from
 553          * overflowing too fast.
 554          */
 555         max_freq = UINT_MAX;
 556
 557         /*
 558          * We can not use the TSC if we support APM.  Precise timekeeping
 559          * on an APM'ed machine is at best a fools pursuit, since
 560          * any and all of the time spent in various SMM code can't
 561          * be reliably accounted for.  Reading the RTC is your only
 562          * source of reliable time info.  The i8254 loses too, of course,
 563          * but we need to have some kind of time...
 564          * We don't know at this point whether APM is going to be used
 565          * or not, nor when it might be activated.  Play it safe.
 566          */
 567         if (power_pm_get_type() == POWER_PM_TYPE_APM) {
 568                 tsc_timecounter.tc_quality = -1000;
 569                 if (bootverbose)
 570                         printf("TSC timecounter disabled: APM enabled.\n");
 571                 goto init;
 572         }
 573
 574         /*
 575          * Intel CPUs without a C-state invariant TSC can stop the TSC
 576          * in either C2 or C3.  Disable use of C2 and C3 while using
 577          * the TSC as the timecounter.  The timecounter can be changed
 578          * to enable C2 and C3.
 579          *
 580          * Note that the TSC is used as the cputicker for computing
 581          * thread runtime regardless of the timecounter setting, so
 582          * using an alternate timecounter and enabling C2 or C3 can
 583          * result incorrect runtimes for kernel idle threads (but not
 584          * for any non-idle threads).
 585          */
 586         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
 587             (amd_pminfo & AMDPM_TSC_INVARIANT) == 0) {
 588                 tsc_timecounter.tc_flags |= TC_FLAGS_C2STOP;
 589                 if (bootverbose)
 590                         printf("TSC timecounter disables C2 and C3.\n");
 591         }
 592
 593         /*
 594          * We can not use the TSC in SMP mode unless the TSCs on all CPUs
 595          * are synchronized.  If the user is sure that the system has
 596          * synchronized TSCs, set kern.timecounter.smp_tsc tunable to a
 597          * non-zero value.  The TSC seems unreliable in virtualized SMP
 598          * environments, so it is set to a negative quality in those cases.
 599          */
 600 #ifdef SMP
 601         if (mp_ncpus > 1)
 602                 tsc_timecounter.tc_quality = test_tsc(smp_tsc_adjust);
 603         else
 604 #endif /* SMP */
 605         if (tsc_is_invariant)
 606                 tsc_timecounter.tc_quality = 1000;
 607         max_freq >>= tsc_shift;
 608
 609 init:
 610         for (shift = 0; shift <= 31 && (tsc_freq >> shift) > max_freq; shift++)
 611                 ;
 612         if ((cpu_feature & CPUID_SSE2) != 0 && mp_ncpus > 1) {
 613                 if (cpu_vendor_id == CPU_VENDOR_AMD) {
 614                         tsc_timecounter.tc_get_timecount = shift > 0 ?
 615                             tsc_get_timecount_low_mfence :
 616                             tsc_get_timecount_mfence;
 617                 } else {
 618                         tsc_timecounter.tc_get_timecount = shift > 0 ?
 619                             tsc_get_timecount_low_lfence :
 620                             tsc_get_timecount_lfence;
 621                 }
 622         } else {
 623                 tsc_timecounter.tc_get_timecount = shift > 0 ?
 624                     tsc_get_timecount_low : tsc_get_timecount;
 625         }
 626         if (shift > 0) {
 627                 tsc_timecounter.tc_name = "TSC-low";
 628                 if (bootverbose)
 629                         printf("TSC timecounter discards lower %d bit(s)\n",
 630                             shift);
 631         }
 632         if (tsc_freq != 0) {
 633                 tsc_timecounter.tc_frequency = tsc_freq >> shift;
 634                 tsc_timecounter.tc_priv = (void *)(intptr_t)shift;
 635                 tc_init(&tsc_timecounter);
 636         }
 637 }
 638 SYSINIT(tsc_tc, SI_SUB_SMP, SI_ORDER_ANY, init_TSC_tc, NULL);
 639
 640 void
 641 resume_TSC(void)
 642 {
 643 #ifdef SMP
 644         int quality;
 645
 646         /* If TSC was not good on boot, it is unlikely to become good now. */
 647         if (tsc_timecounter.tc_quality < 0)
 648                 return;
 649         /* Nothing to do with UP. */
 650         if (mp_ncpus < 2)
 651                 return;
 652
 653         /*
 654          * If TSC was good, a single synchronization should be enough,
 655          * but honour smp_tsc_adjust if it's set.
 656          */
 657         quality = test_tsc(MAX(smp_tsc_adjust, 1));
 658         if (quality != tsc_timecounter.tc_quality) {
 659                 printf("TSC timecounter quality changed: %d -> %d\n",
 660                     tsc_timecounter.tc_quality, quality);
 661                 tsc_timecounter.tc_quality = quality;
 662         }
 663 #endif /* SMP */
 664 }
 665
 666 /*
 667  * When cpufreq levels change, find out about the (new) max frequency.  We
 668  * use this to update CPU accounting in case it got a lower estimate at boot.
 669  */
 670 static void
 671 tsc_levels_changed(void *arg, int unit)
 672 {
 673         device_t cf_dev;
 674         struct cf_level *levels;
 675         int count, error;
 676         uint64_t max_freq;
 677
 678         /* Only use values from the first CPU, assuming all are equal. */
 679         if (unit != 0)
 680                 return;
 681
 682         /* Find the appropriate cpufreq device instance. */
 683         cf_dev = devclass_get_device(devclass_find("cpufreq"), unit);
 684         if (cf_dev == NULL) {
 685                 printf("tsc_levels_changed() called but no cpufreq device?\n");
 686                 return;
 687         }
 688
 689         /* Get settings from the device and find the max frequency. */
 690         count = 64;
 691         levels = malloc(count * sizeof(*levels), M_TEMP, M_NOWAIT);
 692         if (levels == NULL)
 693                 return;
 694         error = CPUFREQ_LEVELS(cf_dev, levels, &count);
 695         if (error == 0 && count != 0) {
 696                 max_freq = (uint64_t)levels[0].total_set.freq * 1000000;
 697                 set_cputicker(rdtsc, max_freq, 1);
 698         } else
 699                 printf("tsc_levels_changed: no max freq found\n");
 700         free(levels, M_TEMP);
 701 }
 702
 703 /*
 704  * If the TSC timecounter is in use, veto the pending change.  It may be
 705  * possible in the future to handle a dynamically-changing timecounter rate.
 706  */
 707 static void
 708 tsc_freq_changing(void *arg, const struct cf_level *level, int *status)
 709 {
 710
 711         if (*status != 0 || timecounter != &tsc_timecounter)
 712                 return;
 713
 714         printf("timecounter TSC must not be in use when "
 715             "changing frequencies; change denied\n");
 716         *status = EBUSY;
 717 }
 718
 719 /* Update TSC freq with the value indicated by the caller. */
 720 static void
 721 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
 722 {
 723         uint64_t freq;
 724
 725         /* If there was an error during the transition, don't do anything. */
 726         if (tsc_disabled || status != 0)
 727                 return;
 728
 729         /* Total setting for this level gives the new frequency in MHz. */
 730         freq = (uint64_t)level->total_set.freq * 1000000;
 731         atomic_store_rel_64(&tsc_freq, freq);
 732         tsc_timecounter.tc_frequency =
 733             freq >> (int)(intptr_t)tsc_timecounter.tc_priv;
 734 }
 735
 736 static int
 737 sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
 738 {
 739         int error;
 740         uint64_t freq;
 741
 742         freq = atomic_load_acq_64(&tsc_freq);
 743         if (freq == 0)
 744                 return (EOPNOTSUPP);
 745         error = sysctl_handle_64(oidp, &freq, 0, req);
 746         if (error == 0 && req->newptr != NULL) {
 747                 atomic_store_rel_64(&tsc_freq, freq);
 748                 atomic_store_rel_64(&tsc_timecounter.tc_frequency,
 749                     freq >> (int)(intptr_t)tsc_timecounter.tc_priv);
 750         }
 751         return (error);
 752 }
 753
 754 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_U64 | CTLFLAG_RW,
 755     0, 0, sysctl_machdep_tsc_freq, "QU", "Time Stamp Counter frequency");
 756
 757 static u_int
 758 tsc_get_timecount(struct timecounter *tc __unused)
 759 {
 760
 761         return (rdtsc32());
 762 }
 763
 764 static inline u_int
 765 tsc_get_timecount_low(struct timecounter *tc)
 766 {
 767         uint32_t rv;
 768
 769         __asm __volatile("rdtsc; shrd %%cl, %%edx, %0"
 770             : "=a" (rv) : "c" ((int)(intptr_t)tc->tc_priv) : "edx");
 771         return (rv);
 772 }
 773
 774 static u_int
 775 tsc_get_timecount_lfence(struct timecounter *tc __unused)
 776 {
 777
 778         lfence();
 779         return (rdtsc32());
 780 }
 781
 782 static u_int
 783 tsc_get_timecount_low_lfence(struct timecounter *tc)
 784 {
 785
 786         lfence();
 787         return (tsc_get_timecount_low(tc));
 788 }
 789
 790 static u_int
 791 tsc_get_timecount_mfence(struct timecounter *tc __unused)
 792 {
 793
 794         mfence();
 795         return (rdtsc32());
 796 }
 797
 798 static u_int
 799 tsc_get_timecount_low_mfence(struct timecounter *tc)
 800 {
 801
 802         mfence();
 803         return (tsc_get_timecount_low(tc));
 804 }
 805
 806 static uint32_t
 807 x86_tsc_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc)
 808 {
 809
 810         vdso_th->th_algo = VDSO_TH_ALGO_X86_TSC;
 811         vdso_th->th_x86_shift = (int)(intptr_t)tc->tc_priv;
 812         vdso_th->th_x86_hpet_idx = 0xffffffff;
 813         bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
 814         return (1);
 815 }
 816
 817 #ifdef COMPAT_FREEBSD32
 818 static uint32_t
 819 x86_tsc_vdso_timehands32(struct vdso_timehands32 *vdso_th32,
 820     struct timecounter *tc)
 821 {
 822
 823         vdso_th32->th_algo = VDSO_TH_ALGO_X86_TSC;
 824         vdso_th32->th_x86_shift = (int)(intptr_t)tc->tc_priv;
 825         vdso_th32->th_x86_hpet_idx = 0xffffffff;
 826         bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res));
 827         return (1);
 828 }
 829 #endif