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23 #ifndef __XEN_PUBLIC_ARCH_X86_PMU_H__
24 #define __XEN_PUBLIC_ARCH_X86_PMU_H__
26 /* x86-specific PMU definitions */
28 /* AMD PMU registers and structures */
29 struct xen_pmu_amd_ctxt {
31 * Offsets to counter and control MSRs (relative to xen_pmu_arch.c.amd).
32 * For PV(H) guests these fields are RO.
38 #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
40 #elif defined(__GNUC__)
44 typedef struct xen_pmu_amd_ctxt xen_pmu_amd_ctxt_t;
45 DEFINE_XEN_GUEST_HANDLE(xen_pmu_amd_ctxt_t);
47 /* Intel PMU registers and structures */
48 struct xen_pmu_cntr_pair {
52 typedef struct xen_pmu_cntr_pair xen_pmu_cntr_pair_t;
53 DEFINE_XEN_GUEST_HANDLE(xen_pmu_cntr_pair_t);
55 struct xen_pmu_intel_ctxt {
57 * Offsets to fixed and architectural counter MSRs (relative to
58 * xen_pmu_arch.c.intel).
59 * For PV(H) guests these fields are RO.
61 uint32_t fixed_counters;
62 uint32_t arch_counters;
66 uint64_t global_ovf_ctrl;
67 uint64_t global_status;
73 /* Fixed and architectural counter MSRs */
74 #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
76 #elif defined(__GNUC__)
80 typedef struct xen_pmu_intel_ctxt xen_pmu_intel_ctxt_t;
81 DEFINE_XEN_GUEST_HANDLE(xen_pmu_intel_ctxt_t);
83 /* Sampled domain's registers */
93 typedef struct xen_pmu_regs xen_pmu_regs_t;
94 DEFINE_XEN_GUEST_HANDLE(xen_pmu_regs_t);
97 #define PMU_CACHED (1<<0) /* PMU MSRs are cached in the context */
98 #define PMU_SAMPLE_USER (1<<1) /* Sample is from user or kernel mode */
99 #define PMU_SAMPLE_REAL (1<<2) /* Sample is from realmode */
100 #define PMU_SAMPLE_PV (1<<3) /* Sample from a PV guest */
103 * Architecture-specific information describing state of the processor at
104 * the time of PMU interrupt.
105 * Fields of this structure marked as RW for guest should only be written by
106 * the guest when PMU_CACHED bit in pmu_flags is set (which is done by the
107 * hypervisor during PMU interrupt). Hypervisor will read updated data in
108 * XENPMU_flush hypercall and clear PMU_CACHED bit.
110 struct xen_pmu_arch {
113 * Processor's registers at the time of interrupt.
114 * WO for hypervisor, RO for guests.
116 struct xen_pmu_regs regs;
117 /* Padding for adding new registers to xen_pmu_regs in the future */
118 #define XENPMU_REGS_PAD_SZ 64
119 uint8_t pad[XENPMU_REGS_PAD_SZ];
122 /* WO for hypervisor, RO for guest */
126 * APIC LVTPC register.
127 * RW for both hypervisor and guest.
128 * Only APIC_LVT_MASKED bit is loaded by the hypervisor into hardware
129 * during XENPMU_flush or XENPMU_lvtpc_set.
132 uint32_t lapic_lvtpc;
137 * Vendor-specific PMU registers.
138 * RW for both hypervisor and guest (see exceptions above).
139 * Guest's updates to this field are verified and then loaded by the
140 * hypervisor into hardware during XENPMU_flush
143 struct xen_pmu_amd_ctxt amd;
144 struct xen_pmu_intel_ctxt intel;
147 * Padding for contexts (fixed parts only, does not include MSR banks
148 * that are specified by offsets)
150 #define XENPMU_CTXT_PAD_SZ 128
151 uint8_t pad[XENPMU_CTXT_PAD_SZ];
154 typedef struct xen_pmu_arch xen_pmu_arch_t;
155 DEFINE_XEN_GUEST_HANDLE(xen_pmu_arch_t);
157 #endif /* __XEN_PUBLIC_ARCH_X86_PMU_H__ */
161 * c-file-style: "BSD"
164 * indent-tabs-mode: nil