1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 declare <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64>)
5 define <1 x i64> @test_addp_v1i64(<2 x i64> %a) {
6 ; CHECK: test_addp_v1i64:
7 %val = call <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64> %a)
8 ; CHECK: addp d0, v0.2d
12 declare <1 x float> @llvm.aarch64.neon.vpfadd(<2 x float>)
14 define <1 x float> @test_faddp_v1f32(<2 x float> %a) {
15 ; CHECK: test_faddp_v1f32:
16 %val = call <1 x float> @llvm.aarch64.neon.vpfadd(<2 x float> %a)
17 ; CHECK: faddp s0, v0.2s
21 declare <1 x double> @llvm.aarch64.neon.vpfaddq(<2 x double>)
23 define <1 x double> @test_faddp_v1f64(<2 x double> %a) {
24 ; CHECK: test_faddp_v1f64:
25 %val = call <1 x double> @llvm.aarch64.neon.vpfaddq(<2 x double> %a)
26 ; CHECK: faddp d0, v0.2d
31 declare <1 x float> @llvm.aarch64.neon.vpmax(<2 x float>)
33 define <1 x float> @test_fmaxp_v1f32(<2 x float> %a) {
34 ; CHECK: test_fmaxp_v1f32:
35 %val = call <1 x float> @llvm.aarch64.neon.vpmax(<2 x float> %a)
36 ; CHECK: fmaxp s0, v0.2s
40 declare <1 x double> @llvm.aarch64.neon.vpmaxq(<2 x double>)
42 define <1 x double> @test_fmaxp_v1f64(<2 x double> %a) {
43 ; CHECK: test_fmaxp_v1f64:
44 %val = call <1 x double> @llvm.aarch64.neon.vpmaxq(<2 x double> %a)
45 ; CHECK: fmaxp d0, v0.2d
50 declare <1 x float> @llvm.aarch64.neon.vpmin(<2 x float>)
52 define <1 x float> @test_fminp_v1f32(<2 x float> %a) {
53 ; CHECK: test_fminp_v1f32:
54 %val = call <1 x float> @llvm.aarch64.neon.vpmin(<2 x float> %a)
55 ; CHECK: fminp s0, v0.2s
59 declare <1 x double> @llvm.aarch64.neon.vpminq(<2 x double>)
61 define <1 x double> @test_fminp_v1f64(<2 x double> %a) {
62 ; CHECK: test_fminp_v1f64:
63 %val = call <1 x double> @llvm.aarch64.neon.vpminq(<2 x double> %a)
64 ; CHECK: fminp d0, v0.2d
68 declare <1 x float> @llvm.aarch64.neon.vpfmaxnm(<2 x float>)
70 define <1 x float> @test_fmaxnmp_v1f32(<2 x float> %a) {
71 ; CHECK: test_fmaxnmp_v1f32:
72 %val = call <1 x float> @llvm.aarch64.neon.vpfmaxnm(<2 x float> %a)
73 ; CHECK: fmaxnmp s0, v0.2s
77 declare <1 x double> @llvm.aarch64.neon.vpfmaxnmq(<2 x double>)
79 define <1 x double> @test_fmaxnmp_v1f64(<2 x double> %a) {
80 ; CHECK: test_fmaxnmp_v1f64:
81 %val = call <1 x double> @llvm.aarch64.neon.vpfmaxnmq(<2 x double> %a)
82 ; CHECK: fmaxnmp d0, v0.2d
86 declare <1 x float> @llvm.aarch64.neon.vpfminnm(<2 x float>)
88 define <1 x float> @test_fminnmp_v1f32(<2 x float> %a) {
89 ; CHECK: test_fminnmp_v1f32:
90 %val = call <1 x float> @llvm.aarch64.neon.vpfminnm(<2 x float> %a)
91 ; CHECK: fminnmp s0, v0.2s
95 declare <1 x double> @llvm.aarch64.neon.vpfminnmq(<2 x double>)
97 define <1 x double> @test_fminnmp_v1f64(<2 x double> %a) {
98 ; CHECK: test_fminnmp_v1f64:
99 %val = call <1 x double> @llvm.aarch64.neon.vpfminnmq(<2 x double> %a)
100 ; CHECK: fminnmp d0, v0.2d
101 ret <1 x double> %val
104 define float @test_vaddv_f32(<2 x float> %a) {
105 ; CHECK-LABEL: test_vaddv_f32
106 ; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
107 %1 = tail call <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v2f32(<2 x float> %a)
108 %2 = extractelement <1 x float> %1, i32 0
112 define float @test_vaddvq_f32(<4 x float> %a) {
113 ; CHECK-LABEL: test_vaddvq_f32
114 ; CHECK: faddp {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
115 ; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
116 %1 = tail call <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v4f32(<4 x float> %a)
117 %2 = extractelement <1 x float> %1, i32 0
121 define double @test_vaddvq_f64(<2 x double> %a) {
122 ; CHECK-LABEL: test_vaddvq_f64
123 ; CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
124 %1 = tail call <1 x double> @llvm.aarch64.neon.vaddv.v1f64.v2f64(<2 x double> %a)
125 %2 = extractelement <1 x double> %1, i32 0
129 define float @test_vmaxv_f32(<2 x float> %a) {
130 ; CHECK-LABEL: test_vmaxv_f32
131 ; CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
132 %1 = tail call <1 x float> @llvm.aarch64.neon.vmaxv.v1f32.v2f32(<2 x float> %a)
133 %2 = extractelement <1 x float> %1, i32 0
137 define double @test_vmaxvq_f64(<2 x double> %a) {
138 ; CHECK-LABEL: test_vmaxvq_f64
139 ; CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
140 %1 = tail call <1 x double> @llvm.aarch64.neon.vmaxv.v1f64.v2f64(<2 x double> %a)
141 %2 = extractelement <1 x double> %1, i32 0
145 define float @test_vminv_f32(<2 x float> %a) {
146 ; CHECK-LABEL: test_vminv_f32
147 ; CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
148 %1 = tail call <1 x float> @llvm.aarch64.neon.vminv.v1f32.v2f32(<2 x float> %a)
149 %2 = extractelement <1 x float> %1, i32 0
153 define double @test_vminvq_f64(<2 x double> %a) {
154 ; CHECK-LABEL: test_vminvq_f64
155 ; CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
156 %1 = tail call <1 x double> @llvm.aarch64.neon.vminv.v1f64.v2f64(<2 x double> %a)
157 %2 = extractelement <1 x double> %1, i32 0
161 define double @test_vmaxnmvq_f64(<2 x double> %a) {
162 ; CHECK-LABEL: test_vmaxnmvq_f64
163 ; CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
164 %1 = tail call <1 x double> @llvm.aarch64.neon.vmaxnmv.v1f64.v2f64(<2 x double> %a)
165 %2 = extractelement <1 x double> %1, i32 0
169 define float @test_vmaxnmv_f32(<2 x float> %a) {
170 ; CHECK-LABEL: test_vmaxnmv_f32
171 ; CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
172 %1 = tail call <1 x float> @llvm.aarch64.neon.vmaxnmv.v1f32.v2f32(<2 x float> %a)
173 %2 = extractelement <1 x float> %1, i32 0
177 define double @test_vminnmvq_f64(<2 x double> %a) {
178 ; CHECK-LABEL: test_vminnmvq_f64
179 ; CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
180 %1 = tail call <1 x double> @llvm.aarch64.neon.vminnmv.v1f64.v2f64(<2 x double> %a)
181 %2 = extractelement <1 x double> %1, i32 0
185 define float @test_vminnmv_f32(<2 x float> %a) {
186 ; CHECK-LABEL: test_vminnmv_f32
187 ; CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
188 %1 = tail call <1 x float> @llvm.aarch64.neon.vminnmv.v1f32.v2f32(<2 x float> %a)
189 %2 = extractelement <1 x float> %1, i32 0
193 define <2 x i64> @test_vpaddq_s64(<2 x i64> %a, <2 x i64> %b) {
194 ; CHECK-LABEL: test_vpaddq_s64
195 ; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
196 %1 = tail call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
200 define <2 x i64> @test_vpaddq_u64(<2 x i64> %a, <2 x i64> %b) {
201 ; CHECK-LABEL: test_vpaddq_u64
202 ; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
203 %1 = tail call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
207 define i64 @test_vaddvq_s64(<2 x i64> %a) {
208 ; CHECK-LABEL: test_vaddvq_s64
209 ; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
210 %1 = tail call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
211 %2 = extractelement <1 x i64> %1, i32 0
215 define i64 @test_vaddvq_u64(<2 x i64> %a) {
216 ; CHECK-LABEL: test_vaddvq_u64
217 ; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
218 %1 = tail call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
219 %2 = extractelement <1 x i64> %1, i32 0
223 declare <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64>)
225 declare <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64>, <2 x i64>)
227 declare <1 x float> @llvm.aarch64.neon.vminnmv.v1f32.v2f32(<2 x float>)
229 declare <1 x double> @llvm.aarch64.neon.vminnmv.v1f64.v2f64(<2 x double>)
231 declare <1 x float> @llvm.aarch64.neon.vmaxnmv.v1f32.v2f32(<2 x float>)
233 declare <1 x double> @llvm.aarch64.neon.vmaxnmv.v1f64.v2f64(<2 x double>)
235 declare <1 x double> @llvm.aarch64.neon.vminv.v1f64.v2f64(<2 x double>)
237 declare <1 x float> @llvm.aarch64.neon.vminv.v1f32.v2f32(<2 x float>)
239 declare <1 x double> @llvm.aarch64.neon.vmaxv.v1f64.v2f64(<2 x double>)
241 declare <1 x float> @llvm.aarch64.neon.vmaxv.v1f32.v2f32(<2 x float>)
243 declare <1 x double> @llvm.aarch64.neon.vaddv.v1f64.v2f64(<2 x double>)
245 declare <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v4f32(<4 x float>)
247 declare <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v2f32(<2 x float>)