1 ; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3 ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
5 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
7 define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
8 ; GCN-LABEL: {{^}}trunc_i64_to_i32_store:
9 ; GCN: s_load_dword [[SLOAD:s[0-9]+]], s[0:1],
10 ; GCN: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
11 ; SI: buffer_store_dword [[VLOAD]]
12 ; VI: flat_store_dword v[{{[0-9:]+}}], [[VLOAD]]
14 ; EG-LABEL: {{^}}trunc_i64_to_i32_store:
15 ; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
19 %result = trunc i64 %in to i32 store i32 %result, i32 addrspace(1)* %out, align 4
23 ; GCN-LABEL: {{^}}trunc_load_shl_i64:
24 ; GCN-DAG: s_load_dwordx2
25 ; GCN-DAG: s_load_dword [[SREG:s[0-9]+]],
26 ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
27 ; GCN: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
28 ; SI: buffer_store_dword [[VSHL]]
29 ; VI: flat_store_dword v[{{[0-9:]+}}], [[VSHL]]
31 define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) {
33 %result = trunc i64 %b to i32
34 store i32 %result, i32 addrspace(1)* %out, align 4
38 ; GCN-LABEL: {{^}}trunc_shl_i64:
39 ; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
40 ; VI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
41 ; GCN: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
42 ; GCN: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
43 ; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
45 ; SI: buffer_store_dword v[[LO_VREG]],
46 ; VI: flat_store_dword v[{{[0-9:]+}}], v[[LO_VREG]]
49 define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {
50 %aa = add i64 %a, 234 ; Prevent shrinking store.
52 %result = trunc i64 %b to i32
53 store i32 %result, i32 addrspace(1)* %out, align 4
54 store i64 %b, i64 addrspace(1)* %out2, align 8 ; Prevent reducing ops to 32-bits
58 ; GCN-LABEL: {{^}}trunc_i32_to_i1:
59 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
61 define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {
62 %a = load i32, i32 addrspace(1)* %ptr, align 4
63 %trunc = trunc i32 %a to i1
64 %result = select i1 %trunc, i32 1, i32 0
65 store i32 %result, i32 addrspace(1)* %out, align 4
69 ; GCN-LABEL: {{^}}trunc_i8_to_i1:
70 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
72 define void @trunc_i8_to_i1(i8 addrspace(1)* %out, i8 addrspace(1)* %ptr) {
73 %a = load i8, i8 addrspace(1)* %ptr, align 4
74 %trunc = trunc i8 %a to i1
75 %result = select i1 %trunc, i8 1, i8 0
76 store i8 %result, i8 addrspace(1)* %out, align 4
80 ; GCN-LABEL: {{^}}sgpr_trunc_i16_to_i1:
81 ; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}
83 define void @sgpr_trunc_i16_to_i1(i16 addrspace(1)* %out, i16 %a) {
84 %trunc = trunc i16 %a to i1
85 %result = select i1 %trunc, i16 1, i16 0
86 store i16 %result, i16 addrspace(1)* %out, align 4
90 ; GCN-LABEL: {{^}}sgpr_trunc_i32_to_i1:
91 ; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}
93 define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
94 %trunc = trunc i32 %a to i1
95 %result = select i1 %trunc, i32 1, i32 0
96 store i32 %result, i32 addrspace(1)* %out, align 4
100 ; GCN-LABEL: {{^}}s_trunc_i64_to_i1:
101 ; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb
102 ; VI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x2c
103 ; GCN: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]
104 ; GCN: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}
105 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]
106 define void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 %x) {
107 %trunc = trunc i64 %x to i1
108 %sel = select i1 %trunc, i32 63, i32 -12
109 store i32 %sel, i32 addrspace(1)* %out
113 ; GCN-LABEL: {{^}}v_trunc_i64_to_i1:
114 ; SI: buffer_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
115 ; VI: flat_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
116 ; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
117 ; GCN: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]
118 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
119 define void @v_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {
120 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
121 %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
122 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
123 %x = load i64, i64 addrspace(1)* %gep
125 %trunc = trunc i64 %x to i1
126 %sel = select i1 %trunc, i32 63, i32 -12
127 store i32 %sel, i32 addrspace(1)* %out.gep