1 ; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s
2 ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s
4 ; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
5 ; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
7 ; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW %s
8 ; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW %s
10 ; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW %s
11 ; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW %s
13 ; Test the effect of varargs on floating point types in the non-variable part
14 ; of the argument list as specified by section 2 of the MIPSpro N32 Handbook.
16 ; N32/N64 are almost identical in this area so many of their checks have been
17 ; combined into the 'NEW' prefix (the N stands for New).
19 ; On O32, varargs prevents all FPU argument register usage. This contradicts
20 ; the N32 handbook, but agrees with the SYSV ABI and GCC's behaviour.
22 @floats = global [11 x float] zeroinitializer
23 @doubles = global [11 x double] zeroinitializer
25 define void @double_args(double %a, ...)
28 %0 = getelementptr [11 x double]* @doubles, i32 0, i32 1
29 store volatile double %a, double* %0
32 %ap2 = bitcast i8** %ap to i8*
33 call void @llvm.va_start(i8* %ap2)
34 %b = va_arg i8** %ap, double
35 %1 = getelementptr [11 x double]* @doubles, i32 0, i32 2
36 store volatile double %b, double* %1
40 ; ALL-LABEL: double_args:
41 ; We won't test the way the global address is calculated in this test. This is
42 ; just to get the register number for the other checks.
43 ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
44 ; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(doubles)(
46 ; O32 forbids using floating point registers for the non-variable portion.
48 ; O32BE-DAG: mtc1 $5, [[FTMP1:\$f[0-9]*[02468]+]]
49 ; O32BE-DAG: mtc1 $4, [[FTMP2:\$f[0-9]*[13579]+]]
50 ; O32LE-DAG: mtc1 $4, [[FTMP1:\$f[0-9]*[02468]+]]
51 ; O32LE-DAG: mtc1 $5, [[FTMP2:\$f[0-9]*[13579]+]]
52 ; O32-DAG: sdc1 [[FTMP1]], 8([[R2]])
53 ; NEW-DAG: sdc1 $f12, 8([[R2]])
55 ; The varargs portion is dumped to stack
56 ; O32-DAG: sw $6, 16($sp)
57 ; O32-DAG: sw $7, 20($sp)
58 ; NEW-DAG: sd $5, 8($sp)
59 ; NEW-DAG: sd $6, 16($sp)
60 ; NEW-DAG: sd $7, 24($sp)
61 ; NEW-DAG: sd $8, 32($sp)
62 ; NEW-DAG: sd $9, 40($sp)
63 ; NEW-DAG: sd $10, 48($sp)
64 ; NEW-DAG: sd $11, 56($sp)
66 ; Get the varargs pointer
67 ; O32 has 4 bytes padding, 4 bytes for the varargs pointer, and 8 bytes reserved
68 ; for arguments 1 and 2.
69 ; N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
70 ; O32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 16
71 ; O32-DAG: sw [[VAPTR]], 4($sp)
72 ; N32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 8
73 ; N32-DAG: sw [[VAPTR]], 4($sp)
74 ; N64-DAG: daddiu [[VAPTR:\$[0-9]+]], $sp, 8
75 ; N64-DAG: sd [[VAPTR]], 0($sp)
77 ; Increment the pointer then get the varargs arg
78 ; LLVM will rebind the load to the stack pointer instead of the varargs pointer
79 ; during lowering. This is fine and doesn't change the behaviour.
80 ; O32-DAG: addiu [[VAPTR]], [[VAPTR]], 8
81 ; O32-DAG: sw [[VAPTR]], 4($sp)
82 ; N32-DAG: addiu [[VAPTR]], [[VAPTR]], 8
83 ; N32-DAG: sw [[VAPTR]], 4($sp)
84 ; N64-DAG: daddiu [[VAPTR]], [[VAPTR]], 8
85 ; N64-DAG: sd [[VAPTR]], 0($sp)
86 ; O32-DAG: ldc1 [[FTMP1:\$f[0-9]+]], 16($sp)
87 ; NEW-DAG: ldc1 [[FTMP1:\$f[0-9]+]], 8($sp)
88 ; ALL-DAG: sdc1 [[FTMP1]], 16([[R2]])
90 define void @float_args(float %a, ...) nounwind {
92 %0 = getelementptr [11 x float]* @floats, i32 0, i32 1
93 store volatile float %a, float* %0
96 %ap2 = bitcast i8** %ap to i8*
97 call void @llvm.va_start(i8* %ap2)
98 %b = va_arg i8** %ap, float
99 %1 = getelementptr [11 x float]* @floats, i32 0, i32 2
100 store volatile float %b, float* %1
104 ; ALL-LABEL: float_args:
105 ; We won't test the way the global address is calculated in this test. This is
106 ; just to get the register number for the other checks.
107 ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
108 ; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(floats)(
110 ; The first four arguments are the same in O32/N32/N64.
111 ; The non-variable portion should be unaffected.
112 ; O32-DAG: sw $4, 4([[R2]])
113 ; NEW-DAG: swc1 $f12, 4([[R2]])
115 ; The varargs portion is dumped to stack
116 ; O32-DAG: sw $5, 12($sp)
117 ; O32-DAG: sw $6, 16($sp)
118 ; O32-DAG: sw $7, 20($sp)
119 ; NEW-DAG: sd $5, 8($sp)
120 ; NEW-DAG: sd $6, 16($sp)
121 ; NEW-DAG: sd $7, 24($sp)
122 ; NEW-DAG: sd $8, 32($sp)
123 ; NEW-DAG: sd $9, 40($sp)
124 ; NEW-DAG: sd $10, 48($sp)
125 ; NEW-DAG: sd $11, 56($sp)
127 ; Get the varargs pointer
128 ; O32 has 4 bytes padding, 4 bytes for the varargs pointer, and should have 8
129 ; bytes reserved for arguments 1 and 2 (the first float arg) but as discussed in
130 ; arguments-float.ll, GCC doesn't agree with MD00305 and treats floats as 4
131 ; bytes so we only have 12 bytes total.
132 ; N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
133 ; O32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 12
134 ; O32-DAG: sw [[VAPTR]], 4($sp)
135 ; N32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 8
136 ; N32-DAG: sw [[VAPTR]], 4($sp)
137 ; N64-DAG: daddiu [[VAPTR:\$[0-9]+]], $sp, 8
138 ; N64-DAG: sd [[VAPTR]], 0($sp)
140 ; Increment the pointer then get the varargs arg
141 ; LLVM will rebind the load to the stack pointer instead of the varargs pointer
142 ; during lowering. This is fine and doesn't change the behaviour.
143 ; N32/N64 is using ori instead of addiu/daddiu but (although odd) this is fine
144 ; since the stack is always aligned.
145 ; O32-DAG: addiu [[VAPTR]], [[VAPTR]], 4
146 ; O32-DAG: sw [[VAPTR]], 4($sp)
147 ; N32-DAG: ori [[VAPTR]], [[VAPTR]], 4
148 ; N32-DAG: sw [[VAPTR]], 4($sp)
149 ; N64-DAG: ori [[VAPTR]], [[VAPTR]], 4
150 ; N64-DAG: sd [[VAPTR]], 0($sp)
151 ; O32-DAG: lwc1 [[FTMP1:\$f[0-9]+]], 12($sp)
152 ; NEW-DAG: lwc1 [[FTMP1:\$f[0-9]+]], 8($sp)
153 ; ALL-DAG: swc1 [[FTMP1]], 8([[R2]])
155 declare void @llvm.va_start(i8*)
156 declare void @llvm.va_copy(i8*, i8*)
157 declare void @llvm.va_end(i8*)