1 ; RUN: llc -relocation-model=pic -march=mipsel -mcpu=mips32r5 \
2 ; RUN: -mattr=+fp64,+msa < %s | FileCheck %s \
3 ; RUN: --check-prefixes=ALL,MIPS32,MIPSR5,MIPS32-O32,MIPS32R5-O32
4 ; RUN: llc -relocation-model=pic -march=mips64el -mcpu=mips64r5 \
5 ; RUN: -mattr=+fp64,+msa -target-abi n32 < %s | FileCheck %s \
6 ; RUN: --check-prefixes=ALL,MIPS64,MIPSR5,MIPS64-N32,MIPS64R5-N32
7 ; RUN: llc -relocation-model=pic -march=mips64el -mcpu=mips64r5 \
8 ; RUN: -mattr=+fp64,+msa -target-abi n64 < %s | FileCheck %s \
9 ; RUN: --check-prefixes=ALL,MIPS64,MIPSR5,MIPS64-N64,MIPS64R5-N64
11 ; RUN: llc -relocation-model=pic -march=mipsel -mcpu=mips32r6 \
12 ; RUN: -mattr=+fp64,+msa < %s | FileCheck %s \
13 ; RUN: --check-prefixes=ALL,MIPS32,MIPSR6,MIPSR6-O32
14 ; RUN: llc -relocation-model=pic -march=mips64el -mcpu=mips64r6 \
15 ; RUN: -mattr=+fp64,+msa -target-abi n32 < %s | FileCheck %s \
16 ; RUN: --check-prefixes=ALL,MIPS64,MIPSR6,MIPS64-N32,MIPSR6-N32
17 ; RUN: llc -relocation-model=pic -march=mips64el -mcpu=mips64r6 \
18 ; RUN: -mattr=+fp64,+msa -target-abi n64 < %s | FileCheck %s \
19 ; RUN: --check-prefixes=ALL,MIPS64,MIPSR6,MIPS64-N64,MIPSR6-N64
22 ; Check the use of frame indexes in the msa pseudo f16 instructions.
24 @k = external global float
26 declare float @k2(half *)
28 define void @f3(i16 %b) {
32 ; ALL: sh $4, [[O0:[0-9]+]]($sp)
34 ; MIPS32-DAG: addiu $4, $sp, [[O0]]
35 ; MIPS64-N32: addiu $4, $sp, [[O0]]
36 ; MIPS64-N64: daddiu $4, $sp, [[O0]]
40 %1 = bitcast i16 %b to half
41 store half %1, half * %0
42 %2 = call float @k2(half * %0)
43 store float %2, float * @k
47 define void @f(i16 %b) {
50 ; ALL: sh $4, [[O0:[0-9]+]]($sp)
51 ; ALL: lh $[[R0:[0-9]+]], [[O0]]($sp)
52 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
53 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
54 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
55 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
58 %1 = bitcast i16 %b to half
59 %2 = fpext half %1 to float
60 store float %2, float * @k
64 @g = external global i16, align 2
65 @h = external global half, align 2
67 ; Check that fext f16 to double has a fexupr.w, fexupr.d sequence.
68 ; Check that ftrunc double to f16 has fexdo.w, fexdo.h sequence.
69 ; Check that MIPS64R5+ uses 64-bit floating point <-> 64-bit GPR transfers.
71 ; We don't need to check if pre-MIPSR5 expansions occur, the MSA ASE requires
72 ; MIPSR5. Additionally, fp64 mode / FR=1 is required to use MSA.
74 define void @fadd_f64() {
76 ; ALL-LABEL: fadd_f64:
77 %0 = load half, half * @h, align 2
78 %1 = fpext half %0 to double
79 ; ALL: lh $[[R0:[0-9]+]]
80 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
81 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
82 ; ALL: fexupr.d $w[[W2:[0-9]+]], $w[[W1]]
83 ; MIPS32: copy_s.w $[[R1:[0-9]+]], $w[[W2]][0]
84 ; MIPS32: mtc1 $[[R1]], $f[[F0:[0-9]+]]
85 ; MIPS32: copy_s.w $[[R2:[0-9]+]], $w[[W2]][1]
86 ; MIPS32: mthc1 $[[R2]], $f[[F0]]
87 ; MIPS64: copy_s.d $[[R2:[0-9]+]], $w[[W2]][0]
88 ; MIPS64: dmtc1 $[[R2]], $f[[F0:[0-9]+]]
90 %2 = load half, half * @h, align 2
91 %3 = fpext half %2 to double
92 %add = fadd double %1, %3
94 ; ALL: add.d $f[[F1:[0-9]+]], $f[[F0]], $f[[F0]]
96 %4 = fptrunc double %add to half
98 ; MIPS32: mfc1 $[[R2:[0-9]+]], $f[[F1]]
99 ; MIPS32: fill.w $w[[W2:[0-9]+]], $[[R2]]
100 ; MIPS32: mfhc1 $[[R3:[0-9]+]], $f[[F1]]
101 ; MIPS32: insert.w $w[[W2]][1], $[[R3]]
102 ; MIPS32: insert.w $w[[W2]][3], $[[R3]]
104 ; MIPS64: dmfc1 $[[R2:[0-9]+]], $f[[F1]]
105 ; MIPS64: fill.d $w[[W2:[0-9]+]], $[[R2]]
107 ; ALL: fexdo.w $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
108 ; ALL: fexdo.h $w[[W4:[0-9]+]], $w[[W3]], $w[[W3]]
109 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W4]][0]
111 store half %4, half * @h, align 2
115 define i32 @ffptoui() {
117 ; ALL-LABEL: ffptoui:
118 %0 = load half, half * @h, align 2
119 %1 = fptoui half %0 to i32
121 ; MIPS32: lwc1 $f[[FC:[0-9]+]], %lo($CPI{{[0-9]+}}_{{[0-9]+}})
122 ; MIPS64-N32: lwc1 $f[[FC:[0-9]+]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
123 ; MIPS64-N64: lwc1 $f[[FC:[0-9]+]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
125 ; ALL: lh $[[R0:[0-9]+]]
126 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
127 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
128 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
129 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
130 ; MIPSR6: cmp.lt.s $f[[F1:[0-9]+]], $f[[F0]], $f[[FC]]
131 ; ALL: sub.s $f[[F2:[0-9]+]], $f[[F0]], $f[[FC]]
132 ; ALL: mfc1 $[[R2:[0-9]]], $f[[F2]]
133 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
134 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
135 ; ALL: fexupr.w $w[[W4:[0-9]+]], $w[[W3]]
136 ; ALL: fexupr.d $w[[W5:[0-9]+]], $w[[W4]]
138 ; MIPS32: copy_s.w $[[R3:[0-9]+]], $w[[W5]][0]
139 ; MIPS32: mtc1 $[[R3]], $f[[F3:[0-9]+]]
140 ; MIPS32: copy_s.w $[[R4:[0-9]+]], $w[[W5]][1]
141 ; MIPS32: mthc1 $[[R3]], $f[[F3]]
143 ; MIPS64: copy_s.d $[[R2:[0-9]+]], $w[[W2]][0]
144 ; MIPS64: dmtc1 $[[R2]], $f[[F3:[0-9]+]]
146 ; ALL: trunc.w.d $f[[F4:[0-9]+]], $f[[F3]]
147 ; ALL: mfc1 $[[R4:[0-9]+]], $f[[F4]]
148 ; ALL: fexupr.d $w[[W6:[0-9]+]], $w[[W1]]
150 ; MIPS32: copy_s.w $[[R5:[0-9]+]], $w[[W6]][0]
151 ; MIPS32: mtc1 $[[R5]], $f[[F5:[0-9]+]]
152 ; MIPS32: copy_s.w $[[R6:[0-9]+]], $w[[W6]][1]
153 ; MIPS32: mthc1 $[[R6]], $f[[F5]]
155 ; MIPS64: copy_s.d $[[R2:[0-9]+]], $w[[W2]][0]
156 ; MIPS64: dmtc1 $[[R2]], $f[[F5:[0-9]+]]
158 ; ALL: trunc.w.d $f[[F6:[0-9]]], $f[[F5]]
159 ; ALL: mfc1 $[[R7:[0-9]]], $f[[F6]]
161 ; MIPS32R5-O32: lw $[[R13:[0-9]+]], %got($CPI{{[0-9]+}}_{{[0-9]+}})
162 ; MIPS32R5-O32: addiu $[[R14:[0-9]+]], $[[R13]], %lo($CPI{{[0-9]+}}_{{[0-9]+}})
164 ; MIPS64R5-N32: lw $[[R13:[0-9]+]], %got_page(.LCPI{{[0-9]+}}_{{[0-9]+}})
165 ; MIPS64R5-N32: addiu $[[R14:[0-9]+]], $[[R13]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
167 ; MIPS64R5-N64: ld $[[R13:[0-9]+]], %got_page(.LCPI{{[0-9]+}}_{{[0-9]+}})
168 ; MIPS64R5-N64: daddiu $[[R14:[0-9]+]], $[[R13]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
170 ; ALL: lui $[[R8:[0-9]+]], 32768
171 ; ALL: xor $[[R9:[0-9]+]], $[[R4]], $[[R8]]
173 ; MIPSR5: lh $[[R15:[0-9]+]], 0($[[R14]])
174 ; MIPSR5: fill.h $w[[W7:[0-9]+]], $[[R15]]
175 ; MIPSR5: fexupr.w $w[[W8:[0-9]+]], $w[[W7]]
176 ; MIPSR5: copy_s.w $[[R16:[0-9]+]], $w[[W8]][0]
177 ; MIPSR5: mtc1 $[[R16]], $f[[F7:[0-9]+]]
178 ; MIPSR5: c.olt.s $f[[F0]], $f[[F7]]
179 ; MIPSR5: movt $[[R9]], $[[R7]], $fcc0
181 ; MIPSR6: mfc1 $[[R10:[0-9]+]], $f[[F1]]
182 ; MIPSR6: seleqz $[[R11:[0-9]]], $[[R9]], $[[R10]]
183 ; MIPSR6: selnez $[[R12:[0-9]]], $[[R7]], $[[R10]]
184 ; MIPSR6: or $2, $[[R12]], $[[R11]]
189 define i32 @ffptosi() {
191 ; ALL-LABEL: ffptosi:
192 %0 = load half, half * @h, align 2
193 %1 = fptosi half %0 to i32
196 ; ALL: lh $[[R0:[0-9]+]]
197 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
198 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
199 ; ALL: fexupr.d $w[[W2:[0-9]+]], $w[[W1]]
201 ; MIPS32: copy_s.w $[[R2:[0-9]+]], $w[[W2]][0]
202 ; MIPS32: mtc1 $[[R2]], $f[[F0:[0-9]+]]
203 ; MIPS32: copy_s.w $[[R3:[0-9]+]], $w[[W2]][1]
204 ; MIPS32: mthc1 $[[R3]], $f[[F0]]
206 ; MIPS64: copy_s.d $[[R2:[0-9]+]], $w[[W2]][0]
207 ; MIPS64: dmtc1 $[[R2]], $f[[F0:[0-9]+]]
209 ; ALL: trunc.w.d $f[[F1:[0-9]+]], $f[[F0]]
210 ; ALL: mfc1 $2, $f[[F1]]
213 define void @uitofp(i32 %a) {
217 ; MIPS32-O32: ldc1 $f[[F0:[0-9]+]], %lo($CPI{{[0-9]+}}_{{[0-9]+}})
218 ; MIPS32-O32: ldc1 $f[[F1:[0-9]+]], 0($sp)
220 ; MIPS64-N32: ldc1 $f[[F0:[0-9]+]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
221 ; MIPS64-N32: ldc1 $f[[F1:[0-9]+]], 8($sp)
223 ; MIPS64-N64: ldc1 $f[[F0:[0-9]+]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
224 ; MIPS64-N64: ldc1 $f[[F1:[0-9]+]], 8($sp)
226 ; MIPSR5: sub.d $f[[F2:[0-9]+]], $f[[F1]], $f[[F0]]
227 ; MIPSR6-O32: sub.d $f[[F2:[0-9]+]], $f[[F0]], $f[[F1]]
228 ; MIPSR6-N32: sub.d $f[[F2:[0-9]+]], $f[[F1]], $f[[F0]]
229 ; MIPSR6-N64: sub.d $f[[F2:[0-9]+]], $f[[F1]], $f[[F0]]
231 ; MIPS32: mfc1 $[[R0:[0-9]+]], $f[[F2]]
232 ; MIPS32: fill.w $w[[W0:[0-9]+]], $[[R0]]
233 ; MIPS32: mfhc1 $[[R1:[0-9]+]], $f[[F2]]
234 ; MIPS32: insert.w $w[[W0]][1], $[[R1]]
235 ; MIPS32: insert.w $w[[W0]][3], $[[R1]]
237 ; MIPS64-N64: ld $[[R3:[0-9]+]], %got_disp(h)
238 ; MIPS64-N32: lw $[[R3:[0-9]+]], %got_disp(h)
239 ; MIPS64: dmfc1 $[[R1:[0-9]+]], $f[[F2]]
240 ; MIPS64: fill.d $w[[W0:[0-9]+]], $[[R1]]
242 ; ALL: fexdo.w $w[[W1:[0-9]+]], $w[[W0]], $w[[W0]]
243 ; ALL: fexdo.h $w[[W2:[0-9]+]], $w[[W1]], $w[[W1]]
245 ; MIPS32: lw $[[R3:[0-9]+]], %got(h)
247 ; ALL: copy_u.h $[[R2:[0-9]+]], $w[[W2]]
248 ; ALL: sh $[[R2]], 0($[[R3]])
249 %0 = uitofp i32 %a to half
250 store half %0, half * @h, align 2
255 ; Check that f16 is expanded to f32 and relevant transfer ops occur.
256 ; We don't check f16 -> f64 expansion occurs, as we expand f16 to f32.
258 define void @fadd() {
261 %0 = load i16, i16* @g, align 2
262 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
264 ; ALL: lh $[[R0:[0-9]+]]
265 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
266 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
267 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
268 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
270 %2 = load i16, i16* @g, align 2
271 %3 = call float @llvm.convert.from.fp16.f32(i16 %2)
272 %add = fadd float %1, %3
274 ; ALL: add.s $f[[F1:[0-9]+]], $f[[F0]], $f[[F0]]
276 %4 = call i16 @llvm.convert.to.fp16.f32(float %add)
278 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
279 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
280 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
281 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
283 store i16 %4, i16* @g, align 2
287 ; Function Attrs: nounwind readnone
288 declare float @llvm.convert.from.fp16.f32(i16)
290 ; Function Attrs: nounwind readnone
291 declare i16 @llvm.convert.to.fp16.f32(float)
293 ; Function Attrs: nounwind
294 define void @fsub() {
297 %0 = load i16, i16* @g, align 2
298 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
300 ; ALL: lh $[[R0:[0-9]+]]
301 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
302 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
303 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
304 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
306 %2 = load i16, i16* @g, align 2
307 %3 = call float @llvm.convert.from.fp16.f32(i16 %2)
308 %sub = fsub float %1, %3
310 ; ALL: sub.s $f[[F1:[0-9]+]], $f[[F0]], $f[[F0]]
312 %4 = call i16 @llvm.convert.to.fp16.f32(float %sub)
314 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
315 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
316 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
317 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
319 store i16 %4, i16* @g, align 2
324 define void @fmult() {
327 %0 = load i16, i16* @g, align 2
328 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
330 ; ALL: lh $[[R0:[0-9]+]]
331 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
332 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
333 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
334 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
336 %2 = load i16, i16* @g, align 2
337 %3 = call float @llvm.convert.from.fp16.f32(i16 %2)
338 %mul = fmul float %1, %3
340 ; ALL: mul.s $f[[F1:[0-9]+]], $f[[F0]], $f[[F0]]
342 %4 = call i16 @llvm.convert.to.fp16.f32(float %mul)
344 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
345 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
346 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
347 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
349 store i16 %4, i16* @g, align 2
355 define void @fdiv() {
359 %0 = load i16, i16* @g, align 2
360 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
362 ; ALL: lh $[[R0:[0-9]+]]
363 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
364 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
365 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
366 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
368 %2 = load i16, i16* @g, align 2
369 %3 = call float @llvm.convert.from.fp16.f32(i16 %2)
370 %div = fdiv float %1, %3
372 ; ALL: div.s $f[[F1:[0-9]+]], $f[[F0]], $f[[F0]]
374 %4 = call i16 @llvm.convert.to.fp16.f32(float %div)
376 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
377 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
378 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
379 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
380 store i16 %4, i16* @g, align 2
385 define void @frem() {
388 %0 = load i16, i16* @g, align 2
389 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
391 ; ALL: lh $[[R0:[0-9]+]]
392 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
393 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
394 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
395 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
397 %2 = load i16, i16* @g, align 2
398 %3 = call float @llvm.convert.from.fp16.f32(i16 %2)
399 %rem = frem float %1, %3
401 ; MIPS32: lw $25, %call16(fmodf)($gp)
402 ; MIPS64-N32: lw $25, %call16(fmodf)($gp)
403 ; MIPS64-N64: ld $25, %call16(fmodf)($gp)
406 %4 = call i16 @llvm.convert.to.fp16.f32(float %rem)
408 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
409 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
410 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
411 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
413 store i16 %4, i16* @g, align 2
419 @i1 = external global i16, align 1
421 define void @fcmp() {
424 %0 = load i16, i16* @g, align 2
425 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
426 ; ALL: lh $[[R0:[0-9]+]]
427 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
428 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
429 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
430 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
432 %2 = load i16, i16* @g, align 2
433 %3 = call float @llvm.convert.from.fp16.f32(i16 %2)
434 %fcmp = fcmp oeq float %1, %3
436 ; MIPSR5: addiu $[[R2:[0-9]+]], $zero, 1
437 ; MIPSR5: c.un.s $f[[F0]], $f[[F0]]
438 ; MIPSR5: movt $[[R2]], $zero, $fcc0
439 ; MIPSR6: cmp.un.s $f[[F1:[0-9]+]], $f[[F0]], $f[[F0]]
440 ; MIPSR6: mfc1 $[[R3:[0-9]]], $f[[F1]]
441 ; MIPSR6: not $[[R4:[0-9]+]], $[[R3]]
442 ; MIPSR6: andi $[[R2:[0-9]+]], $[[R4]], 1
444 %4 = zext i1 %fcmp to i16
445 store i16 %4, i16* @i1, align 2
451 declare float @llvm.powi.f32(float, i32)
453 define void @fpowi() {
456 %0 = load i16, i16* @g, align 2
457 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
459 ; ALL: lh $[[R0:[0-9]+]]
460 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
461 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
462 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
463 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
465 %powi = call float @llvm.powi.f32(float %1, i32 2)
467 ; ALL: mul.s $f[[F1:[0-9]+]], $f[[F0]], $f[[F0]]
469 %2 = call i16 @llvm.convert.to.fp16.f32(float %powi)
471 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
472 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
473 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
474 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
476 store i16 %2, i16* @g, align 2
481 define void @fpowi_var(i32 %var) {
483 ; ALL-LABEL: fpowi_var:
484 %0 = load i16, i16* @g, align 2
485 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
487 ; ALL: lh $[[R0:[0-9]+]]
488 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
489 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
490 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
492 %powi = call float @llvm.powi.f32(float %1, i32 %var)
494 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
495 ; MIPS32-DAG: lw $25, %call16(__powisf2)($gp)
496 ; MIPS64-N32-DAG: lw $25, %call16(__powisf2)($gp)
497 ; MIPS64-N64-DAG: ld $25, %call16(__powisf2)($gp)
500 %2 = call i16 @llvm.convert.to.fp16.f32(float %powi)
502 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
503 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
504 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
505 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
507 store i16 %2, i16* @g, align 2
512 declare float @llvm.pow.f32(float %Val, float %power)
514 define void @fpow(float %var) {
517 %0 = load i16, i16* @g, align 2
518 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
520 ; ALL: lh $[[R0:[0-9]+]]
521 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
522 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
523 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
525 %powi = call float @llvm.pow.f32(float %1, float %var)
527 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
528 ; MIPS32-DAG: lw $25, %call16(powf)($gp)
529 ; MIPS64-N32-DAG: lw $25, %call16(powf)($gp)
530 ; MIPS64-N64-DAG: ld $25, %call16(powf)($gp)
533 %2 = call i16 @llvm.convert.to.fp16.f32(float %powi)
535 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
536 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
537 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
538 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
540 store i16 %2, i16* @g, align 2
545 declare float @llvm.log2.f32(float %Val)
547 define void @flog2() {
550 %0 = load i16, i16* @g, align 2
551 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
553 ; ALL: lh $[[R0:[0-9]+]]
554 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
555 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
556 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
557 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
558 ; MIPS32-DAG: lw $25, %call16(log2f)($gp)
559 ; MIPS64-N32-DAG: lw $25, %call16(log2f)($gp)
560 ; MIPS64-N64-DAG: ld $25, %call16(log2f)($gp)
563 %log2 = call float @llvm.log2.f32(float %1)
564 %2 = call i16 @llvm.convert.to.fp16.f32(float %log2)
566 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
567 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
568 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
569 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
571 store i16 %2, i16* @g, align 2
577 declare float @llvm.log10.f32(float %Val)
579 define void @flog10() {
582 %0 = load i16, i16* @g, align 2
583 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
585 ; ALL: lh $[[R0:[0-9]+]]
586 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
587 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
588 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
589 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
590 ; MIPS32-DAG: lw $25, %call16(log10f)($gp)
591 ; MIPS64-N32-DAG: lw $25, %call16(log10f)($gp)
592 ; MIPS64-N64-DAG: ld $25, %call16(log10f)($gp)
595 %log10 = call float @llvm.log10.f32(float %1)
596 %2 = call i16 @llvm.convert.to.fp16.f32(float %log10)
598 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
599 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
600 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
601 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
603 store i16 %2, i16* @g, align 2
609 declare float @llvm.sqrt.f32(float %Val)
611 define void @fsqrt() {
614 %0 = load i16, i16* @g, align 2
615 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
617 ; ALL: lh $[[R0:[0-9]+]]
618 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
619 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
620 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
621 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
622 ; ALL: sqrt.s $f[[F1:[0-9]+]], $f[[F0]]
624 %sqrt = call float @llvm.sqrt.f32(float %1)
625 %2 = call i16 @llvm.convert.to.fp16.f32(float %sqrt)
627 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
628 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
629 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
630 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
632 store i16 %2, i16* @g, align 2
638 declare float @llvm.sin.f32(float %Val)
640 define void @fsin() {
643 %0 = load i16, i16* @g, align 2
644 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
646 ; ALL: lh $[[R0:[0-9]+]]
647 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
648 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
649 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
650 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
651 ; MIPS32-DAG: lw $25, %call16(sinf)($gp)
652 ; MIPS64-N32-DAG: lw $25, %call16(sinf)($gp)
653 ; MIPS64-N64-DAG: ld $25, %call16(sinf)($gp)
656 %sin = call float @llvm.sin.f32(float %1)
657 %2 = call i16 @llvm.convert.to.fp16.f32(float %sin)
659 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
660 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
661 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
662 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
664 store i16 %2, i16* @g, align 2
670 declare float @llvm.cos.f32(float %Val)
672 define void @fcos() {
675 %0 = load i16, i16* @g, align 2
676 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
678 ; ALL: lh $[[R0:[0-9]+]]
679 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
680 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
681 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
682 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
683 ; MIPS32-DAG: lw $25, %call16(cosf)($gp)
684 ; MIPS64-N32-DAG: lw $25, %call16(cosf)($gp)
685 ; MIPS64-N64-DAG: ld $25, %call16(cosf)($gp)
688 %cos = call float @llvm.cos.f32(float %1)
689 %2 = call i16 @llvm.convert.to.fp16.f32(float %cos)
691 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
692 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
693 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
694 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
696 store i16 %2, i16* @g, align 2
702 declare float @llvm.exp.f32(float %Val)
704 define void @fexp() {
707 %0 = load i16, i16* @g, align 2
708 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
709 ; ALL: lh $[[R0:[0-9]+]]
710 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
711 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
712 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
713 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
714 ; MIPS32-DAG: lw $25, %call16(expf)($gp)
715 ; MIPS64-N32-DAG: lw $25, %call16(expf)($gp)
716 ; MIPS64-N64-DAG: ld $25, %call16(expf)($gp)
719 %exp = call float @llvm.exp.f32(float %1)
720 %2 = call i16 @llvm.convert.to.fp16.f32(float %exp)
722 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
723 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
724 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
725 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
727 store i16 %2, i16* @g, align 2
733 declare float @llvm.exp2.f32(float %Val)
735 define void @fexp2() {
738 %0 = load i16, i16* @g, align 2
739 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
741 ; ALL: lh $[[R0:[0-9]+]]
742 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
743 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
744 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
745 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
746 ; MIPS32-DAG: lw $25, %call16(exp2f)($gp)
747 ; MIPS64-N32-DAG: lw $25, %call16(exp2f)($gp)
748 ; MIPS64-N64-DAG: ld $25, %call16(exp2f)($gp)
751 %exp2 = call float @llvm.exp2.f32(float %1)
752 %2 = call i16 @llvm.convert.to.fp16.f32(float %exp2)
754 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
755 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
756 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
757 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
759 store i16 %2, i16* @g, align 2
765 declare float @llvm.fma.f32(float, float, float)
767 define void @ffma(float %b, float %c) {
770 %0 = load i16, i16* @g, align 2
771 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
773 ; ALL: lh $[[R0:[0-9]+]]
774 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
775 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
776 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
777 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
778 ; MIPS32-DAG: lw $25, %call16(fmaf)($gp)
779 ; MIPS64-N32-DAG: lw $25, %call16(fmaf)($gp)
780 ; MIPS64-N64-DAG: ld $25, %call16(fmaf)($gp)
783 %fma = call float @llvm.fma.f32(float %1, float %b, float %c)
784 %2 = call i16 @llvm.convert.to.fp16.f32(float %fma)
786 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
787 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
788 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
789 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
791 store i16 %2, i16* @g, align 2
797 ; FIXME: For MIPSR6, this should produced the maddf.s instruction. MIPSR5 cannot
798 ; fuse the operation such that the intermediate result is not rounded.
800 declare float @llvm.fmuladd.f32(float, float, float)
802 define void @ffmuladd(float %b, float %c) {
804 ; ALL-LABEL: ffmuladd:
805 %0 = load i16, i16* @g, align 2
806 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
808 ; ALL: lh $[[R0:[0-9]+]]
809 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
810 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
811 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
812 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
813 ; MIPS32-O32: madd.s $f[[F1:[0-9]]], $f14, $f[[F0]], $f12
814 ; MIPS32-N32: madd.s $f[[F1:[0-9]]], $f13, $f[[F0]], $f12
815 ; MIPS32-N64: madd.s $f[[F1:[0-9]]], $f13, $f[[F0]], $f12
816 ; MIPSR6: mul.s $f[[F2:[0-9]+]], $f[[F0]], $f12
817 ; MIPSR6-O32: add.s $f[[F1:[0-9]+]], $f[[F2]], $f14
818 ; MIPSR6-N32: add.s $f[[F1:[0-9]+]], $f[[F2]], $f13
819 ; MIPSR6-N64: add.s $f[[F1:[0-9]+]], $f[[F2]], $f13
821 %fmuladd = call float @llvm.fmuladd.f32(float %1, float %b, float %c)
822 %2 = call i16 @llvm.convert.to.fp16.f32(float %fmuladd)
824 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
825 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
826 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
827 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
829 store i16 %2, i16* @g, align 2
835 declare float @llvm.fabs.f32(float %Val)
837 define void @ffabs() {
840 %0 = load i16, i16* @g, align 2
841 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
843 ; ALL: lh $[[R0:[0-9]+]]
844 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
845 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
846 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
847 ; ALL: mtc1 $[[R1]], $f[[F0:[0-9]+]]
848 ; ALL: abs.s $f[[F1:[0-9]+]], $f[[F0]]
850 %fabs = call float @llvm.fabs.f32(float %1)
851 %2 = call i16 @llvm.convert.to.fp16.f32(float %fabs)
853 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
854 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
855 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
856 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
858 store i16 %2, i16* @g, align 2
864 declare float @llvm.minnum.f32(float %Val, float %b)
866 define void @fminnum(float %b) {
868 ; ALL-LABEL: fminnum:
869 %0 = load i16, i16* @g, align 2
870 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
872 ; ALL: lh $[[R0:[0-9]+]]
873 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
874 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
875 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
876 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
877 ; MIPS32-DAG: lw $25, %call16(fminf)($gp)
878 ; MIPS64-N32-DAG: lw $25, %call16(fminf)($gp)
879 ; MIPS64-N64-DAG: ld $25, %call16(fminf)($gp)
882 %minnum = call float @llvm.minnum.f32(float %1, float %b)
883 %2 = call i16 @llvm.convert.to.fp16.f32(float %minnum)
885 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
886 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
887 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
888 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
890 store i16 %2, i16* @g, align 2
896 declare float @llvm.maxnum.f32(float %Val, float %b)
898 define void @fmaxnum(float %b) {
900 ; ALL-LABEL: fmaxnum:
901 %0 = load i16, i16* @g, align 2
902 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
904 ; ALL: lh $[[R0:[0-9]+]]
905 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
906 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
907 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
908 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
909 ; MIPS32-DAG: lw $25, %call16(fmaxf)($gp)
910 ; MIPS64-N32-DAG: lw $25, %call16(fmaxf)($gp)
911 ; MIPS64-N64-DAG: ld $25, %call16(fmaxf)($gp)
914 %maxnum = call float @llvm.maxnum.f32(float %1, float %b)
915 %2 = call i16 @llvm.convert.to.fp16.f32(float %maxnum)
917 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
918 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
919 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
920 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
922 store i16 %2, i16* @g, align 2
928 ; This expansion of fcopysign could be done without converting f16 to float.
930 declare float @llvm.copysign.f32(float %Val, float %b)
932 define void @fcopysign(float %b) {
934 ; ALL-LABEL: fcopysign:
935 %0 = load i16, i16* @g, align 2
936 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
938 ; ALL: lh $[[R0:[0-9]+]]
939 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
940 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
941 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
943 %copysign = call float @llvm.copysign.f32(float %1, float %b)
944 %2 = call i16 @llvm.convert.to.fp16.f32(float %copysign)
946 ; ALL: mfc1 $[[R2:[0-9]+]], $f12
947 ; ALL: ext $[[R3:[0-9]+]], $3, 31, 1
948 ; ALL: ins $[[R1]], $[[R3]], 31, 1
949 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R1]]
950 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
951 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
953 store i16 %2, i16* @g, align 2
959 declare float @llvm.floor.f32(float %Val)
961 define void @ffloor() {
964 %0 = load i16, i16* @g, align 2
965 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
967 ; ALL: lh $[[R0:[0-9]+]]
968 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
969 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
970 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
971 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
972 ; MIPS32-DAG: lw $25, %call16(floorf)($gp)
973 ; MIPS64-N32-DAG: lw $25, %call16(floorf)($gp)
974 ; MIPS64-N64-DAG: ld $25, %call16(floorf)($gp)
977 %floor = call float @llvm.floor.f32(float %1)
978 %2 = call i16 @llvm.convert.to.fp16.f32(float %floor)
980 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
981 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
982 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
983 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
985 store i16 %2, i16* @g, align 2
991 declare float @llvm.ceil.f32(float %Val)
993 define void @fceil() {
996 %0 = load i16, i16* @g, align 2
997 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
999 ; ALL: lh $[[R0:[0-9]+]]
1000 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
1001 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
1002 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
1003 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
1004 ; MIPS32-DAG: lw $25, %call16(ceilf)($gp)
1005 ; MIPS64-N32-DAG: lw $25, %call16(ceilf)($gp)
1006 ; MIPS64-N64-DAG: ld $25, %call16(ceilf)($gp)
1009 %ceil = call float @llvm.ceil.f32(float %1)
1010 %2 = call i16 @llvm.convert.to.fp16.f32(float %ceil)
1012 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
1013 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
1014 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
1015 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
1017 store i16 %2, i16* @g, align 2
1023 declare float @llvm.trunc.f32(float %Val)
1025 define void @ftrunc() {
1027 ; ALL-LABEL: ftrunc:
1028 %0 = load i16, i16* @g, align 2
1029 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
1031 ; ALL: lh $[[R0:[0-9]+]]
1032 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
1033 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
1034 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
1035 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
1036 ; MIPS32-DAG: lw $25, %call16(truncf)($gp)
1037 ; MIPS64-N32-DAG: lw $25, %call16(truncf)($gp)
1038 ; MIPS64-N64-DAG: ld $25, %call16(truncf)($gp)
1041 %trunc = call float @llvm.trunc.f32(float %1)
1042 %2 = call i16 @llvm.convert.to.fp16.f32(float %trunc)
1044 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
1045 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
1046 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
1047 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
1049 store i16 %2, i16* @g, align 2
1055 declare float @llvm.rint.f32(float %Val)
1057 define void @frint() {
1060 %0 = load i16, i16* @g, align 2
1061 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
1063 ; ALL: lh $[[R0:[0-9]+]]
1064 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
1065 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
1066 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
1067 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
1068 ; MIPS32-DAG: lw $25, %call16(rintf)($gp)
1069 ; MIPS64-N32-DAG: lw $25, %call16(rintf)($gp)
1070 ; MIPS64-N64-DAG: ld $25, %call16(rintf)($gp)
1072 %rint = call float @llvm.rint.f32(float %1)
1073 %2 = call i16 @llvm.convert.to.fp16.f32(float %rint)
1075 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
1076 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
1077 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
1078 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
1079 store i16 %2, i16* @g, align 2
1085 declare float @llvm.nearbyint.f32(float %Val)
1087 define void @fnearbyint() {
1089 ; ALL-LABEL: fnearbyint:
1090 %0 = load i16, i16* @g, align 2
1091 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
1093 ; ALL: lh $[[R0:[0-9]+]]
1094 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
1095 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
1096 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
1097 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
1098 ; MIPS32-DAG: lw $25, %call16(nearbyintf)($gp)
1099 ; MIPS64-N32-DAG: lw $25, %call16(nearbyintf)($gp)
1100 ; MIPS64-N64-DAG: ld $25, %call16(nearbyintf)($gp)
1103 %nearbyint = call float @llvm.nearbyint.f32(float %1)
1104 %2 = call i16 @llvm.convert.to.fp16.f32(float %nearbyint)
1106 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
1107 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
1108 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
1109 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
1111 store i16 %2, i16* @g, align 2
1117 declare float @llvm.round.f32(float %Val)
1119 define void @fround() {
1121 ; ALL-LABEL: fround:
1122 %0 = load i16, i16* @g, align 2
1123 %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
1125 ; ALL: lh $[[R0:[0-9]+]]
1126 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
1127 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
1128 ; ALL: copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
1129 ; ALL-DAG: mtc1 $[[R1]], $f[[F0:[0-9]+]]
1130 ; MIPS32-DAG: lw $25, %call16(roundf)($gp)
1131 ; MIPS64-N32-DAG: lw $25, %call16(roundf)($gp)
1132 ; MIPS64-N64-DAG: ld $25, %call16(roundf)($gp)
1135 %round = call float @llvm.round.f32(float %1)
1136 %2 = call i16 @llvm.convert.to.fp16.f32(float %round)
1138 ; ALL: mfc1 $[[R2:[0-9]+]], $f[[F1]]
1139 ; ALL: fill.w $w[[W2:[0-9]+]], $[[R2]]
1140 ; ALL: fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
1141 ; ALL: copy_u.h $[[R3:[0-9]+]], $w[[W3]][0]
1143 store i16 %2, i16* @g, align 2