1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8 @glob = common local_unnamed_addr global i8 0, align 1
10 define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
11 ; CHECK-LABEL: test_ineuc:
12 ; CHECK: # %bb.0: # %entry
13 ; CHECK-NEXT: xor r3, r3, r4
14 ; CHECK-NEXT: cntlzw r3, r3
15 ; CHECK-NEXT: srwi r3, r3, 5
16 ; CHECK-NEXT: xori r3, r3, 1
19 %cmp = icmp ne i8 %a, %b
20 %conv2 = zext i1 %cmp to i32
24 define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) {
25 ; CHECK-LABEL: test_ineuc_sext:
26 ; CHECK: # %bb.0: # %entry
27 ; CHECK-NEXT: xor r3, r3, r4
28 ; CHECK-NEXT: cntlzw r3, r3
29 ; CHECK-NEXT: srwi r3, r3, 5
30 ; CHECK-NEXT: xori r3, r3, 1
31 ; CHECK-NEXT: neg r3, r3
34 %cmp = icmp ne i8 %a, %b
35 %sub = sext i1 %cmp to i32
39 define signext i32 @test_ineuc_z(i8 zeroext %a) {
40 ; CHECK-LABEL: test_ineuc_z:
41 ; CHECK: # %bb.0: # %entry
42 ; CHECK-NEXT: cntlzw r3, r3
43 ; CHECK-NEXT: srwi r3, r3, 5
44 ; CHECK-NEXT: xori r3, r3, 1
47 %cmp = icmp ne i8 %a, 0
48 %conv1 = zext i1 %cmp to i32
52 define signext i32 @test_ineuc_sext_z(i8 zeroext %a) {
53 ; CHECK-LABEL: test_ineuc_sext_z:
54 ; CHECK: # %bb.0: # %entry
55 ; CHECK-NEXT: cntlzw r3, r3
56 ; CHECK-NEXT: srwi r3, r3, 5
57 ; CHECK-NEXT: xori r3, r3, 1
58 ; CHECK-NEXT: neg r3, r3
61 %cmp = icmp ne i8 %a, 0
62 %sub = sext i1 %cmp to i32
66 define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
67 ; CHECK-LABEL: test_ineuc_store:
68 ; CHECK: # %bb.0: # %entry
69 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
70 ; CHECK-NEXT: xor r3, r3, r4
71 ; CHECK-NEXT: cntlzw r3, r3
72 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
73 ; CHECK-NEXT: srwi r3, r3, 5
74 ; CHECK-NEXT: xori r3, r3, 1
75 ; CHECK-NEXT: stb r3, 0(r4)
78 %cmp = icmp ne i8 %a, %b
79 %conv3 = zext i1 %cmp to i8
80 store i8 %conv3, i8* @glob, align 1
84 define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
85 ; CHECK-LABEL: test_ineuc_sext_store:
86 ; CHECK: # %bb.0: # %entry
87 ; CHECK-NEXT: xor r3, r3, r4
88 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
89 ; CHECK-NEXT: cntlzw r3, r3
90 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
91 ; CHECK-NEXT: srwi r3, r3, 5
92 ; CHECK-NEXT: xori r3, r3, 1
93 ; CHECK-NEXT: neg r3, r3
94 ; CHECK-NEXT: stb r3, 0(r4)
97 %cmp = icmp ne i8 %a, %b
98 %conv3 = sext i1 %cmp to i8
99 store i8 %conv3, i8* @glob, align 1
103 define void @test_ineuc_z_store(i8 zeroext %a) {
104 ; CHECK-LABEL: test_ineuc_z_store:
105 ; CHECK: # %bb.0: # %entry
106 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
107 ; CHECK-NEXT: cntlzw r3, r3
108 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
109 ; CHECK-NEXT: srwi r3, r3, 5
110 ; CHECK-NEXT: xori r3, r3, 1
111 ; CHECK-NEXT: stb r3, 0(r4)
114 %cmp = icmp ne i8 %a, 0
115 %conv2 = zext i1 %cmp to i8
116 store i8 %conv2, i8* @glob, align 1
120 define void @test_ineuc_sext_z_store(i8 zeroext %a) {
121 ; CHECK-LABEL: test_ineuc_sext_z_store:
122 ; CHECK: # %bb.0: # %entry
123 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
124 ; CHECK-NEXT: cntlzw r3, r3
125 ; CHECK-NEXT: srwi r3, r3, 5
126 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
127 ; CHECK-NEXT: xori r3, r3, 1
128 ; CHECK-NEXT: neg r3, r3
129 ; CHECK-NEXT: stb r3, 0(r4)
132 %cmp = icmp ne i8 %a, 0
133 %conv2 = sext i1 %cmp to i8
134 store i8 %conv2, i8* @glob, align 1