1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
3 ;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 15
4 ;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 3
5 ;CHECK-DAG: image_sample {{v[0-9]+}}, 2
6 ;CHECK-DAG: image_sample {{v[0-9]+}}, 1
7 ;CHECK-DAG: image_sample {{v[0-9]+}}, 4
8 ;CHECK-DAG: image_sample {{v[0-9]+}}, 8
9 ;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 5
10 ;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 9
11 ;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 6
12 ;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 10
13 ;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 12
14 ;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 7
15 ;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 11
16 ;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 13
17 ;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 14
18 ;CHECK-DAG: image_sample {{v[0-9]+}}, 8
20 define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) #0 {
21 %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
22 %v2 = insertelement <4 x i32> undef, i32 %a1, i32 1
23 %v3 = insertelement <4 x i32> undef, i32 %a1, i32 2
24 %v4 = insertelement <4 x i32> undef, i32 %a1, i32 3
25 %v5 = insertelement <4 x i32> undef, i32 %a2, i32 0
26 %v6 = insertelement <4 x i32> undef, i32 %a2, i32 1
27 %v7 = insertelement <4 x i32> undef, i32 %a2, i32 2
28 %v8 = insertelement <4 x i32> undef, i32 %a2, i32 3
29 %v9 = insertelement <4 x i32> undef, i32 %a3, i32 0
30 %v10 = insertelement <4 x i32> undef, i32 %a3, i32 1
31 %v11 = insertelement <4 x i32> undef, i32 %a3, i32 2
32 %v12 = insertelement <4 x i32> undef, i32 %a3, i32 3
33 %v13 = insertelement <4 x i32> undef, i32 %a4, i32 0
34 %v14 = insertelement <4 x i32> undef, i32 %a4, i32 1
35 %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2
36 %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3
37 %res1 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v1,
38 <32 x i8> undef, <16 x i8> undef, i32 1)
39 %res2 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v2,
40 <32 x i8> undef, <16 x i8> undef, i32 2)
41 %res3 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v3,
42 <32 x i8> undef, <16 x i8> undef, i32 3)
43 %res4 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v4,
44 <32 x i8> undef, <16 x i8> undef, i32 4)
45 %res5 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v5,
46 <32 x i8> undef, <16 x i8> undef, i32 5)
47 %res6 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v6,
48 <32 x i8> undef, <16 x i8> undef, i32 6)
49 %res7 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v7,
50 <32 x i8> undef, <16 x i8> undef, i32 7)
51 %res8 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v8,
52 <32 x i8> undef, <16 x i8> undef, i32 8)
53 %res9 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v9,
54 <32 x i8> undef, <16 x i8> undef, i32 9)
55 %res10 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v10,
56 <32 x i8> undef, <16 x i8> undef, i32 10)
57 %res11 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v11,
58 <32 x i8> undef, <16 x i8> undef, i32 11)
59 %res12 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v12,
60 <32 x i8> undef, <16 x i8> undef, i32 12)
61 %res13 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v13,
62 <32 x i8> undef, <16 x i8> undef, i32 13)
63 %res14 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v14,
64 <32 x i8> undef, <16 x i8> undef, i32 14)
65 %res15 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v15,
66 <32 x i8> undef, <16 x i8> undef, i32 15)
67 %res16 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v16,
68 <32 x i8> undef, <16 x i8> undef, i32 16)
69 %e1 = extractelement <4 x float> %res1, i32 0
70 %e2 = extractelement <4 x float> %res2, i32 1
71 %e3 = extractelement <4 x float> %res3, i32 2
72 %e4 = extractelement <4 x float> %res4, i32 3
73 %t0 = extractelement <4 x float> %res5, i32 0
74 %t1 = extractelement <4 x float> %res5, i32 1
75 %e5 = fadd float %t0, %t1
76 %t2 = extractelement <4 x float> %res6, i32 0
77 %t3 = extractelement <4 x float> %res6, i32 2
78 %e6 = fadd float %t2, %t3
79 %t4 = extractelement <4 x float> %res7, i32 0
80 %t5 = extractelement <4 x float> %res7, i32 3
81 %e7 = fadd float %t4, %t5
82 %t6 = extractelement <4 x float> %res8, i32 1
83 %t7 = extractelement <4 x float> %res8, i32 2
84 %e8 = fadd float %t6, %t7
85 %t8 = extractelement <4 x float> %res9, i32 1
86 %t9 = extractelement <4 x float> %res9, i32 3
87 %e9 = fadd float %t8, %t9
88 %t10 = extractelement <4 x float> %res10, i32 2
89 %t11 = extractelement <4 x float> %res10, i32 3
90 %e10 = fadd float %t10, %t11
91 %t12 = extractelement <4 x float> %res11, i32 0
92 %t13 = extractelement <4 x float> %res11, i32 1
93 %t14 = extractelement <4 x float> %res11, i32 2
94 %t15 = fadd float %t12, %t13
95 %e11 = fadd float %t14, %t15
96 %t16 = extractelement <4 x float> %res12, i32 0
97 %t17 = extractelement <4 x float> %res12, i32 1
98 %t18 = extractelement <4 x float> %res12, i32 3
99 %t19 = fadd float %t16, %t17
100 %e12 = fadd float %t18, %t19
101 %t20 = extractelement <4 x float> %res13, i32 0
102 %t21 = extractelement <4 x float> %res13, i32 2
103 %t22 = extractelement <4 x float> %res13, i32 3
104 %t23 = fadd float %t20, %t21
105 %e13 = fadd float %t22, %t23
106 %t24 = extractelement <4 x float> %res14, i32 1
107 %t25 = extractelement <4 x float> %res14, i32 2
108 %t26 = extractelement <4 x float> %res14, i32 3
109 %t27 = fadd float %t24, %t25
110 %e14 = fadd float %t26, %t27
111 %t28 = extractelement <4 x float> %res15, i32 0
112 %t29 = extractelement <4 x float> %res15, i32 1
113 %t30 = extractelement <4 x float> %res15, i32 2
114 %t31 = extractelement <4 x float> %res15, i32 3
115 %t32 = fadd float %t28, %t29
116 %t33 = fadd float %t30, %t31
117 %e15 = fadd float %t32, %t33
118 %e16 = extractelement <4 x float> %res16, i32 3
119 %s1 = fadd float %e1, %e2
120 %s2 = fadd float %s1, %e3
121 %s3 = fadd float %s2, %e4
122 %s4 = fadd float %s3, %e5
123 %s5 = fadd float %s4, %e6
124 %s6 = fadd float %s5, %e7
125 %s7 = fadd float %s6, %e8
126 %s8 = fadd float %s7, %e9
127 %s9 = fadd float %s8, %e10
128 %s10 = fadd float %s9, %e11
129 %s11 = fadd float %s10, %e12
130 %s12 = fadd float %s11, %e13
131 %s13 = fadd float %s12, %e14
132 %s14 = fadd float %s13, %e15
133 %s15 = fadd float %s14, %e16
134 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s15, float %s15, float %s15, float %s15)
139 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 15
140 define void @v1(i32 %a1) #0 {
142 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
143 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
144 %2 = extractelement <4 x float> %1, i32 0
145 %3 = extractelement <4 x float> %1, i32 1
146 %4 = extractelement <4 x float> %1, i32 2
147 %5 = extractelement <4 x float> %1, i32 3
148 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %5)
153 declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone
155 declare <4 x float> @llvm.SI.sample.(<4 x i32>, <32 x i8>, <16 x i8>, i32) readnone
157 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
159 attributes #0 = { "ShaderType"="0" }