1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3 declare i32 @llvm.r600.read.tidig.x() #1
5 ; SI-LABEL: {{^}}v_cnd_nan_nosgpr:
6 ; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}}
8 ; All nan values are converted to 0xffffffff
10 define void @v_cnd_nan_nosgpr(float addrspace(1)* %out, i32 %c, float addrspace(1)* %fptr) #0 {
11 %idx = call i32 @llvm.r600.read.tidig.x() #1
12 %f.gep = getelementptr float addrspace(1)* %fptr, i32 %idx
13 %f = load float addrspace(1)* %fptr
14 %setcc = icmp ne i32 %c, 0
15 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
16 store float %select, float addrspace(1)* %out
21 ; This requires slightly trickier SGPR operand legalization since the
22 ; single constant bus SGPR usage is the last operand, and it should
25 ; SI-LABEL: {{^}}v_cnd_nan:
26 ; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}}
28 ; All nan values are converted to 0xffffffff
30 define void @v_cnd_nan(float addrspace(1)* %out, i32 %c, float %f) #0 {
31 %setcc = icmp ne i32 %c, 0
32 %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
33 store float %select, float addrspace(1)* %out
37 attributes #0 = { nounwind }
38 attributes #1 = { nounwind readnone }