1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512dq | FileCheck %s
4 declare <8 x i64> @llvm.x86.avx512.mask.cvtpd2qq.512(<8 x double>, <8 x i64>, i8, i32)
6 define <8 x i64>@test_int_x86_avx512_mask_cvt_pd2qq_512(<8 x double> %x0, <8 x i64> %x1, i8 %x2) {
7 ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2qq_512:
9 ; CHECK-NEXT: kmovb %edi, %k1
10 ; CHECK-NEXT: vcvtpd2qq {ru-sae}, %zmm0, %zmm1 {%k1}
11 ; CHECK-NEXT: vcvtpd2qq {rn-sae}, %zmm0, %zmm0
12 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
14 %res = call <8 x i64> @llvm.x86.avx512.mask.cvtpd2qq.512(<8 x double> %x0, <8 x i64> %x1, i8 %x2, i32 2)
15 %res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtpd2qq.512(<8 x double> %x0, <8 x i64> %x1, i8 -1, i32 0)
16 %res2 = add <8 x i64> %res, %res1
20 declare <8 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.512(<8 x double>, <8 x i64>, i8, i32)
22 define <8 x i64>@test_int_x86_avx512_mask_cvt_pd2uqq_512(<8 x double> %x0, <8 x i64> %x1, i8 %x2) {
23 ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2uqq_512:
25 ; CHECK-NEXT: kmovb %edi, %k1
26 ; CHECK-NEXT: vcvtpd2uqq {ru-sae}, %zmm0, %zmm1 {%k1}
27 ; CHECK-NEXT: vcvtpd2uqq {rn-sae}, %zmm0, %zmm0
28 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
30 %res = call <8 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.512(<8 x double> %x0, <8 x i64> %x1, i8 %x2, i32 2)
31 %res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.512(<8 x double> %x0, <8 x i64> %x1, i8 -1, i32 0)
32 %res2 = add <8 x i64> %res, %res1
36 declare <8 x i64> @llvm.x86.avx512.mask.cvtps2qq.512(<8 x float>, <8 x i64>, i8, i32)
38 define <8 x i64>@test_int_x86_avx512_mask_cvt_ps2qq_512(<8 x float> %x0, <8 x i64> %x1, i8 %x2) {
39 ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2qq_512:
41 ; CHECK-NEXT: kmovb %edi, %k1
42 ; CHECK-NEXT: vcvtps2qq {ru-sae}, %ymm0, %zmm1 {%k1}
43 ; CHECK-NEXT: vcvtps2qq {rn-sae}, %ymm0, %zmm0
44 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
46 %res = call <8 x i64> @llvm.x86.avx512.mask.cvtps2qq.512(<8 x float> %x0, <8 x i64> %x1, i8 %x2, i32 2)
47 %res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtps2qq.512(<8 x float> %x0, <8 x i64> %x1, i8 -1, i32 0)
48 %res2 = add <8 x i64> %res, %res1
52 declare <8 x i64> @llvm.x86.avx512.mask.cvtps2uqq.512(<8 x float>, <8 x i64>, i8, i32)
54 define <8 x i64>@test_int_x86_avx512_mask_cvt_ps2uqq_512(<8 x float> %x0, <8 x i64> %x1, i8 %x2) {
55 ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2uqq_512:
57 ; CHECK-NEXT: kmovb %edi, %k1
58 ; CHECK-NEXT: vcvtps2uqq {ru-sae}, %ymm0, %zmm1 {%k1}
59 ; CHECK-NEXT: vcvtps2uqq {rn-sae}, %ymm0, %zmm0
60 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
62 %res = call <8 x i64> @llvm.x86.avx512.mask.cvtps2uqq.512(<8 x float> %x0, <8 x i64> %x1, i8 %x2, i32 2)
63 %res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtps2uqq.512(<8 x float> %x0, <8 x i64> %x1, i8 -1, i32 0)
64 %res2 = add <8 x i64> %res, %res1
68 declare <8 x double> @llvm.x86.avx512.mask.cvtqq2pd.512(<8 x i64>, <8 x double>, i8, i32)
70 define <8 x double>@test_int_x86_avx512_mask_cvt_qq2pd_512(<8 x i64> %x0, <8 x double> %x1, i8 %x2) {
71 ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_qq2pd_512:
73 ; CHECK-NEXT: kmovb %edi, %k1
74 ; CHECK-NEXT: vcvtqq2pd %zmm0, %zmm1 {%k1}
75 ; CHECK-NEXT: vcvtqq2pd {rn-sae}, %zmm0, %zmm0
76 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
78 %res = call <8 x double> @llvm.x86.avx512.mask.cvtqq2pd.512(<8 x i64> %x0, <8 x double> %x1, i8 %x2, i32 4)
79 %res1 = call <8 x double> @llvm.x86.avx512.mask.cvtqq2pd.512(<8 x i64> %x0, <8 x double> %x1, i8 -1, i32 0)
80 %res2 = fadd <8 x double> %res, %res1
81 ret <8 x double> %res2
84 declare <8 x float> @llvm.x86.avx512.mask.cvtqq2ps.512(<8 x i64>, <8 x float>, i8, i32)
86 define <8 x float>@test_int_x86_avx512_mask_cvt_qq2ps_512(<8 x i64> %x0, <8 x float> %x1, i8 %x2) {
87 ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_qq2ps_512:
89 ; CHECK-NEXT: kmovb %edi, %k1
90 ; CHECK-NEXT: vcvtqq2ps %zmm0, %ymm1 {%k1}
91 ; CHECK-NEXT: vcvtqq2ps {rn-sae}, %zmm0, %ymm0
92 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
94 %res = call <8 x float> @llvm.x86.avx512.mask.cvtqq2ps.512(<8 x i64> %x0, <8 x float> %x1, i8 %x2, i32 4)
95 %res1 = call <8 x float> @llvm.x86.avx512.mask.cvtqq2ps.512(<8 x i64> %x0, <8 x float> %x1, i8 -1, i32 0)
96 %res2 = fadd <8 x float> %res, %res1
100 declare <8 x i64> @llvm.x86.avx512.mask.cvttpd2qq.512(<8 x double>, <8 x i64>, i8, i32)
102 define <8 x i64>@test_int_x86_avx512_mask_cvtt_pd2qq_512(<8 x double> %x0, <8 x i64> %x1, i8 %x2) {
103 ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2qq_512:
105 ; CHECK-NEXT: kmovb %edi, %k1
106 ; CHECK-NEXT: vcvttpd2qq %zmm0, %zmm1 {%k1}
107 ; CHECK-NEXT: vcvttpd2qq {sae}, %zmm0, %zmm0
108 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
110 %res = call <8 x i64> @llvm.x86.avx512.mask.cvttpd2qq.512(<8 x double> %x0, <8 x i64> %x1, i8 %x2, i32 4)
111 %res1 = call <8 x i64> @llvm.x86.avx512.mask.cvttpd2qq.512(<8 x double> %x0, <8 x i64> %x1, i8 -1, i32 8)
112 %res2 = add <8 x i64> %res, %res1
116 declare <8 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.512(<8 x double>, <8 x i64>, i8, i32)
118 define <8 x i64>@test_int_x86_avx512_mask_cvtt_pd2uqq_512(<8 x double> %x0, <8 x i64> %x1, i8 %x2) {
119 ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2uqq_512:
121 ; CHECK-NEXT: kmovb %edi, %k1
122 ; CHECK-NEXT: vcvttpd2uqq %zmm0, %zmm1 {%k1}
123 ; CHECK-NEXT: vcvttpd2uqq {sae}, %zmm0, %zmm0
124 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
126 %res = call <8 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.512(<8 x double> %x0, <8 x i64> %x1, i8 %x2, i32 4)
127 %res1 = call <8 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.512(<8 x double> %x0, <8 x i64> %x1, i8 -1, i32 8)
128 %res2 = add <8 x i64> %res, %res1
132 declare <8 x i64> @llvm.x86.avx512.mask.cvttps2qq.512(<8 x float>, <8 x i64>, i8, i32)
134 define <8 x i64>@test_int_x86_avx512_mask_cvtt_ps2qq_512(<8 x float> %x0, <8 x i64> %x1, i8 %x2) {
135 ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2qq_512:
137 ; CHECK-NEXT: kmovb %edi, %k1
138 ; CHECK-NEXT: vcvttps2qq %ymm0, %zmm1 {%k1}
139 ; CHECK-NEXT: vcvttps2qq {sae}, %ymm0, %zmm0
140 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
142 %res = call <8 x i64> @llvm.x86.avx512.mask.cvttps2qq.512(<8 x float> %x0, <8 x i64> %x1, i8 %x2, i32 4)
143 %res1 = call <8 x i64> @llvm.x86.avx512.mask.cvttps2qq.512(<8 x float> %x0, <8 x i64> %x1, i8 -1, i32 8)
144 %res2 = add <8 x i64> %res, %res1
148 declare <8 x i64> @llvm.x86.avx512.mask.cvttps2uqq.512(<8 x float>, <8 x i64>, i8, i32)
150 define <8 x i64>@test_int_x86_avx512_mask_cvtt_ps2uqq_512(<8 x float> %x0, <8 x i64> %x1, i8 %x2) {
151 ; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2uqq_512:
153 ; CHECK-NEXT: kmovb %edi, %k1
154 ; CHECK-NEXT: vcvttps2uqq %ymm0, %zmm1 {%k1}
155 ; CHECK-NEXT: vcvttps2uqq {sae}, %ymm0, %zmm0
156 ; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
158 %res = call <8 x i64> @llvm.x86.avx512.mask.cvttps2uqq.512(<8 x float> %x0, <8 x i64> %x1, i8 %x2, i32 4)
159 %res1 = call <8 x i64> @llvm.x86.avx512.mask.cvttps2uqq.512(<8 x float> %x0, <8 x i64> %x1, i8 -1, i32 8)
160 %res2 = add <8 x i64> %res, %res1
164 declare <8 x double> @llvm.x86.avx512.mask.cvtuqq2pd.512(<8 x i64>, <8 x double>, i8, i32)
166 define <8 x double>@test_int_x86_avx512_mask_cvt_uqq2pd_512(<8 x i64> %x0, <8 x double> %x1, i8 %x2) {
167 ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_uqq2pd_512:
169 ; CHECK-NEXT: kmovb %edi, %k1
170 ; CHECK-NEXT: vcvtuqq2pd %zmm0, %zmm1 {%k1}
171 ; CHECK-NEXT: vcvtuqq2pd {rn-sae}, %zmm0, %zmm0
172 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
174 %res = call <8 x double> @llvm.x86.avx512.mask.cvtuqq2pd.512(<8 x i64> %x0, <8 x double> %x1, i8 %x2, i32 4)
175 %res1 = call <8 x double> @llvm.x86.avx512.mask.cvtuqq2pd.512(<8 x i64> %x0, <8 x double> %x1, i8 -1, i32 0)
176 %res2 = fadd <8 x double> %res, %res1
177 ret <8 x double> %res2
180 declare <8 x float> @llvm.x86.avx512.mask.cvtuqq2ps.512(<8 x i64>, <8 x float>, i8, i32)
182 define <8 x float>@test_int_x86_avx512_mask_cvt_uqq2ps_512(<8 x i64> %x0, <8 x float> %x1, i8 %x2) {
183 ; CHECK-LABEL: test_int_x86_avx512_mask_cvt_uqq2ps_512:
185 ; CHECK-NEXT: kmovb %edi, %k1
186 ; CHECK-NEXT: vcvtuqq2ps %zmm0, %ymm1 {%k1}
187 ; CHECK-NEXT: vcvtuqq2ps {rn-sae}, %zmm0, %ymm0
188 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
190 %res = call <8 x float> @llvm.x86.avx512.mask.cvtuqq2ps.512(<8 x i64> %x0, <8 x float> %x1, i8 %x2, i32 4)
191 %res1 = call <8 x float> @llvm.x86.avx512.mask.cvtuqq2ps.512(<8 x i64> %x0, <8 x float> %x1, i8 -1, i32 0)
192 %res2 = fadd <8 x float> %res, %res1
193 ret <8 x float> %res2
196 declare <8 x double> @llvm.x86.avx512.mask.reduce.pd.512(<8 x double>, i32, <8 x double>, i8, i32)
198 define <8 x double>@test_int_x86_avx512_mask_reduce_pd_512(<8 x double> %x0, <8 x double> %x2, i8 %x3) {
199 ; CHECK-LABEL: test_int_x86_avx512_mask_reduce_pd_512:
201 ; CHECK-NEXT: kmovb %edi, %k1
202 ; CHECK-NEXT: vreducepd $8, %zmm0, %zmm1 {%k1}
203 ; CHECK-NEXT: vreducepd $4, {sae}, %zmm0, %zmm0
204 ; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
206 %res = call <8 x double> @llvm.x86.avx512.mask.reduce.pd.512(<8 x double> %x0, i32 8, <8 x double> %x2, i8 %x3, i32 4)
207 %res1 = call <8 x double> @llvm.x86.avx512.mask.reduce.pd.512(<8 x double> %x0, i32 4, <8 x double> %x2, i8 -1, i32 8)
208 %res2 = fadd <8 x double> %res, %res1
209 ret <8 x double> %res2
212 declare <16 x float> @llvm.x86.avx512.mask.reduce.ps.512(<16 x float>, i32, <16 x float>, i16, i32)
214 define <16 x float>@test_int_x86_avx512_mask_reduce_ps_512(<16 x float> %x0, <16 x float> %x2, i16 %x3) {
215 ; CHECK-LABEL: test_int_x86_avx512_mask_reduce_ps_512:
217 ; CHECK-NEXT: kmovw %edi, %k1
218 ; CHECK-NEXT: vreduceps $44, {sae}, %zmm0, %zmm1 {%k1}
219 ; CHECK-NEXT: vreduceps $11, %zmm0, %zmm0
220 ; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm0
222 %res = call <16 x float> @llvm.x86.avx512.mask.reduce.ps.512(<16 x float> %x0, i32 44, <16 x float> %x2, i16 %x3, i32 8)
223 %res1 = call <16 x float> @llvm.x86.avx512.mask.reduce.ps.512(<16 x float> %x0, i32 11, <16 x float> %x2, i16 -1, i32 4)
224 %res2 = fadd <16 x float> %res, %res1
225 ret <16 x float> %res2
228 declare <8 x double> @llvm.x86.avx512.mask.range.pd.512(<8 x double>, <8 x double>, i32, <8 x double>, i8, i32)
230 define <8 x double>@test_int_x86_avx512_mask_range_pd_512(<8 x double> %x0, <8 x double> %x1, <8 x double> %x3, i8 %x4) {
231 ; CHECK-LABEL: test_int_x86_avx512_mask_range_pd_512:
233 ; CHECK-NEXT: kmovb %edi, %k1
234 ; CHECK-NEXT: vrangepd $8, %zmm1, %zmm0, %zmm2 {%k1}
235 ; CHECK-NEXT: vrangepd $4, {sae}, %zmm1, %zmm0, %zmm0
236 ; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0
238 %res = call <8 x double> @llvm.x86.avx512.mask.range.pd.512(<8 x double> %x0, <8 x double> %x1, i32 8, <8 x double> %x3, i8 %x4, i32 4)
239 %res1 = call <8 x double> @llvm.x86.avx512.mask.range.pd.512(<8 x double> %x0, <8 x double> %x1, i32 4, <8 x double> %x3, i8 -1, i32 8)
240 %res2 = fadd <8 x double> %res, %res1
241 ret <8 x double> %res2
244 declare <16 x float> @llvm.x86.avx512.mask.range.ps.512(<16 x float>, <16 x float>, i32, <16 x float>, i16, i32)
246 define <16 x float>@test_int_x86_avx512_mask_range_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x float> %x3, i16 %x4) {
247 ; CHECK-LABEL: test_int_x86_avx512_mask_range_ps_512:
249 ; CHECK-NEXT: kmovw %edi, %k1
250 ; CHECK-NEXT: vrangeps $88, %zmm1, %zmm0, %zmm2 {%k1}
251 ; CHECK-NEXT: vrangeps $4, {sae}, %zmm1, %zmm0, %zmm0
252 ; CHECK-NEXT: vaddps %zmm0, %zmm2, %zmm0
254 %res = call <16 x float> @llvm.x86.avx512.mask.range.ps.512(<16 x float> %x0, <16 x float> %x1, i32 88, <16 x float> %x3, i16 %x4, i32 4)
255 %res1 = call <16 x float> @llvm.x86.avx512.mask.range.ps.512(<16 x float> %x0, <16 x float> %x1, i32 4, <16 x float> %x3, i16 -1, i32 8)
256 %res2 = fadd <16 x float> %res, %res1
257 ret <16 x float> %res2
260 declare <4 x float> @llvm.x86.avx512.mask.reduce.ss(<4 x float>, <4 x float>,<4 x float>, i8, i32, i32)
262 define <4 x float>@test_int_x86_avx512_mask_reduce_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4) {
263 ; CHECK-LABEL: test_int_x86_avx512_mask_reduce_ss:
265 ; CHECK-NEXT: andl $1, %edi
266 ; CHECK-NEXT: kmovw %edi, %k1
267 ; CHECK-NEXT: vreducess $4, %xmm1, %xmm0, %xmm2 {%k1}
268 ; CHECK-NEXT: vreducess $4, {sae}, %xmm1, %xmm0, %xmm0
269 ; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0
271 %res = call <4 x float> @llvm.x86.avx512.mask.reduce.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4, i32 4, i32 4)
272 %res1 = call <4 x float> @llvm.x86.avx512.mask.reduce.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 -1, i32 4, i32 8)
273 %res2 = fadd <4 x float> %res, %res1
274 ret <4 x float> %res2
277 declare <4 x float> @llvm.x86.avx512.mask.range.ss(<4 x float>, <4 x float>,<4 x float>, i8, i32, i32)
279 define <4 x float>@test_int_x86_avx512_mask_range_ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4) {
280 ; CHECK-LABEL: test_int_x86_avx512_mask_range_ss:
282 ; CHECK-NEXT: andl $1, %edi
283 ; CHECK-NEXT: kmovw %edi, %k1
284 ; CHECK-NEXT: vrangess $4, {sae}, %xmm1, %xmm0, %xmm2 {%k1}
285 ; CHECK-NEXT: vrangess $4, {sae}, %xmm1, %xmm0, %xmm0
286 ; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0
288 %res = call <4 x float> @llvm.x86.avx512.mask.range.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 %x4, i32 4, i32 8)
289 %res1 = call <4 x float> @llvm.x86.avx512.mask.range.ss(<4 x float> %x0, <4 x float> %x1, <4 x float> %x3, i8 -1, i32 4, i32 8)
290 %res2 = fadd <4 x float> %res, %res1
291 ret <4 x float> %res2
294 declare <2 x double> @llvm.x86.avx512.mask.reduce.sd(<2 x double>, <2 x double>,<2 x double>, i8, i32, i32)
296 define <2 x double>@test_int_x86_avx512_mask_reduce_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4) {
297 ; CHECK-LABEL: test_int_x86_avx512_mask_reduce_sd:
299 ; CHECK-NEXT: andl $1, %edi
300 ; CHECK-NEXT: kmovw %edi, %k1
301 ; CHECK-NEXT: vreducesd $4, %xmm1, %xmm0, %xmm2 {%k1}
302 ; CHECK-NEXT: vreducesd $4, {sae}, %xmm1, %xmm0, %xmm0
303 ; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0
305 %res = call <2 x double> @llvm.x86.avx512.mask.reduce.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4, i32 4, i32 4)
306 %res1 = call <2 x double> @llvm.x86.avx512.mask.reduce.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 -1, i32 4, i32 8)
307 %res2 = fadd <2 x double> %res, %res1
308 ret <2 x double> %res2
311 declare <2 x double> @llvm.x86.avx512.mask.range.sd(<2 x double>, <2 x double>,<2 x double>, i8, i32, i32)
313 define <2 x double>@test_int_x86_avx512_mask_range_sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4) {
314 ; CHECK-LABEL: test_int_x86_avx512_mask_range_sd:
316 ; CHECK-NEXT: andl $1, %edi
317 ; CHECK-NEXT: kmovw %edi, %k1
318 ; CHECK-NEXT: vrangesd $4, %xmm1, %xmm0, %xmm2 {%k1}
319 ; CHECK-NEXT: vrangesd $4, {sae}, %xmm1, %xmm0, %xmm0
320 ; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0
322 %res = call <2 x double> @llvm.x86.avx512.mask.range.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 %x4, i32 4, i32 4)
323 %res1 = call <2 x double> @llvm.x86.avx512.mask.range.sd(<2 x double> %x0, <2 x double> %x1, <2 x double> %x3, i8 -1, i32 4, i32 8)
324 %res2 = fadd <2 x double> %res, %res1
325 ret <2 x double> %res2
328 declare i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double>, i32, i8)
330 define i8 @test_int_x86_avx512_mask_fpclass_pd_512(<8 x double> %x0, i8 %x1) {
331 ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_512:
333 ; CHECK-NEXT: kmovb %edi, %k1
334 ; CHECK-NEXT: vfpclasspd $2, %zmm0, %k0 {%k1}
335 ; CHECK-NEXT: kmovb %k0, %ecx
336 ; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0
337 ; CHECK-NEXT: kmovb %k0, %eax
338 ; CHECK-NEXT: addb %cl, %al
340 %res = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 2, i8 %x1)
341 %res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 4, i8 -1)
342 %res2 = add i8 %res, %res1
345 declare i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float>, i32, i16)
347 define i16@test_int_x86_avx512_mask_fpclass_ps_512(<16 x float> %x0, i16 %x1) {
348 ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_512:
350 ; CHECK-NEXT: kmovw %edi, %k1
351 ; CHECK-NEXT: vfpclassps $4, %zmm0, %k0
352 ; CHECK-NEXT: kmovw %k0, %ecx
353 ; CHECK-NEXT: vfpclassps $4, %zmm0, %k0 {%k1}
354 ; CHECK-NEXT: kmovw %k0, %eax
355 ; CHECK-NEXT: addl %ecx, %eax
356 ; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
358 %res = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4, i16 %x1)
359 %res1 = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4, i16 -1)
360 %res2 = add i16 %res, %res1
364 declare i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double>, i32, i8)
366 define i8 @test_int_x86_avx512_mask_fpclass_sd(<2 x double> %x0, i8 %x1) {
367 ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_sd:
369 ; CHECK-NEXT: andl $1, %edi
370 ; CHECK-NEXT: kmovw %edi, %k1
371 ; CHECK-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1}
372 ; CHECK-NEXT: kmovw %k0, %ecx
373 ; CHECK-NEXT: andl $1, %ecx
374 ; CHECK-NEXT: vfpclasssd $4, %xmm0, %k0
375 ; CHECK-NEXT: kmovw %k0, %eax
376 ; CHECK-NEXT: andl $1, %eax
377 ; CHECK-NEXT: addb %cl, %al
378 ; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
380 %res = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 2, i8 %x1)
381 %res1 = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 4, i8 -1)
382 %res2 = add i8 %res, %res1
386 declare i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float>, i32, i8)
388 define i8 @test_int_x86_avx512_mask_fpclass_ss(<4 x float> %x0, i8 %x1) {
389 ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ss:
391 ; CHECK-NEXT: andl $1, %edi
392 ; CHECK-NEXT: kmovw %edi, %k1
393 ; CHECK-NEXT: vfpclassss $4, %xmm0, %k0 {%k1}
394 ; CHECK-NEXT: kmovw %k0, %ecx
395 ; CHECK-NEXT: andl $1, %ecx
396 ; CHECK-NEXT: vfpclassss $4, %xmm0, %k0
397 ; CHECK-NEXT: kmovw %k0, %eax
398 ; CHECK-NEXT: andl $1, %eax
399 ; CHECK-NEXT: addb %cl, %al
400 ; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
402 %res = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 %x1)
403 %res1 = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 -1)
404 %res2 = add i8 %res, %res1
408 declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x2.512(<4 x float>, <16 x float>, i16)
410 define <16 x float>@test_int_x86_avx512_mask_broadcastf32x2_512(<4 x float> %x0, <16 x float> %x2, i16 %x3) {
411 ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x2_512:
413 ; CHECK-NEXT: kmovw %edi, %k1
414 ; CHECK-NEXT: vbroadcastf32x2 {{.*#+}} zmm1 {%k1} = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
415 ; CHECK-NEXT: vbroadcastf32x2 {{.*#+}} zmm2 {%k1} {z} = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
416 ; CHECK-NEXT: vbroadcastf32x2 {{.*#+}} zmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
417 ; CHECK-NEXT: vaddps %zmm2, %zmm1, %zmm1
418 ; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm0
420 %res = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x2.512(<4 x float> %x0, <16 x float> %x2, i16 %x3)
421 %res1 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x2.512(<4 x float> %x0, <16 x float> zeroinitializer, i16 %x3)
422 %res2 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x2.512(<4 x float> %x0, <16 x float> %x2, i16 -1)
423 %res3 = fadd <16 x float> %res, %res1
424 %res4 = fadd <16 x float> %res3, %res2
425 ret <16 x float> %res4
428 declare <16 x i32> @llvm.x86.avx512.mask.broadcasti32x2.512(<4 x i32>, <16 x i32>, i16)
430 define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x2_512(<4 x i32> %x0, <16 x i32> %x2, i16 %x3) {
431 ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x2_512:
433 ; CHECK-NEXT: kmovw %edi, %k1
434 ; CHECK-NEXT: vbroadcasti32x2 {{.*#+}} zmm1 {%k1} = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
435 ; CHECK-NEXT: vbroadcasti32x2 {{.*#+}} zmm2 {%k1} {z} = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
436 ; CHECK-NEXT: vbroadcasti32x2 {{.*#+}} zmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
437 ; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1
438 ; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
440 %res = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x2.512(<4 x i32> %x0, <16 x i32> %x2, i16 %x3)
441 %res1 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x2.512(<4 x i32> %x0, <16 x i32> zeroinitializer, i16 %x3)
442 %res2 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x2.512(<4 x i32> %x0, <16 x i32> %x2, i16 -1)
443 %res3 = add <16 x i32> %res, %res1
444 %res4 = add <16 x i32> %res3, %res2
448 declare i16 @llvm.x86.avx512.cvtd2mask.512(<16 x i32>)
450 define i16@test_int_x86_avx512_cvtd2mask_512(<16 x i32> %x0) {
451 ; CHECK-LABEL: test_int_x86_avx512_cvtd2mask_512:
453 ; CHECK-NEXT: vpmovd2m %zmm0, %k0
454 ; CHECK-NEXT: kmovw %k0, %eax
456 %res = call i16 @llvm.x86.avx512.cvtd2mask.512(<16 x i32> %x0)
460 declare i8 @llvm.x86.avx512.cvtq2mask.512(<8 x i64>)
462 define i8@test_int_x86_avx512_cvtq2mask_512(<8 x i64> %x0) {
463 ; CHECK-LABEL: test_int_x86_avx512_cvtq2mask_512:
465 ; CHECK-NEXT: vpmovq2m %zmm0, %k0
466 ; CHECK-NEXT: kmovb %k0, %eax
468 %res = call i8 @llvm.x86.avx512.cvtq2mask.512(<8 x i64> %x0)
472 declare <16 x i32> @llvm.x86.avx512.cvtmask2d.512(i16)
474 define <16 x i32>@test_int_x86_avx512_cvtmask2d_512(i16 %x0) {
475 ; CHECK-LABEL: test_int_x86_avx512_cvtmask2d_512:
477 ; CHECK-NEXT: kmovw %edi, %k0
478 ; CHECK-NEXT: vpmovm2d %k0, %zmm0
480 %res = call <16 x i32> @llvm.x86.avx512.cvtmask2d.512(i16 %x0)
484 declare <8 x i64> @llvm.x86.avx512.cvtmask2q.512(i8)
486 define <8 x i64>@test_int_x86_avx512_cvtmask2q_512(i8 %x0) {
487 ; CHECK-LABEL: test_int_x86_avx512_cvtmask2q_512:
489 ; CHECK-NEXT: kmovb %edi, %k0
490 ; CHECK-NEXT: vpmovm2q %k0, %zmm0
492 %res = call <8 x i64> @llvm.x86.avx512.cvtmask2q.512(i8 %x0)
496 declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x8.512(<8 x float>, <16 x float>, i16)
498 define <16 x float>@test_int_x86_avx512_mask_broadcastf32x8_512(<8 x float> %x0, <16 x float> %x2, i16 %mask) {
499 ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x8_512:
501 ; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
502 ; CHECK-NEXT: kmovw %edi, %k1
503 ; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm2 {%k1} {z} = zmm0[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]
504 ; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm1 {%k1} = zmm0[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]
505 ; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 = zmm0[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]
506 ; CHECK-NEXT: vaddps %zmm1, %zmm0, %zmm0
507 ; CHECK-NEXT: vaddps %zmm0, %zmm2, %zmm0
510 %res1 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x8.512(<8 x float> %x0, <16 x float> %x2, i16 -1)
511 %res2 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x8.512(<8 x float> %x0, <16 x float> %x2, i16 %mask)
512 %res3 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x8.512(<8 x float> %x0, <16 x float> zeroinitializer, i16 %mask)
513 %res4 = fadd <16 x float> %res1, %res2
514 %res5 = fadd <16 x float> %res3, %res4
515 ret <16 x float> %res5
518 declare <8 x double> @llvm.x86.avx512.mask.broadcastf64x2.512(<2 x double>, <8 x double>, i8)
520 define <8 x double>@test_int_x86_avx512_mask_broadcastf64x2_512(<2 x double> %x0, <8 x double> %x2, i8 %mask) {
521 ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x2_512:
523 ; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
524 ; CHECK-NEXT: kmovb %edi, %k1
525 ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm2 {%k1} {z} = zmm0[0,1,0,1,0,1,0,1]
526 ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm1 {%k1} = zmm0[0,1,0,1,0,1,0,1]
527 ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,0,1,0,1,0,1]
528 ; CHECK-NEXT: vaddpd %zmm1, %zmm0, %zmm0
529 ; CHECK-NEXT: vaddpd %zmm0, %zmm2, %zmm0
532 %res1 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x2.512(<2 x double> %x0, <8 x double> %x2, i8 -1)
533 %res2 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x2.512(<2 x double> %x0, <8 x double> %x2, i8 %mask)
534 %res3 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x2.512(<2 x double> %x0, <8 x double> zeroinitializer, i8 %mask)
535 %res4 = fadd <8 x double> %res1, %res2
536 %res5 = fadd <8 x double> %res3, %res4
537 ret <8 x double> %res5
540 declare <16 x i32> @llvm.x86.avx512.mask.broadcasti32x8.512(<8 x i32>, <16 x i32>, i16)
542 define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x8_512(<8 x i32> %x0, <16 x i32> %x2, i16 %mask) {
543 ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x8_512:
545 ; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
546 ; CHECK-NEXT: kmovw %edi, %k1
547 ; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm2 {%k1} {z} = zmm0[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]
548 ; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm1 {%k1} = zmm0[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]
549 ; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 = zmm0[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]
550 ; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0
551 ; CHECK-NEXT: vpaddd %zmm0, %zmm2, %zmm0
554 %res1 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x8.512(<8 x i32> %x0, <16 x i32> %x2, i16 -1)
555 %res2 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x8.512(<8 x i32> %x0, <16 x i32> %x2, i16 %mask)
556 %res3 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x8.512(<8 x i32> %x0, <16 x i32> zeroinitializer, i16 %mask)
557 %res4 = add <16 x i32> %res1, %res2
558 %res5 = add <16 x i32> %res3, %res4
562 declare <8 x i64> @llvm.x86.avx512.mask.broadcasti64x2.512(<2 x i64>, <8 x i64>, i8)
564 define <8 x i64>@test_int_x86_avx512_mask_broadcasti64x2_512(<2 x i64> %x0, <8 x i64> %x2, i8 %mask) {
565 ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x2_512:
567 ; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def>
568 ; CHECK-NEXT: kmovb %edi, %k1
569 ; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm2 {%k1} {z} = zmm0[0,1,0,1,0,1,0,1]
570 ; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm1 {%k1} = zmm0[0,1,0,1,0,1,0,1]
571 ; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,0,1,0,1,0,1]
572 ; CHECK-NEXT: vpaddq %zmm1, %zmm0, %zmm0
573 ; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
576 %res1 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x2.512(<2 x i64> %x0, <8 x i64> %x2, i8 -1)
577 %res2 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x2.512(<2 x i64> %x0, <8 x i64> %x2, i8 %mask)
578 %res3 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x2.512(<2 x i64> %x0, <8 x i64> zeroinitializer, i8 %mask)
579 %res4 = add <8 x i64> %res1, %res2
580 %res5 = add <8 x i64> %res3, %res4