1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; NOTE: Assertions have been autogenerated by update_llc_test_checks.py
3 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512vl -mattr=+avx512ifma | FileCheck %s
5 declare <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
7 define <2 x i64>@test_int_x86_avx512_mask_vpmadd52h_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
8 ; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52h_uq_128:
10 ; CHECK-NEXT: kmovw %edi, %k1
11 ; CHECK-NEXT: vmovdqa %xmm0, %xmm3
12 ; CHECK-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm3
13 ; CHECK-NEXT: vmovdqa %xmm0, %xmm4
14 ; CHECK-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm4 {%k1}
15 ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2
16 ; CHECK-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm0 {%k1}
17 ; CHECK-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm2 {%k1} {z}
18 ; CHECK-NEXT: vpaddq %xmm0, %xmm4, %xmm0
19 ; CHECK-NEXT: vpaddq %xmm2, %xmm3, %xmm1
20 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
23 %res = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
24 %res1 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
25 %res2 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
26 %res3 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
27 %res4 = add <2 x i64> %res, %res1
28 %res5 = add <2 x i64> %res3, %res2
29 %res6 = add <2 x i64> %res5, %res4
33 declare <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
35 define <4 x i64>@test_int_x86_avx512_mask_vpmadd52h_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
36 ; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52h_uq_256:
38 ; CHECK-NEXT: kmovw %edi, %k1
39 ; CHECK-NEXT: vmovdqa %ymm0, %ymm3
40 ; CHECK-NEXT: vpmadd52huq %ymm2, %ymm1, %ymm3
41 ; CHECK-NEXT: vmovdqa %ymm0, %ymm4
42 ; CHECK-NEXT: vpmadd52huq %ymm2, %ymm1, %ymm4 {%k1}
43 ; CHECK-NEXT: vpxor %ymm2, %ymm2, %ymm2
44 ; CHECK-NEXT: vpmadd52huq %ymm2, %ymm1, %ymm0 {%k1}
45 ; CHECK-NEXT: vpmadd52huq %ymm2, %ymm1, %ymm2 {%k1} {z}
46 ; CHECK-NEXT: vpaddq %ymm0, %ymm4, %ymm0
47 ; CHECK-NEXT: vpaddq %ymm2, %ymm3, %ymm1
48 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
51 %res = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
52 %res1 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
53 %res2 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
54 %res3 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
55 %res4 = add <4 x i64> %res, %res1
56 %res5 = add <4 x i64> %res3, %res2
57 %res6 = add <4 x i64> %res5, %res4
61 declare <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
63 define <2 x i64>@test_int_x86_avx512_maskz_vpmadd52h_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
64 ; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52h_uq_128:
66 ; CHECK-NEXT: kmovw %edi, %k1
67 ; CHECK-NEXT: vmovdqa %xmm0, %xmm3
68 ; CHECK-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm3
69 ; CHECK-NEXT: vmovdqa %xmm0, %xmm4
70 ; CHECK-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm4 {%k1} {z}
71 ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2
72 ; CHECK-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm0 {%k1} {z}
73 ; CHECK-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm2 {%k1} {z}
74 ; CHECK-NEXT: vpaddq %xmm0, %xmm4, %xmm0
75 ; CHECK-NEXT: vpaddq %xmm2, %xmm3, %xmm1
76 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
79 %res = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
80 %res1 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
81 %res2 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
82 %res3 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
83 %res4 = add <2 x i64> %res, %res1
84 %res5 = add <2 x i64> %res3, %res2
85 %res6 = add <2 x i64> %res5, %res4
89 declare <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
91 define <4 x i64>@test_int_x86_avx512_maskz_vpmadd52h_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
92 ; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52h_uq_256:
94 ; CHECK-NEXT: kmovw %edi, %k1
95 ; CHECK-NEXT: vmovdqa %ymm0, %ymm3
96 ; CHECK-NEXT: vpmadd52huq %ymm2, %ymm1, %ymm3
97 ; CHECK-NEXT: vmovdqa %ymm0, %ymm4
98 ; CHECK-NEXT: vpmadd52huq %ymm2, %ymm1, %ymm4 {%k1} {z}
99 ; CHECK-NEXT: vpxor %ymm2, %ymm2, %ymm2
100 ; CHECK-NEXT: vpmadd52huq %ymm2, %ymm1, %ymm0 {%k1} {z}
101 ; CHECK-NEXT: vpmadd52huq %ymm2, %ymm1, %ymm2 {%k1} {z}
102 ; CHECK-NEXT: vpaddq %ymm0, %ymm4, %ymm0
103 ; CHECK-NEXT: vpaddq %ymm2, %ymm3, %ymm1
104 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
107 %res = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
108 %res1 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
109 %res2 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
110 %res3 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52h.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
111 %res4 = add <4 x i64> %res, %res1
112 %res5 = add <4 x i64> %res3, %res2
113 %res6 = add <4 x i64> %res5, %res4
117 declare <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
119 define <2 x i64>@test_int_x86_avx512_mask_vpmadd52l_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
120 ; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52l_uq_128:
122 ; CHECK-NEXT: kmovw %edi, %k1
123 ; CHECK-NEXT: vmovdqa %xmm0, %xmm3
124 ; CHECK-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm3
125 ; CHECK-NEXT: vmovdqa %xmm0, %xmm4
126 ; CHECK-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm4 {%k1}
127 ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2
128 ; CHECK-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm0 {%k1}
129 ; CHECK-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm2 {%k1} {z}
130 ; CHECK-NEXT: vpaddq %xmm0, %xmm4, %xmm0
131 ; CHECK-NEXT: vpaddq %xmm2, %xmm3, %xmm1
132 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
135 %res = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
136 %res1 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
137 %res2 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
138 %res3 = call <2 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
139 %res4 = add <2 x i64> %res, %res1
140 %res5 = add <2 x i64> %res3, %res2
141 %res6 = add <2 x i64> %res5, %res4
145 declare <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
147 define <4 x i64>@test_int_x86_avx512_mask_vpmadd52l_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
148 ; CHECK-LABEL: test_int_x86_avx512_mask_vpmadd52l_uq_256:
150 ; CHECK-NEXT: kmovw %edi, %k1
151 ; CHECK-NEXT: vmovdqa %ymm0, %ymm3
152 ; CHECK-NEXT: vpmadd52luq %ymm2, %ymm1, %ymm3
153 ; CHECK-NEXT: vmovdqa %ymm0, %ymm4
154 ; CHECK-NEXT: vpmadd52luq %ymm2, %ymm1, %ymm4 {%k1}
155 ; CHECK-NEXT: vpxor %ymm2, %ymm2, %ymm2
156 ; CHECK-NEXT: vpmadd52luq %ymm2, %ymm1, %ymm0 {%k1}
157 ; CHECK-NEXT: vpmadd52luq %ymm2, %ymm1, %ymm2 {%k1} {z}
158 ; CHECK-NEXT: vpaddq %ymm0, %ymm4, %ymm0
159 ; CHECK-NEXT: vpaddq %ymm2, %ymm3, %ymm1
160 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
163 %res = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
164 %res1 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
165 %res2 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
166 %res3 = call <4 x i64> @llvm.x86.avx512.mask.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
167 %res4 = add <4 x i64> %res, %res1
168 %res5 = add <4 x i64> %res3, %res2
169 %res6 = add <4 x i64> %res5, %res4
173 declare <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
175 define <2 x i64>@test_int_x86_avx512_maskz_vpmadd52l_uq_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {
176 ; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52l_uq_128:
178 ; CHECK-NEXT: kmovw %edi, %k1
179 ; CHECK-NEXT: vmovdqa %xmm0, %xmm3
180 ; CHECK-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm3
181 ; CHECK-NEXT: vmovdqa %xmm0, %xmm4
182 ; CHECK-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm4 {%k1} {z}
183 ; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2
184 ; CHECK-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm0 {%k1} {z}
185 ; CHECK-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm2 {%k1} {z}
186 ; CHECK-NEXT: vpaddq %xmm0, %xmm4, %xmm0
187 ; CHECK-NEXT: vpaddq %xmm2, %xmm3, %xmm1
188 ; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
191 %res = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
192 %res1 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
193 %res2 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> zeroinitializer, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
194 %res3 = call <2 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)
195 %res4 = add <2 x i64> %res, %res1
196 %res5 = add <2 x i64> %res3, %res2
197 %res6 = add <2 x i64> %res5, %res4
201 declare <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
203 define <4 x i64>@test_int_x86_avx512_maskz_vpmadd52l_uq_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3) {
204 ; CHECK-LABEL: test_int_x86_avx512_maskz_vpmadd52l_uq_256:
206 ; CHECK-NEXT: kmovw %edi, %k1
207 ; CHECK-NEXT: vmovdqa %ymm0, %ymm3
208 ; CHECK-NEXT: vpmadd52luq %ymm2, %ymm1, %ymm3
209 ; CHECK-NEXT: vmovdqa %ymm0, %ymm4
210 ; CHECK-NEXT: vpmadd52luq %ymm2, %ymm1, %ymm4 {%k1} {z}
211 ; CHECK-NEXT: vpxor %ymm2, %ymm2, %ymm2
212 ; CHECK-NEXT: vpmadd52luq %ymm2, %ymm1, %ymm0 {%k1} {z}
213 ; CHECK-NEXT: vpmadd52luq %ymm2, %ymm1, %ymm2 {%k1} {z}
214 ; CHECK-NEXT: vpaddq %ymm0, %ymm4, %ymm0
215 ; CHECK-NEXT: vpaddq %ymm2, %ymm3, %ymm1
216 ; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
219 %res = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %x3)
220 %res1 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
221 %res2 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> zeroinitializer, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %x3)
222 %res3 = call <4 x i64> @llvm.x86.avx512.maskz.vpmadd52l.uq.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 -1)
223 %res4 = add <4 x i64> %res, %res1
224 %res5 = add <4 x i64> %res3, %res2
225 %res6 = add <4 x i64> %res5, %res4