1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
4 define i64 @test1(i32 %xx, i32 %test) nounwind {
7 ; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
8 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
9 ; CHECK-NEXT: andb $7, %cl
10 ; CHECK-NEXT: movl %edx, %eax
11 ; CHECK-NEXT: shll %cl, %eax
12 ; CHECK-NEXT: shrl %edx
13 ; CHECK-NEXT: xorb $31, %cl
14 ; CHECK-NEXT: shrl %cl, %edx
16 %conv = zext i32 %xx to i64
17 %and = and i32 %test, 7
18 %sh_prom = zext i32 %and to i64
19 %shl = shl i64 %conv, %sh_prom
23 define i64 @test2(i64 %xx, i32 %test) nounwind {
26 ; CHECK-NEXT: pushl %esi
27 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
28 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
29 ; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
30 ; CHECK-NEXT: andb $7, %cl
31 ; CHECK-NEXT: movl %esi, %eax
32 ; CHECK-NEXT: shll %cl, %eax
33 ; CHECK-NEXT: shldl %cl, %esi, %edx
34 ; CHECK-NEXT: popl %esi
36 %and = and i32 %test, 7
37 %sh_prom = zext i32 %and to i64
38 %shl = shl i64 %xx, %sh_prom
42 define i64 @test3(i64 %xx, i32 %test) nounwind {
45 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
46 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
47 ; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
48 ; CHECK-NEXT: andb $7, %cl
49 ; CHECK-NEXT: shrdl %cl, %edx, %eax
50 ; CHECK-NEXT: shrl %cl, %edx
52 %and = and i32 %test, 7
53 %sh_prom = zext i32 %and to i64
54 %shr = lshr i64 %xx, %sh_prom
58 define i64 @test4(i64 %xx, i32 %test) nounwind {
61 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
62 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
63 ; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
64 ; CHECK-NEXT: andb $7, %cl
65 ; CHECK-NEXT: shrdl %cl, %edx, %eax
66 ; CHECK-NEXT: sarl %cl, %edx
68 %and = and i32 %test, 7
69 %sh_prom = zext i32 %and to i64
70 %shr = ashr i64 %xx, %sh_prom
75 define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) {
78 ; CHECK-NEXT: pushl %ebp
80 ; CHECK-NEXT: .cfi_def_cfa_offset 8
81 ; CHECK-NEXT: pushl %ebx
83 ; CHECK-NEXT: .cfi_def_cfa_offset 12
84 ; CHECK-NEXT: pushl %edi
86 ; CHECK-NEXT: .cfi_def_cfa_offset 16
87 ; CHECK-NEXT: pushl %esi
89 ; CHECK-NEXT: .cfi_def_cfa_offset 20
91 ; CHECK-NEXT: .cfi_offset %esi, -20
93 ; CHECK-NEXT: .cfi_offset %edi, -16
95 ; CHECK-NEXT: .cfi_offset %ebx, -12
97 ; CHECK-NEXT: .cfi_offset %ebp, -8
98 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
99 ; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
100 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx
101 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
102 ; CHECK-NEXT: movl %ebx, %edi
103 ; CHECK-NEXT: shll %cl, %edi
104 ; CHECK-NEXT: shldl %cl, %ebx, %esi
105 ; CHECK-NEXT: testb $32, %cl
106 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebp
107 ; CHECK-NEXT: je .LBB4_2
108 ; CHECK-NEXT: # BB#1:
109 ; CHECK-NEXT: movl %edi, %esi
110 ; CHECK-NEXT: xorl %edi, %edi
111 ; CHECK-NEXT: .LBB4_2:
112 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
113 ; CHECK-NEXT: movl %edx, %ebx
114 ; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
115 ; CHECK-NEXT: shll %cl, %ebx
116 ; CHECK-NEXT: shldl %cl, %edx, %ebp
117 ; CHECK-NEXT: testb $32, %cl
118 ; CHECK-NEXT: je .LBB4_4
119 ; CHECK-NEXT: # BB#3:
120 ; CHECK-NEXT: movl %ebx, %ebp
121 ; CHECK-NEXT: xorl %ebx, %ebx
122 ; CHECK-NEXT: .LBB4_4:
123 ; CHECK-NEXT: movl %ebp, 12(%eax)
124 ; CHECK-NEXT: movl %ebx, 8(%eax)
125 ; CHECK-NEXT: movl %esi, 4(%eax)
126 ; CHECK-NEXT: movl %edi, (%eax)
127 ; CHECK-NEXT: popl %esi
128 ; CHECK-NEXT: popl %edi
129 ; CHECK-NEXT: popl %ebx
130 ; CHECK-NEXT: popl %ebp
131 ; CHECK-NEXT: retl $4
132 %shl = shl <2 x i64> %A, %B
137 define i32 @test6() {
138 ; CHECK-LABEL: test6:
140 ; CHECK-NEXT: pushl %ebp
141 ; CHECK-NEXT: .Lcfi8:
142 ; CHECK-NEXT: .cfi_def_cfa_offset 8
143 ; CHECK-NEXT: .Lcfi9:
144 ; CHECK-NEXT: .cfi_offset %ebp, -8
145 ; CHECK-NEXT: movl %esp, %ebp
146 ; CHECK-NEXT: .Lcfi10:
147 ; CHECK-NEXT: .cfi_def_cfa_register %ebp
148 ; CHECK-NEXT: andl $-8, %esp
149 ; CHECK-NEXT: subl $16, %esp
150 ; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp)
151 ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
152 ; CHECK-NEXT: movl $1, (%esp)
153 ; CHECK-NEXT: movl $1, %eax
154 ; CHECK-NEXT: xorl %ecx, %ecx
155 ; CHECK-NEXT: shldl $32, %eax, %ecx
156 ; CHECK-NEXT: movb $32, %dl
157 ; CHECK-NEXT: testb %dl, %dl
158 ; CHECK-NEXT: jne .LBB5_2
159 ; CHECK-NEXT: # BB#1:
160 ; CHECK-NEXT: movl %ecx, %eax
161 ; CHECK-NEXT: .LBB5_2:
162 ; CHECK-NEXT: sete %cl
163 ; CHECK-NEXT: movzbl %cl, %ecx
164 ; CHECK-NEXT: xorl $1, %eax
165 ; CHECK-NEXT: orl %ecx, %eax
166 ; CHECK-NEXT: je .LBB5_5
167 ; CHECK-NEXT: # BB#3: # %if.then
168 ; CHECK-NEXT: movl $1, %eax
169 ; CHECK-NEXT: jmp .LBB5_4
170 ; CHECK-NEXT: .LBB5_5: # %if.end
171 ; CHECK-NEXT: xorl %eax, %eax
172 ; CHECK-NEXT: .LBB5_4: # %if.then
173 ; CHECK-NEXT: movl %ebp, %esp
174 ; CHECK-NEXT: popl %ebp
176 %x = alloca i32, align 4
177 %t = alloca i64, align 8
178 store i32 1, i32* %x, align 4
179 store i64 1, i64* %t, align 8 ;; DEAD
180 %load = load i32, i32* %x, align 4
181 %shl = shl i32 %load, 8
182 %add = add i32 %shl, -224
183 %sh_prom = zext i32 %add to i64
184 %shl1 = shl i64 1, %sh_prom
185 %cmp = icmp ne i64 %shl1, 4294967296
186 br i1 %cmp, label %if.then, label %if.end
188 if.then: ; preds = %entry
191 if.end: ; preds = %entry