1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
5 ; Use sbb x, x to materialize carry bit in a GPR. The value is either
8 define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
11 ; CHECK-NEXT: xorl %eax, %eax
12 ; CHECK-NEXT: cmpl $26, %edi
13 ; CHECK-NEXT: seta %al
14 ; CHECK-NEXT: shll $5, %eax
17 %t0 = icmp ugt i16 %x, 26
18 %if = select i1 %t0, i16 32, i16 0
22 define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
25 ; CHECK-NEXT: cmpl $26, %edi
26 ; CHECK-NEXT: sbbl %eax, %eax
27 ; CHECK-NEXT: andl $32, %eax
30 %t0 = icmp ult i16 %x, 26
31 %if = select i1 %t0, i16 32, i16 0
35 define i64 @t3(i64 %x) nounwind readnone ssp {
38 ; CHECK-NEXT: cmpq $18, %rdi
39 ; CHECK-NEXT: sbbq %rax, %rax
40 ; CHECK-NEXT: andl $64, %eax
43 %t0 = icmp ult i64 %x, 18
44 %if = select i1 %t0, i64 64, i64 0
48 @v4 = common global i32 0, align 4
50 define i32 @t4(i32 %a) {
53 ; CHECK-NEXT: movq _v4@{{.*}}(%rip), %rax
54 ; CHECK-NEXT: cmpl $1, (%rax)
55 ; CHECK-NEXT: sbbl %eax, %eax
56 ; CHECK-NEXT: andl $32768, %eax ## imm = 0x8000
57 ; CHECK-NEXT: leal 65536(%rax,%rax), %eax
60 %t0 = load i32, i32* @v4, align 4
61 %not.tobool = icmp eq i32 %t0, 0
62 %conv.i = sext i1 %not.tobool to i16
63 %call.lobit = lshr i16 %conv.i, 15
64 %add.i.1 = add nuw nsw i16 %call.lobit, 1
65 %conv4.2 = zext i16 %add.i.1 to i32
66 %add = shl nuw nsw i32 %conv4.2, 16
70 define i8 @t5(i32 %a) #0 {
73 ; CHECK-NEXT: testl %edi, %edi
74 ; CHECK-NEXT: setns %al
77 %.lobit = lshr i32 %a, 31
78 %trunc = trunc i32 %.lobit to i8
79 %.not = xor i8 %trunc, 1
83 define zeroext i1 @t6(i32 %a) #0 {
86 ; CHECK-NEXT: testl %edi, %edi
87 ; CHECK-NEXT: setns %al
90 %.lobit = lshr i32 %a, 31
91 %trunc = trunc i32 %.lobit to i1
92 %.not = xor i1 %trunc, 1
96 attributes #0 = { "target-cpu"="skylake-avx512" }