1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X32 --check-prefix=X32-SSE
3 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX
7 define <2 x i64> @test_extrqi(<2 x i64> %x) nounwind uwtable ssp {
8 ; X32-LABEL: test_extrqi:
10 ; X32-NEXT: extrq $2, $3, %xmm0
13 ; X64-LABEL: test_extrqi:
15 ; X64-NEXT: extrq $2, $3, %xmm0
17 %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)
21 define <2 x i64> @test_extrqi_domain(<2 x i64> *%p) nounwind uwtable ssp {
22 ; X32-SSE-LABEL: test_extrqi_domain:
24 ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
25 ; X32-SSE-NEXT: movdqa (%eax), %xmm0
26 ; X32-SSE-NEXT: extrq $2, $3, %xmm0
29 ; X32-AVX-LABEL: test_extrqi_domain:
31 ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
32 ; X32-AVX-NEXT: vmovdqa (%eax), %xmm0
33 ; X32-AVX-NEXT: extrq $2, $3, %xmm0
36 ; X64-SSE-LABEL: test_extrqi_domain:
38 ; X64-SSE-NEXT: movdqa (%rdi), %xmm0
39 ; X64-SSE-NEXT: extrq $2, $3, %xmm0
42 ; X64-AVX-LABEL: test_extrqi_domain:
44 ; X64-AVX-NEXT: vmovdqa (%rdi), %xmm0
45 ; X64-AVX-NEXT: extrq $2, $3, %xmm0
47 %1 = load <2 x i64>, <2 x i64> *%p
48 %2 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %1, i8 3, i8 2)
52 declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
54 define <2 x i64> @test_extrq(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
55 ; X32-LABEL: test_extrq:
57 ; X32-NEXT: extrq %xmm1, %xmm0
60 ; X64-LABEL: test_extrq:
62 ; X64-NEXT: extrq %xmm1, %xmm0
64 %1 = bitcast <2 x i64> %y to <16 x i8>
65 %2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind
69 define <2 x i64> @test_extrq_domain(<2 x i64> *%p, <2 x i64> %y) nounwind uwtable ssp {
70 ; X32-SSE-LABEL: test_extrq_domain:
72 ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
73 ; X32-SSE-NEXT: movdqa (%eax), %xmm1
74 ; X32-SSE-NEXT: extrq %xmm0, %xmm1
75 ; X32-SSE-NEXT: movdqa %xmm1, %xmm0
78 ; X32-AVX-LABEL: test_extrq_domain:
80 ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
81 ; X32-AVX-NEXT: vmovdqa (%eax), %xmm1
82 ; X32-AVX-NEXT: extrq %xmm0, %xmm1
83 ; X32-AVX-NEXT: vmovdqa %xmm1, %xmm0
86 ; X64-SSE-LABEL: test_extrq_domain:
88 ; X64-SSE-NEXT: movdqa (%rdi), %xmm1
89 ; X64-SSE-NEXT: extrq %xmm0, %xmm1
90 ; X64-SSE-NEXT: movdqa %xmm1, %xmm0
93 ; X64-AVX-LABEL: test_extrq_domain:
95 ; X64-AVX-NEXT: vmovdqa (%rdi), %xmm1
96 ; X64-AVX-NEXT: extrq %xmm0, %xmm1
97 ; X64-AVX-NEXT: vmovdqa %xmm1, %xmm0
99 %1 = load <2 x i64>, <2 x i64> *%p
100 %2 = bitcast <2 x i64> %y to <16 x i8>
101 %3 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %1, <16 x i8> %2) nounwind
105 declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
107 define <2 x i64> @test_insertqi(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
108 ; X32-LABEL: test_insertqi:
110 ; X32-NEXT: insertq $6, $5, %xmm1, %xmm0
113 ; X64-LABEL: test_insertqi:
115 ; X64-NEXT: insertq $6, $5, %xmm1, %xmm0
117 %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)
121 define <2 x i64> @test_insertqi_domain(<2 x i64> *%p, <2 x i64> %y) nounwind uwtable ssp {
122 ; X32-SSE-LABEL: test_insertqi_domain:
124 ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
125 ; X32-SSE-NEXT: movdqa (%eax), %xmm1
126 ; X32-SSE-NEXT: insertq $6, $5, %xmm0, %xmm1
127 ; X32-SSE-NEXT: movdqa %xmm1, %xmm0
130 ; X32-AVX-LABEL: test_insertqi_domain:
132 ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
133 ; X32-AVX-NEXT: vmovdqa (%eax), %xmm1
134 ; X32-AVX-NEXT: insertq $6, $5, %xmm0, %xmm1
135 ; X32-AVX-NEXT: vmovdqa %xmm1, %xmm0
138 ; X64-SSE-LABEL: test_insertqi_domain:
140 ; X64-SSE-NEXT: movdqa (%rdi), %xmm1
141 ; X64-SSE-NEXT: insertq $6, $5, %xmm0, %xmm1
142 ; X64-SSE-NEXT: movdqa %xmm1, %xmm0
145 ; X64-AVX-LABEL: test_insertqi_domain:
147 ; X64-AVX-NEXT: vmovdqa (%rdi), %xmm1
148 ; X64-AVX-NEXT: insertq $6, $5, %xmm0, %xmm1
149 ; X64-AVX-NEXT: vmovdqa %xmm1, %xmm0
151 %1 = load <2 x i64>, <2 x i64> *%p
152 %2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %y, i8 5, i8 6)
156 declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
158 define <2 x i64> @test_insertq(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
159 ; X32-LABEL: test_insertq:
161 ; X32-NEXT: insertq %xmm1, %xmm0
164 ; X64-LABEL: test_insertq:
166 ; X64-NEXT: insertq %xmm1, %xmm0
168 %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
172 define <2 x i64> @test_insertq_domain(<2 x i64> *%p, <2 x i64> %y) nounwind uwtable ssp {
173 ; X32-SSE-LABEL: test_insertq_domain:
175 ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
176 ; X32-SSE-NEXT: movdqa (%eax), %xmm1
177 ; X32-SSE-NEXT: insertq %xmm0, %xmm1
178 ; X32-SSE-NEXT: movdqa %xmm1, %xmm0
181 ; X32-AVX-LABEL: test_insertq_domain:
183 ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
184 ; X32-AVX-NEXT: vmovdqa (%eax), %xmm1
185 ; X32-AVX-NEXT: insertq %xmm0, %xmm1
186 ; X32-AVX-NEXT: vmovdqa %xmm1, %xmm0
189 ; X64-SSE-LABEL: test_insertq_domain:
191 ; X64-SSE-NEXT: movdqa (%rdi), %xmm1
192 ; X64-SSE-NEXT: insertq %xmm0, %xmm1
193 ; X64-SSE-NEXT: movdqa %xmm1, %xmm0
196 ; X64-AVX-LABEL: test_insertq_domain:
198 ; X64-AVX-NEXT: vmovdqa (%rdi), %xmm1
199 ; X64-AVX-NEXT: insertq %xmm0, %xmm1
200 ; X64-AVX-NEXT: vmovdqa %xmm1, %xmm0
202 %1 = load <2 x i64>, <2 x i64> *%p
203 %2 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %1, <2 x i64> %y) nounwind
207 declare <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64>, <2 x i64>) nounwind