test/CodeGen/arm-atomics-m.c

   1 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=thumbv7m-none--eabi -target-cpu cortex-m3 | FileCheck %s
   2
   3 int i;
   4 long long l;
   5
   6 typedef enum memory_order {
   7   memory_order_relaxed, memory_order_consume, memory_order_acquire,
   8   memory_order_release, memory_order_acq_rel, memory_order_seq_cst
   9 } memory_order;
  10
  11 void test_presence(void)
  12 {
  13   // CHECK-LABEL: @test_presence
  14   // CHECK: atomicrmw add i32* {{.*}} seq_cst
  15   __atomic_fetch_add(&i, 1, memory_order_seq_cst);
  16   // CHECK: atomicrmw sub i32* {{.*}} seq_cst
  17   __atomic_fetch_sub(&i, 1, memory_order_seq_cst);
  18   // CHECK: load atomic i32, i32* {{.*}} seq_cst
  19   int r;
  20   __atomic_load(&i, &r, memory_order_seq_cst);
  21   // CHECK: store atomic i32 {{.*}} seq_cst
  22   r = 0;
  23   __atomic_store(&i, &r, memory_order_seq_cst);
  24
  25   // CHECK: __atomic_fetch_add_8
  26   __atomic_fetch_add(&l, 1, memory_order_seq_cst);
  27   // CHECK: __atomic_fetch_sub_8
  28   __atomic_fetch_sub(&l, 1, memory_order_seq_cst);
  29   // CHECK: __atomic_load_8
  30   long long rl;
  31   __atomic_load(&l, &rl, memory_order_seq_cst);
  32   // CHECK: __atomic_store_8
  33   rl = 0;
  34   __atomic_store(&l, &rl, memory_order_seq_cst);
  35 }