1 // Test target codegen - host bc file has to be created first.
2 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
7 // expected-no-diagnostics
11 // Check that the execution mode of all 2 target regions on the gpu is set to SPMD Mode.
12 // CHECK-DAG: {{@__omp_offloading_.+l26}}_exec_mode = weak constant i8 0
13 // CHECK-DAG: {{@__omp_offloading_.+l31}}_exec_mode = weak constant i8 0
21 #pragma omp target parallel if(target: 0)
26 #pragma omp target parallel map(tofrom: aa)
31 #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40)
44 a += ftemplate<int>(n);
49 // CHECK-NOT: define {{.*}}void {{@__omp_offloading_.+template.+l17}}
56 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l26}}(
57 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
58 // CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align
59 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
60 // CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
61 // CHECK: call void @__kmpc_spmd_kernel_init(i32 [[THREAD_LIMIT]],
62 // CHECK: br label {{%?}}[[EXEC:.+]]
65 // CHECK: {{call|invoke}} void [[OP1:@.+]](i32* null, i32* null, i16* [[AA]])
66 // CHECK: br label {{%?}}[[DONE:.+]]
69 // CHECK: call void @__kmpc_spmd_kernel_deinit()
70 // CHECK: br label {{%?}}[[EXIT:.+]]
76 // CHECK: define internal void [[OP1]](i32* noalias %.global_tid., i32* noalias %.bound_tid., i16* {{[^%]*}}[[ARG:%.+]])
77 // CHECK: = alloca i32*, align
78 // CHECK: = alloca i32*, align
79 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
80 // CHECK: store i16* [[ARG]], i16** [[AA_ADDR]], align
81 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
82 // CHECK: [[VAL:%.+]] = load i16, i16* [[AA]], align
83 // CHECK: store i16 {{%.+}}, i16* [[AA]], align
92 // CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l31}}(
93 // CHECK: [[A_ADDR:%.+]] = alloca i32*, align
94 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
95 // CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align
96 // CHECK: store i32* {{%.+}}, i32** [[A_ADDR]], align
97 // CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align
98 // CHECK: store [10 x i32]* {{%.+}}, [10 x i32]** [[B_ADDR]], align
99 // CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align
100 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
101 // CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align
102 // CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
103 // CHECK: call void @__kmpc_spmd_kernel_init(i32 [[THREAD_LIMIT]],
104 // CHECK: br label {{%?}}[[EXEC:.+]]
107 // CHECK: {{call|invoke}} void [[OP2:@.+]](i32* null, i32* null, i32* [[A]], i16* [[AA]], [10 x i32]* [[B]])
108 // CHECK: br label {{%?}}[[DONE:.+]]
111 // CHECK: call void @__kmpc_spmd_kernel_deinit()
112 // CHECK: br label {{%?}}[[EXIT:.+]]
118 // CHECK: define internal void [[OP2]](i32* noalias %.global_tid., i32* noalias %.bound_tid., i32* {{[^%]*}}[[ARG1:%.+]], i16* {{[^%]*}}[[ARG2:%.+]], [10 x i32]* {{[^%]*}}[[ARG3:%.+]])
119 // CHECK: = alloca i32*, align
120 // CHECK: = alloca i32*, align
121 // CHECK: [[A_ADDR:%.+]] = alloca i32*, align
122 // CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
123 // CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align
124 // CHECK: store i32* [[ARG1]], i32** [[A_ADDR]], align
125 // CHECK: store i16* [[ARG2]], i16** [[AA_ADDR]], align
126 // CHECK: store [10 x i32]* [[ARG3]], [10 x i32]** [[B_ADDR]], align
127 // CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align
128 // CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
129 // CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align
130 // CHECK: store i32 {{%.+}}, i32* [[A]], align
131 // CHECK: store i16 {{%.+}}, i16* [[AA]], align
132 // CHECK: [[ELT:%.+]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]],
133 // CHECK: store i32 {{%.+}}, i32* [[ELT]], align