1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -instcombine -S | FileCheck %s
4 define i32 @select_0_or_1_from_bool(i1 %x) {
5 ; CHECK-LABEL: @select_0_or_1_from_bool(
6 ; CHECK-NEXT: [[TMP1:%.*]] = xor i1 %x, true
7 ; CHECK-NEXT: [[ADD:%.*]] = zext i1 [[TMP1]] to i32
8 ; CHECK-NEXT: ret i32 [[ADD]]
10 %ext = sext i1 %x to i32
11 %add = add i32 %ext, 1
15 define <2 x i32> @select_0_or_1_from_bool_vec(<2 x i1> %x) {
16 ; CHECK-LABEL: @select_0_or_1_from_bool_vec(
17 ; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i1> %x, <i1 true, i1 true>
18 ; CHECK-NEXT: [[ADD:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32>
19 ; CHECK-NEXT: ret <2 x i32> [[ADD]]
21 %ext = sext <2 x i1> %x to <2 x i32>
22 %add = add <2 x i32> %ext, <i32 1, i32 1>
26 ; This is an 'andn' of the low bit.
28 define i32 @flip_and_mask(i32 %x) {
29 ; CHECK-LABEL: @flip_and_mask(
30 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, 1
31 ; CHECK-NEXT: [[INC:%.*]] = xor i32 [[TMP1]], 1
32 ; CHECK-NEXT: ret i32 [[INC]]
35 %shr = ashr i32 %shl, 31
36 %inc = add i32 %shr, 1
40 define <2 x i8> @flip_and_mask_splat(<2 x i8> %x) {
41 ; CHECK-LABEL: @flip_and_mask_splat(
42 ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> %x, <i8 1, i8 1>
43 ; CHECK-NEXT: [[INC:%.*]] = xor <2 x i8> [[TMP1]], <i8 1, i8 1>
44 ; CHECK-NEXT: ret <2 x i8> [[INC]]
46 %shl = shl <2 x i8> %x, <i8 7, i8 7>
47 %shr = ashr <2 x i8> %shl, <i8 7, i8 7>
48 %inc = add <2 x i8> %shr, <i8 1, i8 1>
52 define i32 @test1(i32 %A) {
53 ; CHECK-LABEL: @test1(
54 ; CHECK-NEXT: ret i32 %A
60 define i32 @test2(i32 %A) {
61 ; CHECK-LABEL: @test2(
62 ; CHECK-NEXT: ret i32 %A
69 define i32 @test3(i32 %A) {
70 ; CHECK-LABEL: @test3(
71 ; CHECK-NEXT: ret i32 %A
74 ;; This should get converted to an add
79 define i32 @test4(i32 %A, i32 %B) {
80 ; CHECK-LABEL: @test4(
81 ; CHECK-NEXT: [[D:%.*]] = sub i32 %B, %A
82 ; CHECK-NEXT: ret i32 [[D]]
90 define i32 @test5(i32 %A, i32 %B) {
91 ; CHECK-LABEL: @test5(
92 ; CHECK-NEXT: [[D:%.*]] = sub i32 %B, %A
93 ; CHECK-NEXT: ret i32 [[D]]
101 define i32 @test6(i32 %A) {
102 ; CHECK-LABEL: @test6(
103 ; CHECK-NEXT: [[C:%.*]] = shl i32 %A, 3
104 ; CHECK-NEXT: ret i32 [[C]]
107 ; C = 7*A+A == 8*A == A << 3
112 define i32 @test7(i32 %A) {
113 ; CHECK-LABEL: @test7(
114 ; CHECK-NEXT: [[C:%.*]] = shl i32 %A, 3
115 ; CHECK-NEXT: ret i32 [[C]]
118 ; C = A+7*A == 8*A == A << 3
123 ; (A & C1)+(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
124 define i32 @test8(i32 %A, i32 %B) {
125 ; CHECK-LABEL: @test8(
126 ; CHECK-NEXT: [[A1:%.*]] = and i32 %A, 7
127 ; CHECK-NEXT: [[B1:%.*]] = and i32 %B, 128
128 ; CHECK-NEXT: [[C:%.*]] = or i32 [[A1]], [[B1]]
129 ; CHECK-NEXT: ret i32 [[C]]
132 %B1 = and i32 %B, 128
133 %C = add i32 %A1, %B1
137 define i32 @test9(i32 %A) {
138 ; CHECK-LABEL: @test9(
139 ; CHECK-NEXT: [[C:%.*]] = shl i32 %A, 5
140 ; CHECK-NEXT: ret i32 [[C]]
148 define i1 @test10(i8 %A, i8 %b) {
149 ; CHECK-LABEL: @test10(
150 ; CHECK-NEXT: [[B:%.*]] = sub i8 0, %b
151 ; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[B]], %A
152 ; CHECK-NEXT: ret i1 [[C]]
156 %c = icmp ne i8 %B, 0
160 define <2 x i1> @test10vec(<2 x i8> %a, <2 x i8> %b) {
161 ; CHECK-LABEL: @test10vec(
162 ; CHECK-NEXT: [[C:%.*]] = sub <2 x i8> zeroinitializer, %b
163 ; CHECK-NEXT: [[D:%.*]] = icmp ne <2 x i8> [[C]], %a
164 ; CHECK-NEXT: ret <2 x i1> [[D]]
166 %c = add <2 x i8> %a, %b
167 %d = icmp ne <2 x i8> %c, zeroinitializer
171 define i1 @test11(i8 %A) {
172 ; CHECK-LABEL: @test11(
173 ; CHECK-NEXT: [[C:%.*]] = icmp ne i8 %A, 1
174 ; CHECK-NEXT: ret i1 [[C]]
178 %c = icmp ne i8 %B, 0
182 define <2 x i1> @test11vec(<2 x i8> %a) {
183 ; CHECK-LABEL: @test11vec(
184 ; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i8> %a, <i8 1, i8 1>
185 ; CHECK-NEXT: ret <2 x i1> [[C]]
187 %b = add <2 x i8> %a, <i8 -1, i8 -1>
188 %c = icmp ne <2 x i8> %b, zeroinitializer
192 ; Should be transformed into shl A, 1?
194 define i32 @test12(i32 %A, i32 %B) {
195 ; CHECK-LABEL: @test12(
196 ; CHECK-NEXT: br label %X
198 ; CHECK-NEXT: [[C_OK:%.*]] = add i32 %B, %A
199 ; CHECK-NEXT: [[D:%.*]] = add i32 [[C_OK]], %A
200 ; CHECK-NEXT: ret i32 [[D]]
202 %C_OK = add i32 %B, %A
206 %D = add i32 %C_OK, %A
210 define i32 @test13(i32 %A, i32 %B, i32 %C) {
211 ; CHECK-LABEL: @test13(
212 ; CHECK-NEXT: [[D_OK:%.*]] = add i32 %A, %B
213 ; CHECK-NEXT: [[E_OK:%.*]] = add i32 [[D_OK]], %C
214 ; CHECK-NEXT: [[F:%.*]] = add i32 [[E_OK]], %A
215 ; CHECK-NEXT: ret i32 [[F]]
217 %D_OK = add i32 %A, %B
218 %E_OK = add i32 %D_OK, %C
220 %F = add i32 %E_OK, %A
224 define i32 @test14(i32 %offset, i32 %difference) {
225 ; CHECK-LABEL: @test14(
226 ; CHECK-NEXT: [[TMP_2:%.*]] = and i32 %difference, 3
227 ; CHECK-NEXT: [[TMP_3_OK:%.*]] = add i32 [[TMP_2]], %offset
228 ; CHECK-NEXT: [[TMP_5_MASK:%.*]] = and i32 %difference, -4
229 ; CHECK-NEXT: [[TMP_8:%.*]] = add i32 [[TMP_3_OK]], [[TMP_5_MASK]]
230 ; CHECK-NEXT: ret i32 [[TMP_8]]
232 %tmp.2 = and i32 %difference, 3
233 %tmp.3_OK = add i32 %tmp.2, %offset
234 %tmp.5.mask = and i32 %difference, -4
235 ; == add %offset, %difference
236 %tmp.8 = add i32 %tmp.3_OK, %tmp.5.mask
240 define i8 @test15(i8 %A) {
241 ; CHECK-LABEL: @test15(
242 ; CHECK-NEXT: [[C:%.*]] = and i8 %A, 16
243 ; CHECK-NEXT: ret i8 [[C]]
251 define i8 @test16(i8 %A) {
252 ; CHECK-LABEL: @test16(
253 ; CHECK-NEXT: [[B:%.*]] = and i8 %A, 16
254 ; CHECK-NEXT: [[C:%.*]] = xor i8 [[B]], 16
255 ; CHECK-NEXT: ret i8 [[C]]
263 define i32 @test17(i32 %A) {
264 ; CHECK-LABEL: @test17(
265 ; CHECK-NEXT: [[C:%.*]] = sub i32 0, %A
266 ; CHECK-NEXT: ret i32 [[C]]
273 define i8 @test18(i8 %A) {
274 ; CHECK-LABEL: @test18(
275 ; CHECK-NEXT: [[C:%.*]] = sub i8 16, %A
276 ; CHECK-NEXT: ret i8 [[C]]
283 define <2 x i64> @test18vec(<2 x i64> %A) {
284 ; CHECK-LABEL: @test18vec(
285 ; CHECK-NEXT: [[ADD:%.*]] = sub <2 x i64> <i64 1, i64 2>, %A
286 ; CHECK-NEXT: ret <2 x i64> [[ADD]]
288 %xor = xor <2 x i64> %A, <i64 -1, i64 -1>
289 %add = add <2 x i64> %xor, <i64 2, i64 3>
293 define i32 @test19(i1 %C) {
294 ; CHECK-LABEL: @test19(
295 ; CHECK-NEXT: [[V:%.*]] = select i1 %C, i32 1123, i32 133
296 ; CHECK-NEXT: ret i32 [[V]]
298 %A = select i1 %C, i32 1000, i32 10
303 define <2 x i32> @test19vec(i1 %C) {
304 ; CHECK-LABEL: @test19vec(
305 ; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1123, i32 1123>, <2 x i32> <i32 133, i32 133>
306 ; CHECK-NEXT: ret <2 x i32> [[V]]
308 %A = select i1 %C, <2 x i32> <i32 1000, i32 1000>, <2 x i32> <i32 10, i32 10>
309 %V = add <2 x i32> %A, <i32 123, i32 123>
313 ; This is an InstSimplify fold, but test it here to make sure that
314 ; InstCombine does not prevent the fold.
315 ; With NSW, add of sign bit -> or of sign bit.
317 define i32 @test20(i32 %x) {
318 ; CHECK-LABEL: @test20(
319 ; CHECK-NEXT: ret i32 %x
321 %y = xor i32 %x, -2147483648
322 %z = add nsw i32 %y, -2147483648
326 define i32 @xor_sign_bit(i32 %x) {
327 ; CHECK-LABEL: @xor_sign_bit(
328 ; CHECK-NEXT: [[ADD:%.*]] = add i32 %x, -2147483606
329 ; CHECK-NEXT: ret i32 [[ADD]]
331 %xor = xor i32 %x, 2147483648
332 %add = add i32 %xor, 42
336 ; No-wrap info allows converting the add to 'or'.
338 define i8 @add_nsw_signbit(i8 %x) {
339 ; CHECK-LABEL: @add_nsw_signbit(
340 ; CHECK-NEXT: [[Y:%.*]] = or i8 %x, -128
341 ; CHECK-NEXT: ret i8 [[Y]]
343 %y = add nsw i8 %x, -128
347 ; No-wrap info allows converting the add to 'or'.
349 define i8 @add_nuw_signbit(i8 %x) {
350 ; CHECK-LABEL: @add_nuw_signbit(
351 ; CHECK-NEXT: [[Y:%.*]] = or i8 %x, -128
352 ; CHECK-NEXT: ret i8 [[Y]]
354 %y = add nuw i8 %x, 128
358 define i1 @test21(i32 %x) {
359 ; CHECK-LABEL: @test21(
360 ; CHECK-NEXT: [[Y:%.*]] = icmp eq i32 %x, 119
361 ; CHECK-NEXT: ret i1 [[Y]]
364 %y = icmp eq i32 %t, 123
368 define <2 x i1> @test21vec(<2 x i32> %x) {
369 ; CHECK-LABEL: @test21vec(
370 ; CHECK-NEXT: [[Y:%.*]] = icmp eq <2 x i32> %x, <i32 119, i32 119>
371 ; CHECK-NEXT: ret <2 x i1> [[Y]]
373 %t = add <2 x i32> %x, <i32 4, i32 4>
374 %y = icmp eq <2 x i32> %t, <i32 123, i32 123>
378 define i32 @test22(i32 %V) {
379 ; CHECK-LABEL: @test22(
380 ; CHECK-NEXT: switch i32 %V, label %Default [
381 ; CHECK-NEXT: i32 10, label %Lab1
382 ; CHECK-NEXT: i32 20, label %Lab2
385 ; CHECK-NEXT: ret i32 123
387 ; CHECK-NEXT: ret i32 12312
389 ; CHECK-NEXT: ret i32 1231231
392 switch i32 %V2, label %Default [
397 Default: ; preds = %0
407 define i32 @test23(i1 %C, i32 %a) {
408 ; CHECK-LABEL: @test23(
410 ; CHECK-NEXT: br i1 %C, label %endif, label %else
412 ; CHECK-NEXT: br label %endif
414 ; CHECK-NEXT: [[B_0:%.*]] = phi i32 [ 1, %entry ], [ 2, %else ]
415 ; CHECK-NEXT: ret i32 [[B_0]]
418 br i1 %C, label %endif, label %else
420 else: ; preds = %entry
423 endif: ; preds = %else, %entry
424 %b.0 = phi i32 [ 0, %entry ], [ 1, %else ]
425 %tmp.4 = add i32 %b.0, 1
429 define i32 @test24(i32 %A) {
430 ; CHECK-LABEL: @test24(
431 ; CHECK-NEXT: [[B:%.*]] = shl i32 %A, 1
432 ; CHECK-NEXT: ret i32 [[B]]
440 define i64 @test25(i64 %Y) {
441 ; CHECK-LABEL: @test25(
442 ; CHECK-NEXT: [[TMP_8:%.*]] = shl i64 %Y, 3
443 ; CHECK-NEXT: ret i64 [[TMP_8]]
445 %tmp.4 = shl i64 %Y, 2
446 %tmp.12 = shl i64 %Y, 2
447 %tmp.8 = add i64 %tmp.4, %tmp.12
451 define i32 @test26(i32 %A, i32 %B) {
452 ; CHECK-LABEL: @test26(
453 ; CHECK-NEXT: ret i32 %A
460 define i32 @test27(i1 %C, i32 %X, i32 %Y) {
461 ; CHECK-LABEL: @test27(
462 ; CHECK-NEXT: [[C_UPGRD_1_V:%.*]] = select i1 %C, i32 %X, i32 123
463 ; CHECK-NEXT: ret i32 [[C_UPGRD_1_V]]
467 ;; Fold add through select.
468 %C.upgrd.1 = select i1 %C, i32 %A, i32 %B
469 %D = sub i32 %C.upgrd.1, %Y
473 define i32 @test28(i32 %X) {
474 ; CHECK-LABEL: @test28(
475 ; CHECK-NEXT: [[Z:%.*]] = sub i32 -1192, %X
476 ; CHECK-NEXT: ret i32 [[Z]]
478 %Y = add i32 %X, 1234
483 define i32 @test29(i32 %X, i32 %x) {
484 ; CHECK-LABEL: @test29(
485 ; CHECK-NEXT: [[TMP_2:%.*]] = sub i32 %X, %x
486 ; CHECK-NEXT: [[TMP_7:%.*]] = and i32 %X, 63
487 ; CHECK-NEXT: [[TMP_9:%.*]] = and i32 [[TMP_2]], -64
488 ; CHECK-NEXT: [[TMP_10:%.*]] = or i32 [[TMP_7]], [[TMP_9]]
489 ; CHECK-NEXT: ret i32 [[TMP_10]]
491 %tmp.2 = sub i32 %X, %x
492 %tmp.2.mask = and i32 %tmp.2, 63
493 %tmp.6 = add i32 %tmp.2.mask, %x
494 %tmp.7 = and i32 %tmp.6, 63
495 %tmp.9 = and i32 %tmp.2, -64
496 %tmp.10 = or i32 %tmp.7, %tmp.9
500 define i64 @test30(i64 %x) {
501 ; CHECK-LABEL: @test30(
502 ; CHECK-NEXT: ret i64 %x
504 %tmp.2 = xor i64 %x, -9223372036854775808
505 ;; Add of sign bit -> xor of sign bit.
506 %tmp.4 = add i64 %tmp.2, -9223372036854775808
510 define i32 @test31(i32 %A) {
511 ; CHECK-LABEL: @test31(
512 ; CHECK-NEXT: [[TMP1:%.*]] = mul i32 %A, 5
513 ; CHECK-NEXT: ret i32 [[TMP1]]
521 define i32 @test32(i32 %A) {
522 ; CHECK-LABEL: @test32(
523 ; CHECK-NEXT: [[B:%.*]] = shl i32 %A, 2
524 ; CHECK-NEXT: ret i32 [[B]]
532 define i8 @test33(i8 %A) {
533 ; CHECK-LABEL: @test33(
534 ; CHECK-NEXT: [[C:%.*]] = or i8 %A, 1
535 ; CHECK-NEXT: ret i8 [[C]]
542 define i8 @test34(i8 %A) {
543 ; CHECK-LABEL: @test34(
544 ; CHECK-NEXT: [[C:%.*]] = and i8 %A, 12
545 ; CHECK-NEXT: ret i8 [[C]]
552 define i32 @test35(i32 %a) {
553 ; CHECK-LABEL: @test35(
554 ; CHECK-NEXT: ret i32 -1
556 %tmpnot = xor i32 %a, -1
557 %tmp2 = add i32 %tmpnot, %a
561 define i32 @test36(i32 %a) {
562 ; CHECK-LABEL: @test36(
563 ; CHECK-NEXT: ret i32 0
566 %y = and i32 %a, -126
568 %q = and i32 %z, 1 ; always zero
572 define i1 @test37(i32 %a, i32 %b) {
573 ; CHECK-LABEL: @test37(
574 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %b, 0
575 ; CHECK-NEXT: ret i1 [[CMP]]
577 %add = add i32 %a, %b
578 %cmp = icmp eq i32 %add, %a
582 define i1 @test38(i32 %a, i32 %b) {
583 ; CHECK-LABEL: @test38(
584 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %a, 0
585 ; CHECK-NEXT: ret i1 [[CMP]]
587 %add = add i32 %a, %b
588 %cmp = icmp eq i32 %add, %b
592 define i1 @test39(i32 %a, i32 %b) {
593 ; CHECK-LABEL: @test39(
594 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %b, 0
595 ; CHECK-NEXT: ret i1 [[CMP]]
597 %add = add i32 %b, %a
598 %cmp = icmp eq i32 %add, %a
602 define i1 @test40(i32 %a, i32 %b) {
603 ; CHECK-LABEL: @test40(
604 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %a, 0
605 ; CHECK-NEXT: ret i1 [[CMP]]
607 %add = add i32 %b, %a
608 %cmp = icmp eq i32 %add, %b
612 ; (add (zext (add nuw X, C2)), C) --> (zext (add nuw X, C2 + C))
614 define i64 @test41(i32 %a) {
615 ; CHECK-LABEL: @test41(
616 ; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 %a, 15
617 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[ADD]] to i64
618 ; CHECK-NEXT: ret i64 [[EXT]]
620 %add = add nuw i32 %a, 16
621 %zext = zext i32 %add to i64
622 %sub = add i64 %zext, -1
626 ; (add (zext (add nuw X, C2)), C) --> (zext (add nuw X, C2 + C))
628 define <2 x i64> @test41vec(<2 x i32> %a) {
629 ; CHECK-LABEL: @test41vec(
630 ; CHECK-NEXT: [[TMP1:%.*]] = add nuw <2 x i32> %a, <i32 15, i32 15>
631 ; CHECK-NEXT: [[SUB:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
632 ; CHECK-NEXT: ret <2 x i64> [[SUB]]
634 %add = add nuw <2 x i32> %a, <i32 16, i32 16>
635 %zext = zext <2 x i32> %add to <2 x i64>
636 %sub = add <2 x i64> %zext, <i64 -1, i64 -1>
640 define <2 x i64> @test41vec_and_multiuse(<2 x i32> %a) {
641 ; CHECK-LABEL: @test41vec_and_multiuse(
642 ; CHECK-NEXT: [[ADD:%.*]] = add nuw <2 x i32> %a, <i32 16, i32 16>
643 ; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[ADD]] to <2 x i64>
644 ; CHECK-NEXT: [[SUB:%.*]] = add nsw <2 x i64> [[ZEXT]], <i64 -1, i64 -1>
645 ; CHECK-NEXT: [[EXTRAUSE:%.*]] = add nsw <2 x i64> [[SUB]], [[ZEXT]]
646 ; CHECK-NEXT: ret <2 x i64> [[EXTRAUSE]]
648 %add = add nuw <2 x i32> %a, <i32 16, i32 16>
649 %zext = zext <2 x i32> %add to <2 x i64>
650 %sub = add <2 x i64> %zext, <i64 -1, i64 -1>
651 %extrause = add <2 x i64> %zext, %sub
652 ret <2 x i64> %extrause
655 define i32 @test42(i1 %C) {
656 ; CHECK-LABEL: @test42(
657 ; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], i32 1123, i32 133
658 ; CHECK-NEXT: ret i32 [[V]]
660 %A = select i1 %C, i32 1000, i32 10
665 define <2 x i32> @test42vec(i1 %C) {
666 ; CHECK-LABEL: @test42vec(
667 ; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1123, i32 1123>, <2 x i32> <i32 133, i32 133>
668 ; CHECK-NEXT: ret <2 x i32> [[V]]
670 %A = select i1 %C, <2 x i32> <i32 1000, i32 1000>, <2 x i32> <i32 10, i32 10>
671 %V = add <2 x i32> <i32 123, i32 123>, %A
675 define <2 x i32> @test42vec2(i1 %C) {
676 ; CHECK-LABEL: @test42vec2(
677 ; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1123, i32 2833>, <2 x i32> <i32 133, i32 363>
678 ; CHECK-NEXT: ret <2 x i32> [[V]]
680 %A = select i1 %C, <2 x i32> <i32 1000, i32 2500>, <2 x i32> <i32 10, i32 30>
681 %V = add <2 x i32> <i32 123, i32 333>, %A
685 define i32 @test55(i1 %which) {
686 ; CHECK-LABEL: @test55(
688 ; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
690 ; CHECK-NEXT: br label [[FINAL]]
692 ; CHECK-NEXT: [[A:%.*]] = phi i32 [ 1123, [[ENTRY:%.*]] ], [ 133, [[DELAY]] ]
693 ; CHECK-NEXT: ret i32 [[A]]
696 br i1 %which, label %final, label %delay
702 %A = phi i32 [ 1000, %entry ], [ 10, %delay ]
703 %value = add i32 123, %A
707 define <2 x i32> @test43vec(i1 %which) {
708 ; CHECK-LABEL: @test43vec(
710 ; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
712 ; CHECK-NEXT: br label [[FINAL]]
714 ; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1123, i32 1123>, [[ENTRY:%.*]] ], [ <i32 133, i32 133>, [[DELAY]] ]
715 ; CHECK-NEXT: ret <2 x i32> [[A]]
718 br i1 %which, label %final, label %delay
724 %A = phi <2 x i32> [ <i32 1000, i32 1000>, %entry ], [ <i32 10, i32 10>, %delay ]
725 %value = add <2 x i32> <i32 123, i32 123>, %A
729 define <2 x i32> @test43vec2(i1 %which) {
730 ; CHECK-LABEL: @test43vec2(
732 ; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
734 ; CHECK-NEXT: br label [[FINAL]]
736 ; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1123, i32 2833>, [[ENTRY:%.*]] ], [ <i32 133, i32 363>, [[DELAY]] ]
737 ; CHECK-NEXT: ret <2 x i32> [[A]]
740 br i1 %which, label %final, label %delay
746 %A = phi <2 x i32> [ <i32 1000, i32 2500>, %entry ], [ <i32 10, i32 30>, %delay ]
747 %value = add <2 x i32> <i32 123, i32 333>, %A