tools/tools/ath/common/dumpregs_5212.c

   1 /*-
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  *
  16  * NO WARRANTY
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27  * THE POSSIBILITY OF SUCH DAMAGES.
  28  *
  29  * $FreeBSD$
  30  */
  31
  32 #include <sys/param.h>
  33
  34 #include "diag.h"
  35
  36 #include "ah.h"
  37 #include "ah_internal.h"
  38 #include "ar5212/ar5212reg.h"
  39 #include "ar5212/ar5212phy.h"
  40
  41 #include "dumpregs.h"
  42
  43 #define MAC5212 SREV(4,5), SREV(16,0)
  44 #define MAC5213 SREV(5,9), SREV(16,0)
  45
  46 static struct dumpreg ar5212regs[] = {
  47     DEFBASIC(AR_CR,             "CR"),
  48     DEFBASIC(AR_RXDP,           "RXDP"),
  49     DEFBASICfmt(AR_CFG,         "CFG",
  50            "\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\6AP_ADHOC\11PHOK\12EEBS"),
  51     DEFBASIC(AR_IER,            "IER"),
  52     DEFBASIC(AR_TXCFG,          "TXCFG"),
  53     DEFBASICfmt(AR_RXCFG,       "RXCFG",
  54           "\20\6JUMBO_ENA\7JUMBO_WRAP\10SLEEP_DEBUG"),
  55     DEFBASIC(AR_MIBC,           "MIBC"),
  56     DEFBASIC(AR_TOPS,           "TOPS"),
  57     DEFBASIC(AR_RXNPTO,         "RXNPTO"),
  58     DEFBASIC(AR_TXNPTO,         "TXNPTO"),
  59     DEFBASIC(AR_RPGTO,          "RPGTO"),
  60     DEFBASIC(AR_RPCNT,          "RPCNT"),
  61     DEFBASIC(AR_MACMISC,        "MACMISC"),
  62     DEFBASIC(AR_SPC_0,          "SPC_0"),
  63     DEFBASIC(AR_SPC_1,          "SPC_1"),
  64
  65     DEFINTfmt(AR_ISR,           "ISR",
  66           "\20\1RXOK\2RXDESC\3RXERR\4RXNOPKT\5RXEOL\6RXORN\7TXOK\10TXDESC"
  67           "\11TXERR\12TXNOPKT\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM"
  68           "\21SWBA\22BRSSI\23BMISS\24HIUERR\25BNR\26RXCHIRP\27RXDOPPL\30BCNMISS"
  69           "\31TIM\32GPIO\33QCBROVF\34QCBRURN\35QTRIG"),
  70     DEFINT(AR_ISR_S0,           "ISR_S0"),
  71     DEFINT(AR_ISR_S1,           "ISR_S1"),
  72     DEFINTfmt(AR_ISR_S2,        "ISR_S2",
  73           "\20\21MCABT\22SSERR\23DPERR\24TIM\25CABEND\26DTIMSYNC\27BCNTO"
  74           "\30CABTO\31DTIM"),
  75     DEFINT(AR_ISR_S3,           "ISR_S3"),
  76     DEFINT(AR_ISR_S4,           "ISR_S4"),
  77     DEFINTfmt(AR_IMR,           "IMR",
  78           "\20\1RXOK\2RXDESC\3RXERR\4RXNOPKT\5RXEOL\6RXORN\7TXOK\10TXDESC"
  79           "\11TXERR\12TXNOPKT\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM"
  80           "\21SWBA\22BRSSI\23BMISS\24HIUERR\25BNR\26RXCHIRP\27RXDOPPL\30BCNMISS"
  81           "\31TIM\32GPIO\33QCBROVF\34QCBRURN\35QTRIG"),
  82     DEFINT(AR_IMR_S0,           "IMR_S0"),
  83     DEFINT(AR_IMR_S1,           "IMR_S1"),
  84     DEFINTfmt(AR_IMR_S2,        "IMR_S2",
  85           "\20\21MCABT\22SSERR\23DPERR\24TIM\25CABEND\26DTIMSYNC\27BCNTO"
  86           "\30CABTO\31DTIM"),
  87     DEFINT(AR_IMR_S3,           "IMR_S3"),
  88     DEFINT(AR_IMR_S4,           "IMR_S4"),
  89     /* NB: don't read the RAC so we don't affect operation */
  90     DEFVOID(AR_ISR_RAC,         "ISR_RAC"),
  91     DEFINT(AR_ISR_S0_S,         "ISR_S0_S"),
  92     DEFINT(AR_ISR_S1_S,         "ISR_S1_S"),
  93     DEFINT(AR_ISR_S2_S,         "ISR_S2_S"),
  94     DEFINT(AR_ISR_S3_S,         "ISR_S3_S"),
  95     DEFINT(AR_ISR_S4_S,         "ISR_S4_S"),
  96
  97     DEFBASIC(AR_DMADBG_0,       "DMADBG0"),
  98     DEFBASIC(AR_DMADBG_1,       "DMADBG1"),
  99     DEFBASIC(AR_DMADBG_2,       "DMADBG2"),
 100     DEFBASIC(AR_DMADBG_3,       "DMADBG3"),
 101     DEFBASIC(AR_DMADBG_4,       "DMADBG4"),
 102     DEFBASIC(AR_DMADBG_5,       "DMADBG5"),
 103     DEFBASIC(AR_DMADBG_6,       "DMADBG6"),
 104     DEFBASIC(AR_DMADBG_7,       "DMADBG7"),
 105
 106     DEFBASIC(AR_DCM_A,          "DCM_A"),
 107     DEFBASIC(AR_DCM_D,          "DCM_D"),
 108     DEFBASIC(AR_DCCFG,          "DCCFG"),
 109     DEFBASIC(AR_CCFG,           "CCFG"),
 110     DEFBASIC(AR_CCUCFG,         "CCUCFG"),
 111     DEFBASIC(AR_CPC_0,          "CPC0"),
 112     DEFBASIC(AR_CPC_1,          "CPC1"),
 113     DEFBASIC(AR_CPC_2,          "CPC2"),
 114     DEFBASIC(AR_CPC_3,          "CPC3"),
 115     DEFBASIC(AR_CPCOVF,         "CPCOVF"),
 116
 117     DEFQCU(AR_Q0_TXDP,          "Q0_TXDP"),
 118     DEFQCU(AR_Q1_TXDP,          "Q1_TXDP"),
 119     DEFQCU(AR_Q2_TXDP,          "Q2_TXDP"),
 120     DEFQCU(AR_Q3_TXDP,          "Q3_TXDP"),
 121     DEFQCU(AR_Q4_TXDP,          "Q4_TXDP"),
 122     DEFQCU(AR_Q5_TXDP,          "Q5_TXDP"),
 123     DEFQCU(AR_Q6_TXDP,          "Q6_TXDP"),
 124     DEFQCU(AR_Q7_TXDP,          "Q7_TXDP"),
 125     DEFQCU(AR_Q8_TXDP,          "Q8_TXDP"),
 126     DEFQCU(AR_Q9_TXDP,          "Q9_TXDP"),
 127
 128     DEFQCU(AR_Q_TXE,            "Q_TXE"),
 129     DEFQCU(AR_Q_TXD,            "Q_TXD"),
 130
 131     DEFQCU(AR_Q0_CBRCFG,        "Q0_CBR"),
 132     DEFQCU(AR_Q1_CBRCFG,        "Q1_CBR"),
 133     DEFQCU(AR_Q2_CBRCFG,        "Q2_CBR"),
 134     DEFQCU(AR_Q3_CBRCFG,        "Q3_CBR"),
 135     DEFQCU(AR_Q4_CBRCFG,        "Q4_CBR"),
 136     DEFQCU(AR_Q5_CBRCFG,        "Q5_CBR"),
 137     DEFQCU(AR_Q6_CBRCFG,        "Q6_CBR"),
 138     DEFQCU(AR_Q7_CBRCFG,        "Q7_CBR"),
 139     DEFQCU(AR_Q8_CBRCFG,        "Q8_CBR"),
 140     DEFQCU(AR_Q9_CBRCFG,        "Q9_CBR"),
 141
 142     DEFQCU(AR_Q0_RDYTIMECFG,    "Q0_RDYT"),
 143     DEFQCU(AR_Q1_RDYTIMECFG,    "Q1_RDYT"),
 144     DEFQCU(AR_Q2_RDYTIMECFG,    "Q2_RDYT"),
 145     DEFQCU(AR_Q3_RDYTIMECFG,    "Q3_RDYT"),
 146     DEFQCU(AR_Q4_RDYTIMECFG,    "Q4_RDYT"),
 147     DEFQCU(AR_Q5_RDYTIMECFG,    "Q5_RDYT"),
 148     DEFQCU(AR_Q6_RDYTIMECFG,    "Q6_RDYT"),
 149     DEFQCU(AR_Q7_RDYTIMECFG,    "Q7_RDYT"),
 150     DEFQCU(AR_Q8_RDYTIMECFG,    "Q8_RDYT"),
 151     DEFQCU(AR_Q9_RDYTIMECFG,    "Q9_RDYT"),
 152
 153     DEFQCU(AR_Q_ONESHOTARM_SC,  "Q_ONESHOTARM_SC"),
 154     DEFQCU(AR_Q_ONESHOTARM_CC,  "Q_ONESHOTARM_CC"),
 155
 156     DEFQCU(AR_Q0_MISC,          "Q0_MISC"),
 157     DEFQCU(AR_Q1_MISC,          "Q1_MISC"),
 158     DEFQCU(AR_Q2_MISC,          "Q2_MISC"),
 159     DEFQCU(AR_Q3_MISC,          "Q3_MISC"),
 160     DEFQCU(AR_Q4_MISC,          "Q4_MISC"),
 161     DEFQCU(AR_Q5_MISC,          "Q5_MISC"),
 162     DEFQCU(AR_Q6_MISC,          "Q6_MISC"),
 163     DEFQCU(AR_Q7_MISC,          "Q7_MISC"),
 164     DEFQCU(AR_Q8_MISC,          "Q8_MISC"),
 165     DEFQCU(AR_Q9_MISC,          "Q9_MISC"),
 166
 167     DEFQCU(AR_Q0_STS,           "Q0_STS"),
 168     DEFQCU(AR_Q1_STS,           "Q1_STS"),
 169     DEFQCU(AR_Q2_STS,           "Q2_STS"),
 170     DEFQCU(AR_Q3_STS,           "Q3_STS"),
 171     DEFQCU(AR_Q4_STS,           "Q4_STS"),
 172     DEFQCU(AR_Q5_STS,           "Q5_STS"),
 173     DEFQCU(AR_Q6_STS,           "Q6_STS"),
 174     DEFQCU(AR_Q7_STS,           "Q7_STS"),
 175     DEFQCU(AR_Q8_STS,           "Q8_STS"),
 176     DEFQCU(AR_Q9_STS,           "Q9_STS"),
 177
 178     DEFQCU(AR_Q_RDYTIMESHDN,    "Q_RDYTIMSHD"),
 179
 180     DEFQCU(AR_Q_CBBS,           "Q_CBBS"),
 181     DEFQCU(AR_Q_CBBA,           "Q_CBBA"),
 182     DEFQCU(AR_Q_CBC,            "Q_CBC"),
 183
 184     DEFDCU(AR_D0_QCUMASK,       "D0_MASK"),
 185     DEFDCU(AR_D1_QCUMASK,       "D1_MASK"),
 186     DEFDCU(AR_D2_QCUMASK,       "D2_MASK"),
 187     DEFDCU(AR_D3_QCUMASK,       "D3_MASK"),
 188     DEFDCU(AR_D4_QCUMASK,       "D4_MASK"),
 189     DEFDCU(AR_D5_QCUMASK,       "D5_MASK"),
 190     DEFDCU(AR_D6_QCUMASK,       "D6_MASK"),
 191     DEFDCU(AR_D7_QCUMASK,       "D7_MASK"),
 192     DEFDCU(AR_D8_QCUMASK,       "D8_MASK"),
 193     DEFDCU(AR_D9_QCUMASK,       "D9_MASK"),
 194
 195     DEFDCU(AR_D0_LCL_IFS,       "D0_IFS"),
 196     DEFDCU(AR_D1_LCL_IFS,       "D1_IFS"),
 197     DEFDCU(AR_D2_LCL_IFS,       "D2_IFS"),
 198     DEFDCU(AR_D3_LCL_IFS,       "D3_IFS"),
 199     DEFDCU(AR_D4_LCL_IFS,       "D4_IFS"),
 200     DEFDCU(AR_D5_LCL_IFS,       "D5_IFS"),
 201     DEFDCU(AR_D6_LCL_IFS,       "D6_IFS"),
 202     DEFDCU(AR_D7_LCL_IFS,       "D7_IFS"),
 203     DEFDCU(AR_D8_LCL_IFS,       "D8_IFS"),
 204     DEFDCU(AR_D9_LCL_IFS,       "D9_IFS"),
 205
 206     DEFDCU(AR_D0_RETRY_LIMIT,   "D0_RTRY"),
 207     DEFDCU(AR_D1_RETRY_LIMIT,   "D1_RTRY"),
 208     DEFDCU(AR_D2_RETRY_LIMIT,   "D2_RTRY"),
 209     DEFDCU(AR_D3_RETRY_LIMIT,   "D3_RTRY"),
 210     DEFDCU(AR_D4_RETRY_LIMIT,   "D4_RTRY"),
 211     DEFDCU(AR_D5_RETRY_LIMIT,   "D5_RTRY"),
 212     DEFDCU(AR_D6_RETRY_LIMIT,   "D6_RTRY"),
 213     DEFDCU(AR_D7_RETRY_LIMIT,   "D7_RTRY"),
 214     DEFDCU(AR_D8_RETRY_LIMIT,   "D8_RTRY"),
 215     DEFDCU(AR_D9_RETRY_LIMIT,   "D9_RTRY"),
 216
 217     DEFDCU(AR_D0_CHNTIME,       "D0_CHNT"),
 218     DEFDCU(AR_D1_CHNTIME,       "D1_CHNT"),
 219     DEFDCU(AR_D2_CHNTIME,       "D2_CHNT"),
 220     DEFDCU(AR_D3_CHNTIME,       "D3_CHNT"),
 221     DEFDCU(AR_D4_CHNTIME,       "D4_CHNT"),
 222     DEFDCU(AR_D5_CHNTIME,       "D5_CHNT"),
 223     DEFDCU(AR_D6_CHNTIME,       "D6_CHNT"),
 224     DEFDCU(AR_D7_CHNTIME,       "D7_CHNT"),
 225     DEFDCU(AR_D8_CHNTIME,       "D8_CHNT"),
 226     DEFDCU(AR_D9_CHNTIME,       "D9_CHNT"),
 227
 228     DEFDCU(AR_D0_MISC,          "D0_MISC"),
 229     DEFDCU(AR_D1_MISC,          "D1_MISC"),
 230     DEFDCU(AR_D2_MISC,          "D2_MISC"),
 231     DEFDCU(AR_D3_MISC,          "D3_MISC"),
 232     DEFDCU(AR_D4_MISC,          "D4_MISC"),
 233     DEFDCU(AR_D5_MISC,          "D5_MISC"),
 234     DEFDCU(AR_D6_MISC,          "D6_MISC"),
 235     DEFDCU(AR_D7_MISC,          "D7_MISC"),
 236     DEFDCU(AR_D8_MISC,          "D8_MISC"),
 237     DEFDCU(AR_D9_MISC,          "D9_MISC"),
 238
 239     _DEFREG(AR_D_SEQNUM,        "D_SEQ",        DUMP_BASIC | DUMP_DCU),
 240     DEFBASIC(AR_D_GBL_IFS_SIFS, "D_SIFS"),
 241     DEFBASIC(AR_D_GBL_IFS_SLOT, "D_SLOT"),
 242     DEFBASIC(AR_D_GBL_IFS_EIFS, "D_EIFS"),
 243     DEFBASIC(AR_D_GBL_IFS_MISC, "D_MISC"),
 244     DEFBASIC(AR_D_FPCTL,        "D_FPCTL"),
 245     DEFBASIC(AR_D_TXPSE,        "D_TXPSE"),
 246     DEFVOID(AR_D_TXBLK_CMD,     "D_CMD"),
 247 #if 0
 248     DEFVOID(AR_D_TXBLK_DATA,    "D_DATA"),
 249 #endif
 250     DEFVOID(AR_D_TXBLK_CLR,     "D_CLR"),
 251     DEFVOID(AR_D_TXBLK_SET,     "D_SET"),
 252     DEFBASIC(AR_RC,             "RC"),
 253     DEFBASICfmt(AR_SCR,         "SCR",
 254           "\20\22SLDTP\23SLDWP\24SLEPOL\25MIBIE"),
 255     DEFBASIC(AR_INTPEND,        "INTPEND"),
 256     DEFBASIC(AR_SFR,            "SFR"),
 257     DEFBASIC(AR_PCICFG,         "PCICFG"),
 258     DEFBASIC(AR_GPIOCR,         "GPIOCR"),
 259     DEFBASIC(AR_GPIODO,         "GPIODO"),
 260     DEFBASIC(AR_GPIODI,         "GPIODI"),
 261     DEFBASIC(AR_SREV,           "SREV"),
 262
 263     DEFBASICx(AR_PCIE_PMC,      "PCIEPMC", SREV(4,8), SREV(13,7)),
 264     DEFBASICx(AR_PCIE_SERDES,   "SERDES",  SREV(4,8), SREV(13,7)),
 265     DEFBASICx(AR_PCIE_SERDES2,  "SERDES2", SREV(4,8), SREV(13,7)),
 266     DEFVOID(AR_EEPROM_ADDR,     "EEADDR"),
 267     DEFVOID(AR_EEPROM_DATA,     "EEDATA"),
 268     DEFVOID(AR_EEPROM_CMD,      "EECMD"),
 269     DEFVOID(AR_EEPROM_STS,      "EESTS"),
 270     DEFVOID(AR_EEPROM_CFG,      "EECFG"),
 271     DEFBASIC(AR_STA_ID0,        "STA_ID0"),
 272     DEFBASICfmt(AR_STA_ID1,     "STA_ID1",
 273           "\20\21STA_AP\22ADHOC\23PWR_SAV\24KSRCHDIS\25PCF\26USE_DEFANT"
 274           "\27UPD_DEFANT\30RTS_USE_DEF\31ACKCTS_6MB\32BASE_RATE11B\33USE_DA_SG"
 275           "\34CRPT_MIC_ENABLE\35KSRCH_MODE\36PRE_SEQNUM\37CBCIV_ENDIAN"
 276           "\40MCAST_KSRCH"),
 277     DEFBASIC(AR_BSS_ID0,        "BSS_ID0"),
 278     DEFBASIC(AR_BSS_ID1,        "BSS_ID1"),
 279     DEFBASIC(AR_SLOT_TIME,      "SLOTTIME"),
 280     DEFBASIC(AR_TIME_OUT,       "TIME_OUT"),
 281     DEFBASIC(AR_RSSI_THR,       "RSSI_THR"),
 282     DEFBASIC(AR_USEC,           "USEC"),
 283     DEFBASIC(AR_BEACON,         "BEACON"),
 284     DEFBASIC(AR_CFP_PERIOD,     "CFP_PER"),
 285     DEFBASIC(AR_TIMER0,         "TIMER0"),
 286     DEFBASIC(AR_TIMER1,         "TIMER1"),
 287     DEFBASIC(AR_TIMER2,         "TIMER2"),
 288     DEFBASIC(AR_TIMER3,         "TIMER3"),
 289     DEFBASIC(AR_CFP_DUR,        "CFP_DUR"),
 290     DEFBASICfmt(AR_RX_FILTER,   "RXFILTER",
 291           "\20\1UCAST\2MCAST\3BCAST\4CONTROL\5BEACON\6PROM\7XR_POLL\10PROBE_REQ"),
 292     DEFBASIC(AR_MCAST_FIL0,     "MCAST_0"),
 293     DEFBASIC(AR_MCAST_FIL1,     "MCAST_1"),
 294     DEFBASICfmt(AR_DIAG_SW,     "DIAG_SW",
 295           "\20\1CACHE_ACK\2ACK_DIS\3CTS_DIS\4ENCRYPT_DIS\5DECRYPT_DIS\6RX_DIS"
 296           "\7CORR_FCS\10CHAN_INFO\11EN_SCRAMSD\22FRAME_NV0\25RX_CLR_HI"
 297           "\26IGNORE_CS\27CHAN_IDLE\30PHEAR_ME"),
 298     DEFBASIC(AR_TSF_L32,        "TSF_L32"),
 299     DEFBASIC(AR_TSF_U32,        "TSF_U32"),
 300     DEFBASIC(AR_TST_ADDAC,      "TST_ADAC"),
 301     DEFBASIC(AR_DEF_ANTENNA,    "DEF_ANT"),
 302     DEFBASIC(AR_QOS_MASK,       "QOS_MASK"),
 303     DEFBASIC(AR_SEQ_MASK,       "SEQ_MASK"),
 304     DEFBASIC(AR_OBSERV_2,       "OBSERV2"),
 305     DEFBASIC(AR_OBSERV_1,       "OBSERV1"),
 306
 307     DEFBASIC(AR_LAST_TSTP,      "LAST_TST"),
 308     DEFBASIC(AR_NAV,            "NAV"),
 309     DEFBASIC(AR_RTS_OK,         "RTS_OK"),
 310     DEFBASIC(AR_RTS_FAIL,       "RTS_FAIL"),
 311     DEFBASIC(AR_ACK_FAIL,       "ACK_FAIL"),
 312     DEFBASIC(AR_FCS_FAIL,       "FCS_FAIL"),
 313     DEFBASIC(AR_BEACON_CNT,     "BEAC_CNT"),
 314
 315     DEFBASIC(AR_SLEEP1,         "SLEEP1"),
 316     DEFBASIC(AR_SLEEP2,         "SLEEP2"),
 317     DEFBASIC(AR_SLEEP3,         "SLEEP3"),
 318     DEFBASIC(AR_BSSMSKL,        "BSSMSKL"),
 319     DEFBASIC(AR_BSSMSKU,        "BSSMSKU"),
 320     DEFBASIC(AR_TPC,            "TPC"),
 321     DEFBASIC(AR_TFCNT,          "TFCNT"),
 322     DEFBASIC(AR_RFCNT,          "RFCNT"),
 323     DEFBASIC(AR_RCCNT,          "RCCNT"),
 324     DEFBASIC(AR_CCCNT,          "CCCNT"),
 325     DEFBASIC(AR_QUIET1,         "QUIET1"),
 326     DEFBASIC(AR_QUIET2,         "QUIET2"),
 327     DEFBASIC(AR_TSF_PARM,       "TSF_PARM"),
 328     DEFBASIC(AR_NOACK,          "NOACK"),
 329     DEFBASIC(AR_PHY_ERR,        "PHY_ERR"),
 330     DEFBASIC(AR_QOS_CONTROL,    "QOS_CTRL"),
 331     DEFBASIC(AR_QOS_SELECT,     "QOS_SEL"),
 332     DEFBASIC(AR_MISC_MODE,      "MISCMODE"),
 333     DEFBASIC(AR_FILTOFDM,       "FILTOFDM"),
 334     DEFBASIC(AR_FILTCCK,        "FILTCCK"),
 335     DEFBASIC(AR_PHYCNT1,        "PHYCNT1"),
 336     DEFBASIC(AR_PHYCNTMASK1,    "PHYCMSK1"),
 337     DEFBASIC(AR_PHYCNT2,        "PHYCNT2"),
 338     DEFBASIC(AR_PHYCNTMASK2,    "PHYCMSK2"),
 339
 340     DEFVOID(AR_PHYCNT1,         "PHYCNT1"),
 341     DEFVOID(AR_PHYCNTMASK1,     "PHYCNTMASK1"),
 342     DEFVOID(AR_PHYCNT2,         "PHYCNT2"),
 343     DEFVOID(AR_PHYCNTMASK2,     "PHYCNTMASK2"),
 344
 345     DEFVOID(AR_PHY_TEST,        "PHY_TEST"),
 346     DEFVOID(AR_PHY_TURBO,       "PHY_TURBO"),
 347     DEFVOID(AR_PHY_TESTCTRL,    "PHY_TESTCTRL"),
 348     DEFVOID(AR_PHY_TIMING3,     "PHY_TIMING3"),
 349     DEFVOID(AR_PHY_CHIP_ID,     "PHY_CHIP_ID"),
 350     DEFVOIDfmt(AR_PHY_ACTIVE,   "PHY_ACTIVE",   "\20\1ENA"),
 351     DEFVOID(AR_PHY_TX_CTL,      "PHY_TX_CTL"),
 352     DEFVOID(AR_PHY_ADC_CTL,     "PHY_ADC_CTL"),
 353     DEFVOID(AR_PHY_BB_XP_PA_CTL,"PHY_BB_XP_PA_CTL"),
 354     DEFVOID(AR_PHY_TSTDAC_CONST,"PHY_TSTDAC_CONST"),
 355     DEFVOID(AR_PHY_SETTLING,    "PHY_SETTLING"),
 356     DEFVOID(AR_PHY_RXGAIN,      "PHY_RXGAIN"),
 357     DEFVOID(AR_PHY_DESIRED_SZ,  "PHY_DESIRED_SZ"),
 358     DEFVOID(AR_PHY_FIND_SIG,    "PHY_FIND_SIG"),
 359     DEFVOID(AR_PHY_AGC_CTL1,    "PHY_AGC_CTL1"),
 360     DEFVOIDfmt(AR_PHY_AGC_CONTROL,      "PHY_AGC_CONTROL",
 361       "\20\1CAL\2NF\16ENA_NF\22NO_UPDATE_NF"),
 362     DEFVOIDfmt(AR_PHY_SFCORR_LOW,       "PHY_SFCORR_LOW",
 363       "\20\1USE_SELF_CORR_LOW"),
 364     DEFVOID(AR_PHY_SFCORR,      "PHY_SFCORR"),
 365     DEFVOID(AR_PHY_SLEEP_CTR_CONTROL, "PHY_SLEEP_CTR_CONTROL"),
 366     DEFVOID(AR_PHY_SLEEP_CTR_LIMIT, "PHY_SLEEP_CTR_LIMIT"),
 367     DEFVOID(AR_PHY_SLEEP_SCAL,  "PHY_SLEEP_SCAL"),
 368     DEFVOID(AR_PHY_BIN_MASK_1,  "PHY_BIN_MASK_1"),
 369     DEFVOID(AR_PHY_BIN_MASK_2,  "PHY_BIN_MASK_2"),
 370     DEFVOID(AR_PHY_BIN_MASK_3,  "PHY_BIN_MASK_3"),
 371     DEFVOID(AR_PHY_MASK_CTL,    "PHY_MASK_CTL"),
 372     DEFVOID(AR_PHY_PLL_CTL,     "PHY_PLL_CTL"),
 373     DEFVOID(AR_PHY_RX_DELAY,    "PHY_RX_DELAY"),
 374     DEFVOID(AR_PHY_TIMING_CTRL4,"PHY_TIMING_CTRL4"),
 375     DEFVOID(AR_PHY_TIMING5,     "PHY_TIMING5"),
 376     DEFVOID(AR_PHY_PAPD_PROBE,  "PHY_PAPD_PROBE"),
 377     DEFVOID(AR_PHY_POWER_TX_RATE1,"PHY_POWER_TX_RATE1"),
 378     DEFVOID(AR_PHY_POWER_TX_RATE2,"PHY_POWER_TX_RATE2"),
 379     DEFVOID(AR_PHY_POWER_TX_RATE_MAX, "PHY_POWER_TX_RATE_MAX"),
 380     DEFVOID(AR_PHY_FRAME_CTL,   "PHY_FRAME_CTL"),
 381     DEFVOID(AR_PHY_TXPWRADJ,    "PHY_TXPWRADJ"),
 382     DEFVOID(AR_PHY_RADAR_0,     "PHY_RADAR_0"),
 383     DEFVOID(AR_PHY_SIGMA_DELTA, "PHY_SIGMA_DELTA"),
 384     DEFVOID(AR_PHY_RESTART,     "PHY_RESTART"),
 385     DEFVOID(AR_PHY_RFBUS_REQ,   "PHY_RFBUS_REQ"),
 386     DEFVOID(AR_PHY_TIMING7,     "PHY_TIMING7"),
 387     DEFVOID(AR_PHY_TIMING8,     "PHY_TIMING8"),
 388     DEFVOID(AR_PHY_BIN_MASK2_1, "PHY_BIN_MASK2_1"),
 389     DEFVOID(AR_PHY_BIN_MASK2_2, "PHY_BIN_MASK2_2"),
 390     DEFVOID(AR_PHY_BIN_MASK2_3, "PHY_BIN_MASK2_3"),
 391     DEFVOID(AR_PHY_BIN_MASK2_4, "PHY_BIN_MASK2_4"),
 392     DEFVOID(AR_PHY_TIMING9,     "PHY_TIMING9"),
 393     DEFVOID(AR_PHY_TIMING10,    "PHY_TIMING10"),
 394     DEFVOID(AR_PHY_TIMING11,    "PHY_TIMING11"),
 395     DEFVOID(AR_PHY_HEAVY_CLIP_ENABLE, "PHY_HEAVY_CLIP_ENABLE"),
 396     DEFVOID(AR_PHY_M_SLEEP,     "PHY_M_SLEEP"),
 397     DEFVOID(AR_PHY_REFCLKDLY,   "PHY_REFCLKDLY"),
 398     DEFVOID(AR_PHY_REFCLKPD,    "PHY_REFCLKPD"),
 399     DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_I, "PHY_IQCAL_RES_PWR_MEAS_I"),
 400     DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_Q, "PHY_IQCAL_RES_PWR_MEAS_Q"),
 401     DEFVOID(AR_PHY_IQCAL_RES_IQ_CORR_MEAS, "PHY_IQCAL_RES_IQ_CORR_MEAS"),
 402     DEFVOID(AR_PHY_CURRENT_RSSI,"PHY_CURRENT_RSSI"),
 403     DEFVOID(AR_PHY_RFBUS_GNT,   "PHY_RFBUS_GNT"),
 404     DEFVOIDfmt(AR_PHY_MODE,     "PHY_MODE",
 405         "\20\1CCK\2RF2GHZ\3DYNAMIC\4AR5112\5HALF\6QUARTER"),
 406     DEFVOID(AR_PHY_CCK_TX_CTRL, "PHY_CCK_TX_CTRL"),
 407     DEFVOID(AR_PHY_CCK_DETECT,  "PHY_CCK_DETECT"),
 408     DEFVOID(AR_PHY_GAIN_2GHZ,   "PHY_GAIN_2GHZ"),
 409     DEFVOID(AR_PHY_CCK_RXCTRL4, "PHY_CCK_RXCTRL4"),
 410     DEFVOID(AR_PHY_DAG_CTRLCCK, "PHY_DAG_CTRLCCK"),
 411     DEFVOID(AR_PHY_DAG_CTRLCCK, "PHY_DAG_CTRLCCK"),
 412     DEFVOID(AR_PHY_POWER_TX_RATE3,"PHY_POWER_TX_RATE3"),
 413     DEFVOID(AR_PHY_POWER_TX_RATE4,"PHY_POWER_TX_RATE4"),
 414     DEFVOID(AR_PHY_FAST_ADC,    "PHY_FAST_ADC"),
 415     DEFVOID(AR_PHY_BLUETOOTH,   "PHY_BLUETOOTH"),
 416     DEFVOID(AR_PHY_TPCRG1,      "PHY_TPCRG1"),
 417     DEFVOID(AR_PHY_TPCRG5,      "PHY_TPCRG5"),
 418
 419     /* XXX { AR_RATE_DURATION(0), AR_RATE_DURATION(0x20) }, */
 420 };
 421
 422 static __constructor void
 423 ar5212_ctor(void)
 424 {
 425         register_regs(ar5212regs, nitems(ar5212regs), MAC5212, PHYANY);
 426         register_keycache(128, MAC5212, PHYANY);
 427
 428         register_range(0x9800, 0x987c, DUMP_BASEBAND, MAC5212, PHYANY);
 429         register_range(0x9900, 0x995c, DUMP_BASEBAND, MAC5212, PHYANY);
 430         register_range(0x9c00, 0x9c1c, DUMP_BASEBAND, MAC5212, PHYANY);
 431         register_range(0xa180, 0xa238, DUMP_BASEBAND, MAC5212, PHYANY);
 432         register_range(0xa258, 0xa26c, DUMP_BASEBAND,
 433             SREV(7,8), SREV(15,15), PHYANY);
 434 }