2 * Copyright (c) 2002-2005 Bruce M. Simpson.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bruce M. Simpson.
16 * 4. Neither the name of Bruce M. Simpson nor the names of
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY BRUCE M. SIMPSON AND AFFILIATES
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
36 * All fields and quantities in this file are in little-endian byte order,
37 * unless otherwise specified.
43 #define PIR_BASE 0xF0000
44 #define PIR_SIZE 0x10000
47 #define PIR_DEV(x) (((x) & 0xF8) >> 3)
48 #define PIR_FUNC(x) ((x) & 0x7)
51 u_int8_t bus; /* bus number of this device */
52 u_int8_t devfunc; /* only upper 5 device bits valid */
53 u_int8_t inta_link; /* how INTA is linked */
54 u_int8_t inta_irqs[2]; /* how INTA may be routed (bitset) */
56 u_int8_t intb_irqs[2];
58 u_int8_t intc_irqs[2];
60 u_int8_t intd_irqs[2]; /* how this pin may be routed */
61 u_int8_t slot; /* physical slot number on bus,
62 * slot 0 if motherboard */
63 u_int8_t reserved00; /* must be zero */
64 } pir_entry_t __packed;
67 u_int32_t signature; /* $PIR */
68 u_int8_t minor; /* minor version (0) */
69 u_int8_t major; /* major version (1) */
70 u_int16_t size; /* total size of tab;e */
71 u_int8_t bus; /* Bus number of router */
72 u_int8_t devfunc; /* Dev/Func of router */
73 u_int16_t excl_irqs; /* PCI Exclusive IRQs */
74 u_int32_t compatible; /* Device/Vendor ID of a register
75 * compatible PCI IRQ router device */
76 u_int32_t miniport_data; /* Windows specific */
77 u_int8_t reserved00[11]; /* Must be zero */
78 u_int8_t checksum; /* Inverse mod-256 sum of table bytes */
79 pir_entry_t entry[1]; /* 1..N device entries */
80 } pir_table_t __packed;
82 #endif /* _PIRTABLE_H */