2 * Copyright(c) 2002-2011 Exar Corp.
5 * Redistribution and use in source and binary forms, with or without
6 * modification are permitted provided the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Exar Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
41 #include <sys/types.h>
42 #include <sys/socket.h>
43 #include <sys/ioctl.h>
45 #include <netinet/in.h>
46 #include <arpa/inet.h>
49 #if BYTE_ORDER == BIG_ENDIAN
50 #define VXGE_OS_HOST_BIG_ENDIAN
52 #define VXGE_OS_HOST_LITTLE_ENDIAN
55 #if defined(VXGE_OS_HOST_BIG_ENDIAN)
57 #define GET_OFFSET_STATS(index) statsInfo[(index)].be_offset
58 #define GET_OFFSET_PCICONF(index) pciconfInfo[(index)].be_offset
62 #define GET_OFFSET_STATS(index) statsInfo[(index)].le_offset
63 #define GET_OFFSET_PCICONF(index) pciconfInfo[(index)].le_offset
67 #define vxge_mem_free(x) \
68 if (NULL != x) { free(x); x = NULL; }
73 typedef unsigned long long u64;
74 typedef u_long ulong_t;
76 typedef enum _vxge_query_device_info_e {
78 VXGE_GET_PCI_CONF = 100,
79 VXGE_GET_MRPCIM_STATS = 101,
80 VXGE_GET_DEVICE_STATS = 102,
81 VXGE_GET_DEVICE_HWINFO = 103,
82 VXGE_GET_DRIVER_STATS = 104,
83 VXGE_GET_INTR_STATS = 105,
84 VXGE_GET_VERSION = 106,
86 VXGE_GET_VPATH_COUNT = 108,
87 VXGE_GET_BANDWIDTH = 109,
88 VXGE_SET_BANDWIDTH = 110,
89 VXGE_GET_PORT_MODE = 111,
90 VXGE_SET_PORT_MODE = 112
92 } vxge_query_device_info_e;
94 /* Register type enumaration */
95 typedef enum vxge_hal_mgmt_reg_type_e {
97 vxge_hal_mgmt_reg_type_legacy = 0,
98 vxge_hal_mgmt_reg_type_toc = 1,
99 vxge_hal_mgmt_reg_type_common = 2,
100 vxge_hal_mgmt_reg_type_memrepair = 3,
101 vxge_hal_mgmt_reg_type_pcicfgmgmt = 4,
102 vxge_hal_mgmt_reg_type_mrpcim = 5,
103 vxge_hal_mgmt_reg_type_srpcim = 6,
104 vxge_hal_mgmt_reg_type_vpmgmt = 7,
105 vxge_hal_mgmt_reg_type_vpath = 8
107 } vxge_hal_mgmt_reg_type_e;
109 typedef enum vxge_hal_xmac_nwif_dp_mode {
111 VXGE_HAL_DP_NP_MODE_DEFAULT,
112 VXGE_HAL_DP_NP_MODE_LINK_AGGR,
113 VXGE_HAL_DP_NP_MODE_ACTIVE_PASSIVE,
114 VXGE_HAL_DP_NP_MODE_SINGLE_PORT,
115 VXGE_HAL_DP_NP_MODE_DUAL_PORT,
116 VXGE_HAL_DP_NP_MODE_DISABLE_PORT_MGMT
118 } vxge_hal_xmac_nwif_dp_mode;
120 typedef enum vxge_hal_xmac_nwif_behavior_on_failure {
122 VXGE_HAL_XMAC_NWIF_OnFailure_NoMove,
123 VXGE_HAL_XMAC_NWIF_OnFailure_OtherPort,
124 VXGE_HAL_XMAC_NWIF_OnFailure_OtherPortBackOnRestore
126 } vxge_hal_xmac_nwif_behavior_on_failure;
128 #define VXGE_HAL_MGMT_REG_COUNT_LEGACY 7
129 #define VXGE_HAL_MGMT_REG_COUNT_TOC 11
130 #define VXGE_HAL_MGMT_REG_COUNT_COMMON 65
131 #define VXGE_HAL_MGMT_REG_COUNT_PCICFGMGMT 3
132 #define VXGE_HAL_MGMT_REG_COUNT_MRPCIM 1370
133 #define VXGE_HAL_MGMT_REG_COUNT_SRPCIM 48
134 #define VXGE_HAL_MGMT_REG_COUNT_VPMGMT 29
135 #define VXGE_HAL_MGMT_REG_COUNT_VPATH 139
136 #define VXGE_HAL_MGMT_STATS_COUNT_DRIVER 17
137 #define VXGE_HAL_MGMT_STATS_COUNT 160
138 #define VXGE_HAL_MGMT_STATS_COUNT_SW 54
139 #define VXGE_HAL_MGMT_STATS_COUNT_EXTENDED 56
140 #define VXGE_MAX_BANDWIDTH 10000
142 #define VXGE_HAL_MAX_VIRTUAL_PATHS 17
143 #define ETH_LENGTH_OF_ADDRESS 6
145 typedef char macaddr[ETH_LENGTH_OF_ADDRESS];
147 #define VXGE_PRINT(fd, fmt...) { \
154 /* Read & Write Register */
155 typedef struct _vxge_register_info_t {
161 } vxge_register_info_t;
164 typedef struct _vxge_pci_bar0_t {
171 typedef struct _vxge_stats_driver_info_t {
176 } vxge_stats_driver_info_t;
178 typedef struct _vxge_hal_device_pmd_info_t {
186 } vxge_hal_device_pmd_info_t;
188 typedef struct _vxge_hal_device_version_t {
195 } vxge_hal_device_version_t;
197 typedef struct _vxge_hal_device_date_t {
204 } vxge_hal_device_date_t;
206 typedef struct _vxge_hal_device_hw_info_t {
213 vxge_hal_device_version_t fw_version;
214 vxge_hal_device_date_t fw_date;
215 vxge_hal_device_version_t flash_version;
216 vxge_hal_device_date_t flash_date;
218 char serial_number[24];
219 char part_number[24];
220 char product_description[72];
224 vxge_hal_device_pmd_info_t pmd_port0;
225 vxge_hal_device_pmd_info_t pmd_port1;
227 macaddr mac_addrs[VXGE_HAL_MAX_VIRTUAL_PATHS];
228 macaddr mac_addr_masks[VXGE_HAL_MAX_VIRTUAL_PATHS];
230 } vxge_hal_device_hw_info_t;
232 typedef struct _vxge_device_hw_info_t {
234 vxge_hal_device_hw_info_t hw_info;
238 } vxge_device_hw_info_t;
240 typedef struct _vxge_bw_info_t {
249 typedef struct _vxge_port_info_t {
257 u32 vxge_get_num_vpath(void);
258 void vxge_null_terminate(char *, size_t);
260 #endif /* _VXGE_CMN_H_ */