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4 .TH "LLI" "1" "2020-06-26" "10" "LLVM"
6 lli \- directly execute programs from LLVM bitcode
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36 \fBlli\fP [\fIoptions\fP] [\fIfilename\fP] [\fIprogram args\fP]
39 \fBlli\fP directly executes programs in LLVM bitcode format. It takes a program
40 in LLVM bitcode format and executes it using a just\-in\-time compiler or an
43 \fBlli\fP is \fInot\fP an emulator. It will not execute IR of different architectures
44 and it can only interpret (or JIT\-compile) for the host architecture.
46 The JIT compiler takes the same arguments as other tools, like \fBllc\fP,
47 but they don\(aqt necessarily work for the interpreter.
49 If \fIfilename\fP is not specified, then \fBlli\fP reads the LLVM bitcode for the
50 program from standard input.
52 The optional \fIargs\fP specified on the command line are passed to the program as
57 .B \-fake\-argv0=executable
58 Override the \fBargv[0]\fP value passed into the executing program.
62 .B \-force\-interpreter={false,true}
63 If set to true, use the interpreter even if a just\-in\-time compiler is available
64 for this architecture. Defaults to false.
69 Print a summary of command line options.
73 .B \-load=pluginfilename
74 Causes \fBlli\fP to load the plugin (shared object) named \fIpluginfilename\fP and use
80 Print statistics from the code\-generation passes. This is only meaningful for
81 the just\-in\-time compiler, at present.
86 Record the amount of time needed for each code\-generation pass and print it to
92 Print out the version of \fBlli\fP and exit without doing anything else.
97 .B \-mtriple=target triple
98 Override the target triple specified in the input bitcode file with the
99 specified string. This may result in a crash if you pick an
100 architecture which is not compatible with the current system.
105 Specify the architecture for which to generate assembly, overriding the target
106 encoded in the bitcode file. See the output of \fBllc \-help\fP for a list of
107 valid architectures. By default this is inferred from the target triple or
108 autodetected to the current architecture.
113 Specify a specific chip in the current architecture to generate code for.
114 By default this is inferred from the target triple and autodetected to
115 the current architecture. For a list of available CPUs, use:
116 \fBllvm\-as < /dev/null | llc \-march=xyz \-mcpu=help\fP
120 .B \-mattr=a1,+a2,\-a3,...
121 Override or control specific attributes of the target, such as whether SIMD
122 operations are enabled or not. The default set of attributes is set by the
123 current CPU. For a list of available attributes, use:
124 \fBllvm\-as < /dev/null | llc \-march=xyz \-mattr=help\fP
126 .SH FLOATING POINT OPTIONS
129 .B \-disable\-excess\-fp\-precision
130 Disable optimizations that may increase floating point precision.
134 .B \-enable\-no\-infs\-fp\-math
135 Enable optimizations that assume no Inf values.
139 .B \-enable\-no\-nans\-fp\-math
140 Enable optimizations that assume no NAN values.
144 .B \-enable\-unsafe\-fp\-math
145 Causes \fBlli\fP to enable optimizations that may decrease floating point
151 Causes \fBlli\fP to generate software floating point library calls instead of
152 equivalent hardware instructions.
154 .SH CODE GENERATION OPTIONS
157 .B \-code\-model=model
158 Choose the code model from:
164 default: Target default code model
165 tiny: Tiny code model
166 small: Small code model
167 kernel: Kernel code model
168 medium: Medium code model
169 large: Large code model
177 .B \-disable\-post\-RA\-scheduler
178 Disable scheduling after register allocation.
182 .B \-disable\-spill\-fusing
183 Disable fusing of spill code into instructions.
188 Exception handling should be enabled in the just\-in\-time compiler.
192 .B \-join\-liveintervals
193 Coalesce copies (default=true).
197 .B \-nozero\-initialized\-in\-bss
198 Don\(aqt place zero\-initialized symbols into the BSS section.
202 .B \-pre\-RA\-sched=scheduler
203 Instruction schedulers available (before register allocation):
209 =default: Best scheduler for the target
210 =none: No scheduling: breadth first sequencing
211 =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization
212 =simple\-noitin: Simple two pass scheduling: Same as simple except using generic latency
213 =list\-burr: Bottom\-up register reduction list scheduling
214 =list\-tdrr: Top\-down register reduction list scheduling
215 =list\-td: Top\-down list scheduler \-print\-machineinstrs \- Print generated machine code
223 .B \-regalloc=allocator
224 Register allocator to use (default=linearscan)
230 =bigblock: Big\-block register allocator
231 =linearscan: linear scan register allocator =local \- local register allocator
232 =simple: simple register allocator
240 .B \-relocation\-model=model
241 Choose relocation model from:
247 =default: Target default relocation model
248 =static: Non\-relocatable code =pic \- Fully relocatable, position independent code
249 =dynamic\-no\-pic: Relocatable external references, non\-relocatable code
258 Spiller to use (default=local)
264 =simple: simple spiller
265 =local: local spiller
273 .B \-x86\-asm\-syntax=syntax
274 Choose style of code to emit from X86 backend:
280 =att: Emit AT&T\-style assembly
281 =intel: Emit Intel\-style assembly
289 If \fBlli\fP fails to load the program, it will exit with an exit code of 1.
290 Otherwise, it will return the exit code of the program it executes.
295 Maintained by the LLVM Team (https://llvm.org/).
297 2003-2020, LLVM Project
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