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4 .TH "LLVM-MCA" "1" "2020-06-26" "10" "LLVM"
6 llvm-mca \- LLVM Machine Code Analyzer
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36 \fBllvm\-mca\fP [\fIoptions\fP] [input]
39 \fBllvm\-mca\fP is a performance analysis tool that uses information
40 available in LLVM (e.g. scheduling models) to statically measure the performance
41 of machine code in a specific CPU.
43 Performance is measured in terms of throughput as well as processor resource
44 consumption. The tool currently works for processors with an out\-of\-order
45 backend, for which there is a scheduling model available in LLVM.
47 The main goal of this tool is not just to predict the performance of the code
48 when run on the target, but also help with diagnosing potential performance
51 Given an assembly code sequence, \fBllvm\-mca\fP estimates the Instructions
52 Per Cycle (IPC), as well as hardware resource pressure. The analysis and
53 reporting style were inspired by the IACA tool from Intel.
55 For example, you can compile code with clang, output assembly, and pipe it
56 directly into \fBllvm\-mca\fP for analysis:
62 $ clang foo.c \-O2 \-target x86_64\-unknown\-unknown \-S \-o \- | llvm\-mca \-mcpu=btver2
74 $ clang foo.c \-O2 \-target x86_64\-unknown\-unknown \-mllvm \-x86\-asm\-syntax=intel \-S \-o \- | llvm\-mca \-mcpu=btver2
80 Scheduling models are not just used to compute instruction latencies and
81 throughput, but also to understand what processor resources are available
82 and how to simulate them.
84 By design, the quality of the analysis conducted by \fBllvm\-mca\fP is
85 inevitably affected by the quality of the scheduling models in LLVM.
87 If you see that the performance report is not accurate for a processor,
88 please \fI\%file a bug\fP
89 against the appropriate backend.
92 If \fBinput\fP is "\fB\-\fP" or omitted, \fBllvm\-mca\fP reads from standard
93 input. Otherwise, it will read from the specified filename.
95 If the \fI\%\-o\fP option is omitted, then \fBllvm\-mca\fP will send its output
96 to standard output if the input is from standard input. If the \fI\%\-o\fP
97 option specifies "\fB\-\fP", then the output will also be sent to standard output.
101 Print a summary of command line options.
106 Use \fB<filename>\fP as the output filename. See the summary above for more
111 .B \-mtriple=<target triple>
112 Specify a target triple string.
117 Specify the architecture for which to analyze the code. It defaults to the
123 Specify the processor for which to analyze the code. By default, the cpu name
124 is autodetected from the host.
128 .B \-output\-asm\-variant=<variant id>
129 Specify the output assembly variant for the report generated by the tool.
130 On x86, possible values are [0, 1]. A value of 0 (vic. 1) for this flag enables
131 the AT&T (vic. Intel) assembly format for the code printed out by the tool in
137 Prefer hex format for numeric literals in the output assembly printed as part
142 .B \-dispatch=<width>
143 Specify a different dispatch width for the processor. The dispatch width
144 defaults to field \(aqIssueWidth\(aq in the processor scheduling model. If width is
145 zero, then the default dispatch width is used.
149 .B \-register\-file\-size=<size>
150 Specify the size of the register file. When specified, this flag limits how
151 many physical registers are available for register renaming purposes. A value
152 of zero for this flag means "unlimited number of physical registers".
156 .B \-iterations=<number of iterations>
157 Specify the number of iterations to run. If this flag is set to 0, then the
158 tool sets the number of iterations to a default value (i.e. 100).
163 If set, the tool assumes that loads and stores don\(aqt alias. This is the
168 .B \-lqueue=<load queue size>
169 Specify the size of the load queue in the load/store unit emulated by the tool.
170 By default, the tool assumes an unbound number of entries in the load queue.
171 A value of zero for this flag is ignored, and the default load queue size is
176 .B \-squeue=<store queue size>
177 Specify the size of the store queue in the load/store unit emulated by the
178 tool. By default, the tool assumes an unbound number of entries in the store
179 queue. A value of zero for this flag is ignored, and the default store queue
180 size is used instead.
185 Enable the timeline view.
189 .B \-timeline\-max\-iterations=<iterations>
190 Limit the number of iterations to print in the timeline view. By default, the
191 timeline view prints information for up to 10 iterations.
195 .B \-timeline\-max\-cycles=<cycles>
196 Limit the number of cycles in the timeline view. By default, the number of
201 .B \-resource\-pressure
202 Enable the resource pressure view. This is enabled by default.
206 .B \-register\-file\-stats
207 Enable register file usage statistics.
212 Enable extra dispatch statistics. This view collects and analyzes instruction
213 dispatch events, as well as static/dynamic dispatch stall events. This view
214 is disabled by default.
218 .B \-scheduler\-stats
219 Enable extra scheduler statistics. This view collects and analyzes instruction
220 issue events. This view is disabled by default.
225 Enable extra retire control unit statistics. This view is disabled by default.
229 .B \-instruction\-info
230 Enable the instruction info view. This is enabled by default.
235 Enable the printing of instruction encodings within the instruction info view.
240 Print all hardware statistics. This enables extra statistics related to the
241 dispatch logic, the hardware schedulers, the register file(s), and the retire
242 control unit. This option is disabled by default.
251 .B \-instruction\-tables
252 Prints resource pressure information based on the static information
253 available from the processor model. This differs from the resource pressure
254 view because it doesn\(aqt require that the code is simulated. It instead prints
255 the theoretical uniform distribution of resource pressure for every
256 instruction in sequence.
260 .B \-bottleneck\-analysis
261 Print information about bottlenecks that affect the throughput. This analysis
262 can be expensive, and it is disabled by default. Bottlenecks are highlighted
267 \fBllvm\-mca\fP returns 0 on success. Otherwise, an error message is printed
268 to standard error, and the tool returns 1.
269 .SH USING MARKERS TO ANALYZE SPECIFIC CODE BLOCKS
271 \fBllvm\-mca\fP allows for the optional usage of special code comments to
272 mark regions of the assembly code to be analyzed. A comment starting with
273 substring \fBLLVM\-MCA\-BEGIN\fP marks the beginning of a code region. A comment
274 starting with substring \fBLLVM\-MCA\-END\fP marks the end of a code region. For
289 If no user\-defined region is specified, then \fBllvm\-mca\fP assumes a
290 default region which contains every instruction in the input file. Every region
291 is analyzed in isolation, and the final performance report is the union of all
292 the reports generated for every code region.
294 Code regions can have names. For example:
300 # LLVM\-MCA\-BEGIN A simple example
308 The code from the example above defines a region named "A simple example" with a
309 single instruction in it. Note how the region name doesn\(aqt have to be repeated
310 in the \fBLLVM\-MCA\-END\fP directive. In the absence of overlapping regions,
311 an anonymous \fBLLVM\-MCA\-END\fP directive always ends the currently active user
314 Example of nesting regions:
320 # LLVM\-MCA\-BEGIN foo
322 # LLVM\-MCA\-BEGIN bar
331 Example of overlapping regions:
337 # LLVM\-MCA\-BEGIN foo
339 # LLVM\-MCA\-BEGIN bar
349 Note that multiple anonymous regions cannot overlap. Also, overlapping regions
350 cannot have the same name.
352 There is no support for marking regions from high\-level source code, like C or
353 C++. As a workaround, inline assembly directives may be used:
359 int foo(int a, int b) {
360 __asm volatile("# LLVM\-MCA\-BEGIN foo");
362 __asm volatile("# LLVM\-MCA\-END");
371 However, this interferes with optimizations like loop vectorization and may have
372 an impact on the code generated. This is because the \fB__asm\fP statements are
373 seen as real code having important side effects, which limits how the code
374 around them can be transformed. If users want to make use of inline assembly
375 to emit markers, then the recommendation is to always verify that the output
376 assembly is equivalent to the assembly generated in the absence of markers.
377 The \fI\%Clang options to emit optimization reports\fP
378 can also help in detecting missed optimizations.
379 .SH HOW LLVM-MCA WORKS
381 \fBllvm\-mca\fP takes assembly code as input. The assembly code is parsed
382 into a sequence of MCInst with the help of the existing LLVM target assembly
383 parsers. The parsed sequence of MCInst is then analyzed by a \fBPipeline\fP module
384 to generate a performance report.
386 The Pipeline module simulates the execution of the machine code sequence in a
387 loop of iterations (default is 100). During this process, the pipeline collects
388 a number of execution related statistics. At the end of this process, the
389 pipeline generates and prints a report from the collected statistics.
391 Here is an example of a performance report generated by the tool for a
392 dot\-product of two packed float vectors of four elements. The analysis is
393 conducted for target x86, cpu btver2. The following result can be produced via
394 the following command using the example located at
395 \fBtest/tools/llvm\-mca/X86/BtVer2/dot\-product.s\fP:
401 $ llvm\-mca \-mtriple=x86_64\-unknown\-unknown \-mcpu=btver2 \-iterations=300 dot\-product.s
419 Block RThroughput: 2.0
428 [6]: HasSideEffects (U)
430 [1] [2] [3] [4] [5] [6] Instructions:
431 1 2 1.00 vmulps %xmm0, %xmm1, %xmm2
432 1 3 1.00 vhaddps %xmm2, %xmm2, %xmm3
433 1 3 1.00 vhaddps %xmm3, %xmm3, %xmm4
453 Resource pressure per iteration:
454 [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
455 \- \- \- 2.00 1.00 2.00 1.00 \- \- \- \- \- \- \-
457 Resource pressure by instruction:
458 [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
459 \- \- \- \- 1.00 \- 1.00 \- \- \- \- \- \- \- vmulps %xmm0, %xmm1, %xmm2
460 \- \- \- 1.00 \- 1.00 \- \- \- \- \- \- \- \- vhaddps %xmm2, %xmm2, %xmm3
461 \- \- \- 1.00 \- 1.00 \- \- \- \- \- \- \- \- vhaddps %xmm3, %xmm3, %xmm4
467 According to this report, the dot\-product kernel has been executed 300 times,
468 for a total of 900 simulated instructions. The total number of simulated micro
469 opcodes (uOps) is also 900.
471 The report is structured in three main sections. The first section collects a
472 few performance numbers; the goal of this section is to give a very quick
473 overview of the performance throughput. Important performance indicators are
474 \fBIPC\fP, \fBuOps Per Cycle\fP, and \fBBlock RThroughput\fP (Block Reciprocal
477 Field \fIDispatchWidth\fP is the maximum number of micro opcodes that are dispatched
478 to the out\-of\-order backend every simulated cycle.
480 IPC is computed dividing the total number of simulated instructions by the total
483 Field \fIBlock RThroughput\fP is the reciprocal of the block throughput. Block
484 throuhgput is a theoretical quantity computed as the maximum number of blocks
485 (i.e. iterations) that can be executed per simulated clock cycle in the absence
486 of loop carried dependencies. Block throughput is is superiorly
487 limited by the dispatch rate, and the availability of hardware resources.
489 In the absence of loop\-carried data dependencies, the observed IPC tends to a
490 theoretical maximum which can be computed by dividing the number of instructions
491 of a single iteration by the \fIBlock RThroughput\fP\&.
493 Field \(aquOps Per Cycle\(aq is computed dividing the total number of simulated micro
494 opcodes by the total number of cycles. A delta between Dispatch Width and this
495 field is an indicator of a performance issue. In the absence of loop\-carried
496 data dependencies, the observed \(aquOps Per Cycle\(aq should tend to a theoretical
497 maximum throughput which can be computed by dividing the number of uOps of a
498 single iteration by the \fIBlock RThroughput\fP\&.
500 Field \fIuOps Per Cycle\fP is bounded from above by the dispatch width. That is
501 because the dispatch width limits the maximum size of a dispatch group. Both IPC
502 and \(aquOps Per Cycle\(aq are limited by the amount of hardware parallelism. The
503 availability of hardware resources affects the resource pressure distribution,
504 and it limits the number of instructions that can be executed in parallel every
505 cycle. A delta between Dispatch Width and the theoretical maximum uOps per
506 Cycle (computed by dividing the number of uOps of a single iteration by the
507 \fIBlock RThroughput\fP) is an indicator of a performance bottleneck caused by the
508 lack of hardware resources.
509 In general, the lower the Block RThroughput, the better.
511 In this example, \fBuOps per iteration/Block RThroughput\fP is 1.50. Since there
512 are no loop\-carried dependencies, the observed \fIuOps Per Cycle\fP is expected to
513 approach 1.50 when the number of iterations tends to infinity. The delta between
514 the Dispatch Width (2.00), and the theoretical maximum uOp throughput (1.50) is
515 an indicator of a performance bottleneck caused by the lack of hardware
516 resources, and the \fIResource pressure view\fP can help to identify the problematic
519 The second section of the report is the \fIinstruction info view\fP\&. It shows the
520 latency and reciprocal throughput of every instruction in the sequence. It also
521 reports extra information related to the number of micro opcodes, and opcode
522 properties (i.e., \(aqMayLoad\(aq, \(aqMayStore\(aq, and \(aqHasSideEffects\(aq).
524 Field \fIRThroughput\fP is the reciprocal of the instruction throughput. Throughput
525 is computed as the maximum number of instructions of a same type that can be
526 executed per clock cycle in the absence of operand dependencies. In this
527 example, the reciprocal throughput of a vector float multiply is 1
528 cycles/instruction. That is because the FP multiplier JFPM is only available
531 Instruction encodings are displayed within the instruction info view when flag
532 \fI\-show\-encoding\fP is specified.
534 Below is an example of \fI\-show\-encoding\fP output for the dot\-product kernel:
546 [6]: HasSideEffects (U)
549 [1] [2] [3] [4] [5] [6] [7] Encodings: Instructions:
550 1 2 1.00 4 c5 f0 59 d0 vmulps %xmm0, %xmm1, %xmm2
551 1 4 1.00 4 c5 eb 7c da vhaddps %xmm2, %xmm2, %xmm3
552 1 4 1.00 4 c5 e3 7c e3 vhaddps %xmm3, %xmm3, %xmm4
558 The \fIEncoding Size\fP column shows the size in bytes of instructions. The
559 \fIEncodings\fP column shows the actual instruction encodings (byte sequences in
562 The third section is the \fIResource pressure view\fP\&. This view reports
563 the average number of resource cycles consumed every iteration by instructions
564 for every processor resource unit available on the target. Information is
565 structured in two tables. The first table reports the number of resource cycles
566 spent on average every iteration. The second table correlates the resource
567 cycles to the machine instruction in the sequence. For example, every iteration
568 of the instruction vmulps always executes on resource unit [6]
569 (JFPU1 \- floating point pipeline #1), consuming an average of 1 resource cycle
570 per iteration. Note that on AMD Jaguar, vector floating\-point multiply can
571 only be issued to pipeline JFPU1, while horizontal floating\-point additions can
572 only be issued to pipeline JFPU0.
574 The resource pressure view helps with identifying bottlenecks caused by high
575 usage of specific hardware resources. Situations with resource pressure mainly
576 concentrated on a few resources should, in general, be avoided. Ideally,
577 pressure should be uniformly distributed between multiple resources.
580 The timeline view produces a detailed report of each instruction\(aqs state
581 transitions through an instruction pipeline. This view is enabled by the
582 command line option \fB\-timeline\fP\&. As instructions transition through the
583 various stages of the pipeline, their states are depicted in the view report.
584 These states are represented by the following characters:
587 D : Instruction dispatched.
589 e : Instruction executing.
591 E : Instruction executed.
593 R : Instruction retired.
595 = : Instruction already dispatched, waiting to be executed.
597 \- : Instruction executed, waiting to be retired.
600 Below is the timeline view for a subset of the dot\-product example located in
601 \fBtest/tools/llvm\-mca/X86/BtVer2/dot\-product.s\fP and processed by
602 \fBllvm\-mca\fP using the following command:
608 $ llvm\-mca \-mtriple=x86_64\-unknown\-unknown \-mcpu=btver2 \-iterations=3 \-timeline dot\-product.s
622 [0,0] DeeER. . . vmulps %xmm0, %xmm1, %xmm2
623 [0,1] D==eeeER . . vhaddps %xmm2, %xmm2, %xmm3
624 [0,2] .D====eeeER . vhaddps %xmm3, %xmm3, %xmm4
625 [1,0] .DeeE\-\-\-\-\-R . vmulps %xmm0, %xmm1, %xmm2
626 [1,1] . D=eeeE\-\-\-R . vhaddps %xmm2, %xmm2, %xmm3
627 [1,2] . D====eeeER . vhaddps %xmm3, %xmm3, %xmm4
628 [2,0] . DeeE\-\-\-\-\-R . vmulps %xmm0, %xmm1, %xmm2
629 [2,1] . D====eeeER . vhaddps %xmm2, %xmm2, %xmm3
630 [2,2] . D======eeeER vhaddps %xmm3, %xmm3, %xmm4
633 Average Wait times (based on the timeline view):
635 [1]: Average time spent waiting in a scheduler\(aqs queue
636 [2]: Average time spent waiting in a scheduler\(aqs queue while ready
637 [3]: Average time elapsed from WB until retire stage
640 0. 3 1.0 1.0 3.3 vmulps %xmm0, %xmm1, %xmm2
641 1. 3 3.3 0.7 1.0 vhaddps %xmm2, %xmm2, %xmm3
642 2. 3 5.7 0.0 0.0 vhaddps %xmm3, %xmm3, %xmm4
643 3 3.3 0.5 1.4 <total>
649 The timeline view is interesting because it shows instruction state changes
650 during execution. It also gives an idea of how the tool processes instructions
651 executed on the target, and how their timing information might be calculated.
653 The timeline view is structured in two tables. The first table shows
654 instructions changing state over time (measured in cycles); the second table
655 (named \fIAverage Wait times\fP) reports useful timing statistics, which should
656 help diagnose performance bottlenecks caused by long data dependencies and
657 sub\-optimal usage of hardware resources.
659 An instruction in the timeline view is identified by a pair of indices, where
660 the first index identifies an iteration, and the second index is the
661 instruction index (i.e., where it appears in the code sequence). Since this
662 example was generated using 3 iterations: \fB\-iterations=3\fP, the iteration
663 indices range from 0\-2 inclusively.
665 Excluding the first and last column, the remaining columns are in cycles.
666 Cycles are numbered sequentially starting from 0.
668 From the example output above, we know the following:
671 Instruction [1,0] was dispatched at cycle 1.
673 Instruction [1,0] started executing at cycle 2.
675 Instruction [1,0] reached the write back stage at cycle 4.
677 Instruction [1,0] was retired at cycle 10.
680 Instruction [1,0] (i.e., vmulps from iteration #1) does not have to wait in the
681 scheduler\(aqs queue for the operands to become available. By the time vmulps is
682 dispatched, operands are already available, and pipeline JFPU1 is ready to
683 serve another instruction. So the instruction can be immediately issued on the
684 JFPU1 pipeline. That is demonstrated by the fact that the instruction only
685 spent 1cy in the scheduler\(aqs queue.
687 There is a gap of 5 cycles between the write\-back stage and the retire event.
688 That is because instructions must retire in program order, so [1,0] has to wait
689 for [0,2] to be retired first (i.e., it has to wait until cycle 10).
691 In the example, all instructions are in a RAW (Read After Write) dependency
692 chain. Register %xmm2 written by vmulps is immediately used by the first
693 vhaddps, and register %xmm3 written by the first vhaddps is used by the second
694 vhaddps. Long data dependencies negatively impact the ILP (Instruction Level
697 In the dot\-product example, there are anti\-dependencies introduced by
698 instructions from different iterations. However, those dependencies can be
699 removed at register renaming stage (at the cost of allocating register aliases,
700 and therefore consuming physical registers).
702 Table \fIAverage Wait times\fP helps diagnose performance issues that are caused by
703 the presence of long latency instructions and potentially long data dependencies
704 which may limit the ILP. Last row, \fB<total>\fP, shows a global average over all
705 instructions measured. Note that \fBllvm\-mca\fP, by default, assumes at
706 least 1cy between the dispatch event and the issue event.
708 When the performance is limited by data dependencies and/or long latency
709 instructions, the number of cycles spent while in the \fIready\fP state is expected
710 to be very small when compared with the total number of cycles spent in the
711 scheduler\(aqs queue. The difference between the two counters is a good indicator
712 of how large of an impact data dependencies had on the execution of the
713 instructions. When performance is mostly limited by the lack of hardware
714 resources, the delta between the two counters is small. However, the number of
715 cycles spent in the queue tends to be larger (i.e., more than 1\-3cy),
716 especially when compared to other low latency instructions.
717 .SS Bottleneck Analysis
719 The \fB\-bottleneck\-analysis\fP command line option enables the analysis of
720 performance bottlenecks.
722 This analysis is potentially expensive. It attempts to correlate increases in
723 backend pressure (caused by pipeline resource pressure and data dependencies) to
724 dynamic dispatch stalls.
726 Below is an example of \fB\-bottleneck\-analysis\fP output generated by
727 \fBllvm\-mca\fP for 500 iterations of the dot\-product example on btver2.
733 Cycles with backend pressure increase [ 48.07% ]
734 Throughput Bottlenecks:
735 Resource Pressure [ 47.77% ]
738 Data Dependencies: [ 0.30% ]
739 \- Register Dependencies [ 0.30% ]
740 \- Memory Dependencies [ 0.00% ]
742 Critical sequence based on the simulation:
744 Instruction Dependency Information
745 +\-\-\-\-< 2. vhaddps %xmm3, %xmm3, %xmm4
749 | 0. vmulps %xmm0, %xmm1, %xmm2
750 +\-\-\-\-> 1. vhaddps %xmm2, %xmm2, %xmm3 ## RESOURCE interference: JFPA [ probability: 74% ]
751 +\-\-\-\-> 2. vhaddps %xmm3, %xmm3, %xmm4 ## REGISTER dependency: %xmm3
755 +\-\-\-\-> 1. vhaddps %xmm2, %xmm2, %xmm3 ## RESOURCE interference: JFPA [ probability: 74% ]
761 According to the analysis, throughput is limited by resource pressure and not by
762 data dependencies. The analysis observed increases in backend pressure during
763 48.07% of the simulated run. Almost all those pressure increase events were
764 caused by contention on processor resources JFPA/JFPU0.
766 The \fIcritical sequence\fP is the most expensive sequence of instructions according
767 to the simulation. It is annotated to provide extra information about critical
768 register dependencies and resource interferences between instructions.
770 Instructions from the critical sequence are expected to significantly impact
771 performance. By construction, the accuracy of this analysis is strongly
772 dependent on the simulation and (as always) by the quality of the processor
774 .SS Extra Statistics to Further Diagnose Performance Issues
776 The \fB\-all\-stats\fP command line option enables extra statistics and performance
777 counters for the dispatch logic, the reorder buffer, the retire control unit,
778 and the register file.
780 Below is an example of \fB\-all\-stats\fP output generated by \fBllvm\-mca\fP
781 for 300 iterations of the dot\-product example discussed in the previous
788 Dynamic Dispatch Stall Cycles:
789 RAT \- Register unavailable: 0
790 RCU \- Retire tokens unavailable: 0
791 SCHEDQ \- Scheduler full: 272 (44.6%)
792 LQ \- Load queue full: 0
793 SQ \- Store queue full: 0
794 GROUP \- Static restrictions on the dispatch group: 0
797 Dispatch Logic \- number of cycles where we saw N micro opcodes dispatched:
798 [# dispatched], [# cycles]
804 Schedulers \- number of cycles where we saw N micro opcodes issued:
805 [# issued], [# cycles]
810 Scheduler\(aqs queue usage:
812 [2] Average number of used buffer entries.
813 [3] Maximum number of used buffer entries.
814 [4] Total number of buffer entries.
822 Retire Control Unit \- number of cycles where we saw N instructions retired:
823 [# retired], [# cycles]
828 Total ROB Entries: 64
829 Max Used ROB Entries: 35 ( 54.7% )
830 Average Used ROB Entries per cy: 32 ( 50.0% )
833 Register File statistics:
834 Total number of mappings created: 900
835 Max number of mappings used: 35
837 * Register File #1 \-\- JFpuPRF:
838 Number of physical registers: 72
839 Total number of mappings created: 900
840 Max number of mappings used: 35
842 * Register File #2 \-\- JIntegerPRF:
843 Number of physical registers: 64
844 Total number of mappings created: 0
845 Max number of mappings used: 0
851 If we look at the \fIDynamic Dispatch Stall Cycles\fP table, we see the counter for
852 SCHEDQ reports 272 cycles. This counter is incremented every time the dispatch
853 logic is unable to dispatch a full group because the scheduler\(aqs queue is full.
855 Looking at the \fIDispatch Logic\fP table, we see that the pipeline was only able to
856 dispatch two micro opcodes 51.5% of the time. The dispatch group was limited to
857 one micro opcode 44.6% of the cycles, which corresponds to 272 cycles. The
858 dispatch statistics are displayed by either using the command option
859 \fB\-all\-stats\fP or \fB\-dispatch\-stats\fP\&.
861 The next table, \fISchedulers\fP, presents a histogram displaying a count,
862 representing the number of micro opcodes issued on some number of cycles. In
863 this case, of the 610 simulated cycles, single opcodes were issued 306 times
864 (50.2%) and there were 7 cycles where no opcodes were issued.
866 The \fIScheduler\(aqs queue usage\fP table shows that the average and maximum number of
867 buffer entries (i.e., scheduler queue entries) used at runtime. Resource JFPU01
868 reached its maximum (18 of 18 queue entries). Note that AMD Jaguar implements
872 JALU01 \- A scheduler for ALU instructions.
874 JFPU01 \- A scheduler floating point operations.
876 JLSAGU \- A scheduler for address generation.
879 The dot\-product is a kernel of three floating point instructions (a vector
880 multiply followed by two horizontal adds). That explains why only the floating
881 point scheduler appears to be used.
883 A full scheduler queue is either caused by data dependency chains or by a
884 sub\-optimal usage of hardware resources. Sometimes, resource pressure can be
885 mitigated by rewriting the kernel using different instructions that consume
886 different scheduler resources. Schedulers with a small queue are less resilient
887 to bottlenecks caused by the presence of long data dependencies. The scheduler
888 statistics are displayed by using the command option \fB\-all\-stats\fP or
889 \fB\-scheduler\-stats\fP\&.
891 The next table, \fIRetire Control Unit\fP, presents a histogram displaying a count,
892 representing the number of instructions retired on some number of cycles. In
893 this case, of the 610 simulated cycles, two instructions were retired during the
894 same cycle 399 times (65.4%) and there were 109 cycles where no instructions
895 were retired. The retire statistics are displayed by using the command option
896 \fB\-all\-stats\fP or \fB\-retire\-stats\fP\&.
898 The last table presented is \fIRegister File statistics\fP\&. Each physical register
899 file (PRF) used by the pipeline is presented in this table. In the case of AMD
900 Jaguar, there are two register files, one for floating\-point registers (JFpuPRF)
901 and one for integer registers (JIntegerPRF). The table shows that of the 900
902 instructions processed, there were 900 mappings created. Since this dot\-product
903 example utilized only floating point registers, the JFPuPRF was responsible for
904 creating the 900 mappings. However, we see that the pipeline only used a
905 maximum of 35 of 72 available register slots at any given time. We can conclude
906 that the floating point PRF was the only register file used for the example, and
907 that it was never resource constrained. The register file statistics are
908 displayed by using the command option \fB\-all\-stats\fP or
909 \fB\-register\-file\-stats\fP\&.
911 In this example, we can conclude that the IPC is mostly limited by data
912 dependencies, and not by resource pressure.
915 This section describes the instruction flow through the default pipeline of
916 \fBllvm\-mca\fP, as well as the functional units involved in the process.
918 The default pipeline implements the following sequence of stages used to
919 process instructions.
922 Dispatch (Instruction is dispatched to the schedulers).
924 Issue (Instruction is issued to the processor pipelines).
926 Write Back (Instruction is executed, and results are written back).
928 Retire (Instruction is retired; writes are architecturally committed).
931 The default pipeline only models the out\-of\-order portion of a processor.
932 Therefore, the instruction fetch and decode stages are not modeled. Performance
933 bottlenecks in the frontend are not diagnosed. \fBllvm\-mca\fP assumes that
934 instructions have all been decoded and placed into a queue before the simulation
935 start. Also, \fBllvm\-mca\fP does not model branch prediction.
936 .SS Instruction Dispatch
938 During the dispatch stage, instructions are picked in program order from a
939 queue of already decoded instructions, and dispatched in groups to the
940 simulated hardware schedulers.
942 The size of a dispatch group depends on the availability of the simulated
943 hardware resources. The processor dispatch width defaults to the value
944 of the \fBIssueWidth\fP in LLVM\(aqs scheduling model.
946 An instruction can be dispatched if:
949 The size of the dispatch group is smaller than processor\(aqs dispatch width.
951 There are enough entries in the reorder buffer.
953 There are enough physical registers to do register renaming.
955 The schedulers are not full.
958 Scheduling models can optionally specify which register files are available on
959 the processor. \fBllvm\-mca\fP uses that information to initialize register
960 file descriptors. Users can limit the number of physical registers that are
961 globally available for register renaming by using the command option
962 \fB\-register\-file\-size\fP\&. A value of zero for this option means \fIunbounded\fP\&. By
963 knowing how many registers are available for renaming, the tool can predict
964 dispatch stalls caused by the lack of physical registers.
966 The number of reorder buffer entries consumed by an instruction depends on the
967 number of micro\-opcodes specified for that instruction by the target scheduling
968 model. The reorder buffer is responsible for tracking the progress of
969 instructions that are "in\-flight", and retiring them in program order. The
970 number of entries in the reorder buffer defaults to the value specified by field
971 \fIMicroOpBufferSize\fP in the target scheduling model.
973 Instructions that are dispatched to the schedulers consume scheduler buffer
974 entries. \fBllvm\-mca\fP queries the scheduling model to determine the set
975 of buffered resources consumed by an instruction. Buffered resources are
976 treated like scheduler resources.
977 .SS Instruction Issue
979 Each processor scheduler implements a buffer of instructions. An instruction
980 has to wait in the scheduler\(aqs buffer until input register operands become
981 available. Only at that point, does the instruction becomes eligible for
982 execution and may be issued (potentially out\-of\-order) for execution.
983 Instruction latencies are computed by \fBllvm\-mca\fP with the help of the
986 \fBllvm\-mca\fP\(aqs scheduler is designed to simulate multiple processor
987 schedulers. The scheduler is responsible for tracking data dependencies, and
988 dynamically selecting which processor resources are consumed by instructions.
989 It delegates the management of processor resource units and resource groups to a
990 resource manager. The resource manager is responsible for selecting resource
991 units that are consumed by instructions. For example, if an instruction
992 consumes 1cy of a resource group, the resource manager selects one of the
993 available units from the group; by default, the resource manager uses a
994 round\-robin selector to guarantee that resource usage is uniformly distributed
995 between all units of a group.
997 \fBllvm\-mca\fP\(aqs scheduler internally groups instructions into three sets:
1000 WaitSet: a set of instructions whose operands are not ready.
1002 ReadySet: a set of instructions ready to execute.
1004 IssuedSet: a set of instructions executing.
1007 Depending on the operands availability, instructions that are dispatched to the
1008 scheduler are either placed into the WaitSet or into the ReadySet.
1010 Every cycle, the scheduler checks if instructions can be moved from the WaitSet
1011 to the ReadySet, and if instructions from the ReadySet can be issued to the
1012 underlying pipelines. The algorithm prioritizes older instructions over younger
1014 .SS Write\-Back and Retire Stage
1016 Issued instructions are moved from the ReadySet to the IssuedSet. There,
1017 instructions wait until they reach the write\-back stage. At that point, they
1018 get removed from the queue and the retire control unit is notified.
1020 When instructions are executed, the retire control unit flags the instruction as
1023 Instructions are retired in program order. The register file is notified of the
1024 retirement so that it can free the physical registers that were allocated for
1025 the instruction during the register renaming stage.
1026 .SS Load/Store Unit and Memory Consistency Model
1028 To simulate an out\-of\-order execution of memory operations, \fBllvm\-mca\fP
1029 utilizes a simulated load/store unit (LSUnit) to simulate the speculative
1030 execution of loads and stores.
1032 Each load (or store) consumes an entry in the load (or store) queue. Users can
1033 specify flags \fB\-lqueue\fP and \fB\-squeue\fP to limit the number of entries in the
1034 load and store queues respectively. The queues are unbounded by default.
1036 The LSUnit implements a relaxed consistency model for memory loads and stores.
1040 A younger load is allowed to pass an older load only if there are no
1041 intervening stores or barriers between the two loads.
1043 A younger load is allowed to pass an older store provided that the load does
1044 not alias with the store.
1046 A younger store is not allowed to pass an older store.
1048 A younger store is not allowed to pass an older load.
1051 By default, the LSUnit optimistically assumes that loads do not alias
1052 (\fI\-noalias=true\fP) store operations. Under this assumption, younger loads are
1053 always allowed to pass older stores. Essentially, the LSUnit does not attempt
1054 to run any alias analysis to predict when loads and stores do not alias with
1057 Note that, in the case of write\-combining memory, rule 3 could be relaxed to
1058 allow reordering of non\-aliasing store operations. That being said, at the
1059 moment, there is no way to further relax the memory model (\fB\-noalias\fP is the
1060 only option). Essentially, there is no option to specify a different memory
1061 type (e.g., write\-back, write\-combining, write\-through; etc.) and consequently
1062 to weaken, or strengthen, the memory model.
1064 Other limitations are:
1067 The LSUnit does not know when store\-to\-load forwarding may occur.
1069 The LSUnit does not know anything about cache hierarchy and memory types.
1071 The LSUnit does not know how to identify serializing operations and memory
1075 The LSUnit does not attempt to predict if a load or store hits or misses the L1
1076 cache. It only knows if an instruction "MayLoad" and/or "MayStore." For
1077 loads, the scheduling model provides an "optimistic" load\-to\-use latency (which
1078 usually matches the load\-to\-use latency for when there is a hit in the L1D).
1080 \fBllvm\-mca\fP does not know about serializing operations or memory\-barrier
1081 like instructions. The LSUnit conservatively assumes that an instruction which
1082 has both "MayLoad" and unmodeled side effects behaves like a "soft"
1083 load\-barrier. That means, it serializes loads without forcing a flush of the
1084 load queue. Similarly, instructions that "MayStore" and have unmodeled side
1085 effects are treated like store barriers. A full memory barrier is a "MayLoad"
1086 and "MayStore" instruction with unmodeled side effects. This is inaccurate, but
1087 it is the best that we can do at the moment with the current information
1090 A load/store barrier consumes one entry of the load/store queue. A load/store
1091 barrier enforces ordering of loads/stores. A younger load cannot pass a load
1092 barrier. Also, a younger store cannot pass a store barrier. A younger load
1093 has to wait for the memory/load barrier to execute. A load/store barrier is
1094 "executed" when it becomes the oldest entry in the load/store queue(s). That
1095 also means, by construction, all of the older loads/stores have been executed.
1097 In conclusion, the full set of load/store consistency rules are:
1100 A store may not pass a previous store.
1102 A store may not pass a previous load (regardless of \fB\-noalias\fP).
1104 A store has to wait until an older store barrier is fully executed.
1106 A load may pass a previous load.
1108 A load may not pass a previous store unless \fB\-noalias\fP is set.
1110 A load has to wait until an older load barrier is fully executed.
1113 Maintained by the LLVM Team (https://llvm.org/).
1115 2003-2020, LLVM Project
1116 .\" Generated by docutils manpage writer.
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