3 /* Print i386 instructions for GDB, the GNU debugger.
4 Copyright (C) 1988, 1989 Free Software Foundation, Inc.
6 This file is part of GDB.
8 GDB is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 1, or (at your option)
13 GDB is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GDB; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23 * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
28 * The main tables describing the instructions is essentially a copy
29 * of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 * Programmers Manual. Usually, there is a capital letter, followed
31 * by a small letter. The capital letter tell the addressing mode,
32 * and the small letter tells about the operand size. Refer to
33 * the Intel manual for details.
39 #define Eb OP_E, b_mode
40 #define indirEb OP_indirE, b_mode
41 #define Gb OP_G, b_mode
42 #define Ev OP_E, v_mode
43 #define indirEv OP_indirE, v_mode
44 #define Ew OP_E, w_mode
45 #define Ma OP_E, v_mode
47 #define Mp OP_E, 0 /* ? */
48 #define Gv OP_G, v_mode
49 #define Gw OP_G, w_mode
50 #define Rw OP_rm, w_mode
51 #define Rd OP_rm, d_mode
52 #define Ib OP_I, b_mode
53 #define sIb OP_sI, b_mode /* sign extened byte */
54 #define Iv OP_I, v_mode
55 #define Iw OP_I, w_mode
56 #define Jb OP_J, b_mode
57 #define Jv OP_J, v_mode
59 #define Cd OP_C, d_mode
60 #define Dd OP_D, d_mode
61 #define Td OP_T, d_mode
63 #define eAX OP_REG, eAX_reg
64 #define eBX OP_REG, eBX_reg
65 #define eCX OP_REG, eCX_reg
66 #define eDX OP_REG, eDX_reg
67 #define eSP OP_REG, eSP_reg
68 #define eBP OP_REG, eBP_reg
69 #define eSI OP_REG, eSI_reg
70 #define eDI OP_REG, eDI_reg
71 #define AL OP_REG, al_reg
72 #define CL OP_REG, cl_reg
73 #define DL OP_REG, dl_reg
74 #define BL OP_REG, bl_reg
75 #define AH OP_REG, ah_reg
76 #define CH OP_REG, ch_reg
77 #define DH OP_REG, dh_reg
78 #define BH OP_REG, bh_reg
79 #define AX OP_REG, ax_reg
80 #define DX OP_REG, dx_reg
81 #define indirDX OP_REG, indir_dx_reg
83 #define Sw OP_SEG, w_mode
84 #define Ap OP_DIR, lptr
85 #define Av OP_DIR, v_mode
86 #define Ob OP_OFF, b_mode
87 #define Ov OP_OFF, v_mode
88 #define Xb OP_DSSI, b_mode
89 #define Xv OP_DSSI, v_mode
90 #define Yb OP_ESDI, b_mode
91 #define Yv OP_ESDI, v_mode
93 #define es OP_REG, es_reg
94 #define ss OP_REG, ss_reg
95 #define cs OP_REG, cs_reg
96 #define ds OP_REG, ds_reg
97 #define fs OP_REG, fs_reg
98 #define gs OP_REG, gs_reg
100 int OP_E(), OP_indirE(), OP_G(), OP_I(), OP_sI(), OP_REG();
101 int OP_J(), OP_SEG();
102 int OP_DIR(), OP_OFF(), OP_DSSI(), OP_ESDI(), OP_ONE(), OP_C();
103 int OP_D(), OP_T(), OP_rm();
146 #define indir_dx_reg 150
148 #define GRP1b NULL, NULL, 0
149 #define GRP1S NULL, NULL, 1
150 #define GRP1Ss NULL, NULL, 2
151 #define GRP2b NULL, NULL, 3
152 #define GRP2S NULL, NULL, 4
153 #define GRP2b_one NULL, NULL, 5
154 #define GRP2S_one NULL, NULL, 6
155 #define GRP2b_cl NULL, NULL, 7
156 #define GRP2S_cl NULL, NULL, 8
157 #define GRP3b NULL, NULL, 9
158 #define GRP3S NULL, NULL, 10
159 #define GRP4 NULL, NULL, 11
160 #define GRP5 NULL, NULL, 12
161 #define GRP6 NULL, NULL, 13
162 #define GRP7 NULL, NULL, 14
163 #define GRP8 NULL, NULL, 15
166 #define FLOAT NULL, NULL, FLOATCODE
178 struct dis386 dis386[] = {
196 { "(bad)" }, /* 0x0f extended opcode escape */
222 { "(bad)" }, /* SEG ES prefix */
231 { "(bad)" }, /* SEG CS prefix */
240 { "(bad)" }, /* SEG SS prefix */
249 { "(bad)" }, /* SEG DS prefix */
290 { "boundS", Gv, Ma },
292 { "(bad)" }, /* seg fs */
293 { "(bad)" }, /* seg gs */
294 { "(bad)" }, /* op size prefix */
295 { "(bad)" }, /* adr size prefix */
297 { "pushS", Iv }, /* 386 book wrong */
298 { "imulS", Gv, Ev, Iv },
299 { "pushl", sIb }, /* push of byte really pushes 4 bytes */
300 { "imulS", Gv, Ev, Ib },
301 { "insb", Yb, indirDX },
302 { "insS", Yv, indirDX },
303 { "outsb", indirDX, Xb },
304 { "outsS", indirDX, Xv },
343 { "xchgS", eCX, eAX },
344 { "xchgS", eDX, eAX },
345 { "xchgS", eBX, eAX },
346 { "xchgS", eSP, eAX },
347 { "xchgS", eBP, eAX },
348 { "xchgS", eSI, eAX },
349 { "xchgS", eDI, eAX },
354 { "(bad)" }, /* fwait */
370 { "testS", eAX, Iv },
372 { "stosS", Yv, eAX },
374 { "lodsS", eAX, Xv },
376 { "scasS", eAX, Yv },
445 { "inb", AL, indirDX },
446 { "inS", eAX, indirDX },
447 { "outb", indirDX, AL },
448 { "outS", indirDX, eAX },
450 { "(bad)" }, /* lock prefix */
452 { "(bad)" }, /* repne */
453 { "(bad)" }, /* repz */
469 struct dis386 dis386_twobyte[] = {
480 { "invd" }, { "wbinvd" }, { "(bad)" }, { "(bad)" },
481 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
483 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
484 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
486 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
487 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
489 /* these are all backward in appendix A of the intel book */
499 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
500 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
502 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
503 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
505 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
506 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
508 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
509 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
511 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
512 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
514 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
515 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
517 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
518 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
520 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
521 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
523 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
524 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
526 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
527 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
529 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
530 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
572 { "shldS", Ev, Gv, Ib },
573 { "shldS", Ev, Gv, CL },
581 { "shrdS", Ev, Gv, Ib },
582 { "shrdS", Ev, Gv, CL },
588 { "lssS", Gv, Mp }, /* 386 lists only Mp */
590 { "lfsS", Gv, Mp }, /* 386 lists only Mp */
591 { "lgsS", Gv, Mp }, /* 386 lists only Mp */
592 { "movzbS", Gv, Eb },
593 { "movzwS", Gv, Ew },
601 { "movsbS", Gv, Eb },
602 { "movswS", Gv, Ew },
604 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
605 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
607 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
608 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
610 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
611 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
613 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
614 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
616 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
617 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
619 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
620 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
622 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
623 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
625 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
626 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
629 static char obuf[100];
631 static char scratchbuf[100];
632 static unsigned char *start_codep;
633 static unsigned char *codep;
638 static char *names32[]={
639 "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
641 static char *names16[] = {
642 "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
644 static char *names8[] = {
645 "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
647 static char *names_seg[] = {
648 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
650 static char *names16_pairs[] = {
651 "%bx+%si","%bx+%di","%bp+%si","%bp+%di","%si","%di","%bp","%bx",
654 struct dis386 grps[][8] = {
772 { "imulS", eAX, Ev },
774 { "idivS", eAX, Ev },
792 { "lcall", indirEv },
833 #define PREFIX_REPZ 0x01
834 #define PREFIX_REPNZ 0x02
835 #define PREFIX_LOCK 0x04
836 #define PREFIX_CS 0x08
837 #define PREFIX_SS 0x10
838 #define PREFIX_DS 0x20
839 #define PREFIX_ES 0x40
840 #define PREFIX_FS 0x80
841 #define PREFIX_GS 0x100
842 #define PREFIX_DATA 0x200
843 #define PREFIX_ADR 0x400
844 #define PREFIX_FWAIT 0x800
856 prefixes |= PREFIX_REPZ;
859 prefixes |= PREFIX_REPNZ;
862 prefixes |= PREFIX_LOCK;
865 prefixes |= PREFIX_CS;
868 prefixes |= PREFIX_SS;
871 prefixes |= PREFIX_DS;
874 prefixes |= PREFIX_ES;
877 prefixes |= PREFIX_FS;
880 prefixes |= PREFIX_GS;
883 prefixes |= PREFIX_DATA;
886 prefixes |= PREFIX_ADR;
889 prefixes |= PREFIX_FWAIT;
901 static char op1out[100], op2out[100], op3out[100];
902 static unsigned long start_pc;
905 * disassemble the first instruction in 'inbuf'. You have to make
906 * sure all of the bytes of the instruction are filled in.
907 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
908 * (see topic "Redundant prefixes" in the "Differences from 8086"
909 * section of the "Virtual 8086 Mode" chapter.)
910 * 'pc' should be the address of this instruction, it will
911 * be used to print the target address if this is a relative jump or call
912 * 'outbuf' gets filled in with the disassembled instruction. it should
913 * be long enough to hold the longest disassembled instruction.
914 * 100 bytes is certainly enough, unless symbol printing is added later
915 * The function returns the length of this instruction in bytes.
917 i386dis (ucs, uip, inbuf, outbuf, mode)
920 unsigned char *inbuf;
926 int enter_instruction;
927 char *first, *second, *third;
935 start_pc = ucs << 16 | uip;
942 enter_instruction = 1;
944 enter_instruction = 0;
948 if (prefixes & PREFIX_REPZ)
950 if (prefixes & PREFIX_REPNZ)
952 if (prefixes & PREFIX_LOCK)
955 if ((prefixes & PREFIX_FWAIT)
956 && ((*codep < 0xd8) || (*codep > 0xdf)))
958 /* fwait not followed by floating point instruction */
960 strcpy (outbuf, obuf);
964 /* these would be initialized to 0 if disassembling for 8086 or 286 */
965 /* these would be initialized to 0 if disassembling for 8086 or 286 */
974 if (prefixes & PREFIX_DATA)
977 if (prefixes & PREFIX_ADR)
984 dp = &dis386_twobyte[*++codep];
986 dp = &dis386[*codep];
988 mod = (*codep >> 6) & 3;
989 reg = (*codep >> 3) & 7;
992 if (dp->name == NULL && dp->bytemode1 == FLOATCODE)
998 if (dp->name == NULL)
999 dp = &grps[dp->bytemode1][reg];
1005 (*dp->op1)(dp->bytemode1);
1009 (*dp->op2)(dp->bytemode2);
1013 (*dp->op3)(dp->bytemode3);
1016 obufp = obuf + strlen (obuf);
1017 for (i = strlen (obuf); i < 6; i++)
1021 /* enter instruction is printed with operands in the
1022 * same order as the intel book; everything else
1023 * is printed in reverse order
1025 if (enter_instruction)
1056 strcpy (outbuf, obuf);
1057 return (codep - inbuf);
1060 char *float_mem[] = {
1136 #define STi OP_STi, 0
1137 int OP_ST(), OP_STi();
1139 #define FGRPd9_2 NULL, NULL, 0
1140 #define FGRPd9_4 NULL, NULL, 1
1141 #define FGRPd9_5 NULL, NULL, 2
1142 #define FGRPd9_6 NULL, NULL, 3
1143 #define FGRPd9_7 NULL, NULL, 4
1144 #define FGRPda_5 NULL, NULL, 5
1145 #define FGRPdb_4 NULL, NULL, 6
1146 #define FGRPde_3 NULL, NULL, 7
1147 #define FGRPdf_4 NULL, NULL, 8
1149 struct dis386 float_reg[][8] = {
1152 { "fadd", ST, STi },
1153 { "fmul", ST, STi },
1156 { "fsub", ST, STi },
1157 { "fsubr", ST, STi },
1158 { "fdiv", ST, STi },
1159 { "fdivr", ST, STi },
1196 { "fadd", STi, ST },
1197 { "fmul", STi, ST },
1200 { "fsub", STi, ST },
1201 { "fsubr", STi, ST },
1202 { "fdiv", STi, ST },
1203 { "fdivr", STi, ST },
1218 { "faddp", STi, ST },
1219 { "fmulp", STi, ST },
1222 { "fsubp", STi, ST },
1223 { "fsubrp", STi, ST },
1224 { "fdivp", STi, ST },
1225 { "fdivrp", STi, ST },
1241 char *fgrps[][8] = {
1244 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1249 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
1254 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
1259 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
1264 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
1269 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1274 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
1275 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
1280 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1285 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1293 unsigned char floatop;
1295 floatop = codep[-1];
1299 putop (float_mem[(floatop - 0xd8) * 8 + reg]);
1306 dp = &float_reg[floatop - 0xd8][reg];
1307 if (dp->name == NULL)
1309 putop (fgrps[dp->bytemode1][rm]);
1310 /* instruction fnstsw is only one with strange arg */
1311 if (floatop == 0xdf && *codep == 0xe0)
1312 strcpy (op1out, "%eax");
1319 (*dp->op1)(dp->bytemode1);
1322 (*dp->op2)(dp->bytemode2);
1335 sprintf (scratchbuf, "%%st(%d)", rm);
1336 oappend (scratchbuf);
1340 /* capital letters in template are macros */
1346 for (p = template; *p; p++)
1353 case 'C': /* For jcxz/jecxz */
1358 if ((prefixes & PREFIX_FWAIT) == 0)
1362 /* operand size flag */
1377 obufp += strlen (s);
1383 if (prefixes & PREFIX_CS)
1385 if (prefixes & PREFIX_DS)
1387 if (prefixes & PREFIX_SS)
1389 if (prefixes & PREFIX_ES)
1391 if (prefixes & PREFIX_FS)
1393 if (prefixes & PREFIX_GS)
1397 OP_indirE (bytemode)
1413 /* skip mod/rm byte */
1423 oappend (names8[rm]);
1426 oappend (names16[rm]);
1430 oappend (names32[rm]);
1432 oappend (names16[rm]);
1435 oappend ("<bad dis table>");
1443 if (aflag && rm == 4) {
1446 scale = (*codep >> 6) & 3;
1447 index = (*codep >> 3) & 7;
1457 /* implies havesib and havebase */
1482 disp = *(char *)codep++;
1483 if (!aflag || rm != 4) {
1493 if (!aflag || rm != 4) {
1500 if (mod != 0 || (aflag && rm == 5 || (havesib && base == 5))
1501 || (!aflag && rm == 6)) {
1502 sprintf (scratchbuf, "0x%x", disp);
1503 oappend (scratchbuf);
1506 if (havebase || havesib) {
1509 oappend (aflag ? names32[base] : names16_pairs[base]);
1512 sprintf (scratchbuf, ",%s", names32[index]);
1513 oappend (scratchbuf);
1515 sprintf (scratchbuf, ",%d", 1 << scale);
1516 oappend (scratchbuf);
1527 oappend (names8[reg]);
1530 oappend (names16[reg]);
1533 oappend (names32[reg]);
1537 oappend (names32[reg]);
1539 oappend (names16[reg]);
1542 oappend ("<internal disassembler error>");
1551 x = *codep++ & 0xff;
1552 x |= (*codep++ & 0xff) << 8;
1553 x |= (*codep++ & 0xff) << 16;
1554 x |= (*codep++ & 0xff) << 24;
1562 x = *codep++ & 0xff;
1563 x |= (*codep++ & 0xff) << 8;
1573 case indir_dx_reg: s = "(%dx)"; break;
1574 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
1575 case sp_reg: case bp_reg: case si_reg: case di_reg:
1576 s = names16[code - ax_reg];
1578 case es_reg: case ss_reg: case cs_reg:
1579 case ds_reg: case fs_reg: case gs_reg:
1580 s = names_seg[code - es_reg];
1582 case al_reg: case ah_reg: case cl_reg: case ch_reg:
1583 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
1584 s = names8[code - al_reg];
1586 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
1587 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
1589 s = names32[code - eAX_reg];
1591 s = names16[code - eAX_reg];
1594 s = "<internal disassembler error>";
1607 op = *codep++ & 0xff;
1619 oappend ("<internal disassembler error>");
1622 sprintf (scratchbuf, "$0x%x", op);
1623 oappend (scratchbuf);
1633 op = *(char *)codep++;
1639 op = (short)get16();
1642 op = (short)get16 ();
1645 oappend ("<internal disassembler error>");
1648 sprintf (scratchbuf, "$0x%x", op);
1649 oappend (scratchbuf);
1659 disp = *(char *)codep++;
1660 append_pc(start_pc + codep - start_codep + disp);
1665 append_pc(start_pc + codep - start_codep + disp);
1667 disp = (short)get16 ();
1668 disp = (((start_pc + codep - start_codep) & 0xffff) + disp) & 0xffff;
1669 append_pc((start_pc & 0xffff0000) | disp);
1673 oappend ("<internal disassembelr error>");
1677 oappend (scratchbuf);
1680 append_pc(unsigned long pc)
1682 sprintf(scratchbuf, "%04x:%04x", pc >> 16, pc & 0xffff);
1688 static char *sreg[] = {
1689 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
1692 oappend (sreg[reg]);
1712 sprintf (scratchbuf, "%04x:%04x", seg, offset);
1713 oappend (scratchbuf);
1719 offset = (short)get16 ();
1721 append_pc(start_pc + codep - start_codep + offset);
1722 oappend (scratchbuf);
1725 oappend ("<internal disassembler error>");
1740 sprintf (scratchbuf, "0x%x", off);
1741 oappend (scratchbuf);
1748 oappend (aflag ? "%edi" : "%di");
1756 oappend (aflag ? "%esi" : "%si");
1769 codep++; /* skip mod/rm */
1770 sprintf (scratchbuf, "%%cr%d", reg);
1771 oappend (scratchbuf);
1777 codep++; /* skip mod/rm */
1778 sprintf (scratchbuf, "%%db%d", reg);
1779 oappend (scratchbuf);
1785 codep++; /* skip mod/rm */
1786 sprintf (scratchbuf, "%%tr%d", reg);
1787 oappend (scratchbuf);
1795 oappend (names32[rm]);
1798 oappend (names16[rm]);
1805 i386dis (pc, inbuf, outbuf, mode)
1807 unsigned char *inbuf;
1810 strcpy (outbuf, "(no disassembler)");
1814 #endif /* DISASSEMBLER */