2 * Copyright (c) 2012 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/types.h>
34 #include <x86/apicreg.h>
35 #include <machine/vmm.h>
49 #define IOAPIC_PADDR 0xFEC00000
54 #define REDIR_ENTRIES 16
55 #define INTR_ASSERTED(ioapic, pin) ((ioapic)->pinstate[(pin)] == true)
60 uint64_t redtbl[REDIR_ENTRIES];
61 bool pinstate[REDIR_ENTRIES];
63 uintptr_t paddr; /* gpa where the ioapic is mapped */
65 struct memory_region *region;
68 static struct ioapic ioapics[1]; /* only a single ioapic for now */
70 static int ioapic_region_read(struct ioapic *ioapic, uintptr_t paddr,
71 int size, uint64_t *data);
72 static int ioapic_region_write(struct ioapic *ioapic, uintptr_t paddr,
73 int size, uint64_t data);
74 static int ioapic_region_handler(struct vmctx *vm, int vcpu, int dir,
75 uintptr_t paddr, int size, uint64_t *val,
76 void *arg1, long arg2);
79 ioapic_set_pinstate(struct vmctx *ctx, int pin, bool newstate)
81 int vector, apicid, vcpu;
83 struct ioapic *ioapic;
85 ioapic = &ioapics[0]; /* assume a single ioapic */
87 if (pin < 0 || pin >= REDIR_ENTRIES)
90 /* Nothing to do if interrupt pin has not changed state */
91 if (ioapic->pinstate[pin] == newstate)
94 ioapic->pinstate[pin] = newstate; /* record it */
96 /* Nothing to do if interrupt pin is deasserted */
97 if (!INTR_ASSERTED(ioapic, pin))
103 * - edge triggered interrupts
104 * - physical destination mode
105 * - fixed delivery mode
107 low = ioapic->redtbl[pin];
108 high = ioapic->redtbl[pin] >> 32;
109 if ((low & IOART_INTMASK) == IOART_INTMCLR &&
110 (low & IOART_TRGRMOD) == IOART_TRGREDG &&
111 (low & IOART_DESTMOD) == IOART_DESTPHY &&
112 (low & IOART_DELMOD) == IOART_DELFIXED) {
113 vector = low & IOART_INTVEC;
114 apicid = high >> APIC_ID_SHIFT;
115 if (apicid != 0xff) {
117 vcpu = vm_apicid2vcpu(ctx, apicid);
118 vm_lapic_irq(ctx, vcpu, vector);
122 while (vcpu < guest_ncpus) {
123 vm_lapic_irq(ctx, vcpu, vector);
131 ioapic_deassert_pin(struct vmctx *ctx, int pin)
133 ioapic_set_pinstate(ctx, pin, false);
137 ioapic_assert_pin(struct vmctx *ctx, int pin)
139 ioapic_set_pinstate(ctx, pin, true);
143 ioapic_init(int which)
145 struct mem_range memp;
146 struct ioapic *ioapic;
152 ioapic = &ioapics[which];
153 assert(ioapic->inited == 0);
155 bzero(ioapic, sizeof(struct ioapic));
157 /* Initialize all redirection entries to mask all interrupts */
158 for (i = 0; i < REDIR_ENTRIES; i++)
159 ioapic->redtbl[i] = 0x0001000000010000UL;
161 ioapic->paddr = IOAPIC_PADDR;
163 /* Register emulated memory region */
164 memp.name = "ioapic";
165 memp.flags = MEM_F_RW;
166 memp.handler = ioapic_region_handler;
169 memp.base = ioapic->paddr;
170 memp.size = sizeof(struct IOAPIC);
171 error = register_mem(&memp);
179 ioapic_read(struct ioapic *ioapic, uint32_t addr)
181 int regnum, pin, rshift;
183 assert(ioapic->inited);
185 regnum = addr & 0xff;
191 return ((REDIR_ENTRIES << MAXREDIRSHIFT) | 0x11);
200 /* redirection table entries */
201 if (regnum >= IOAPIC_REDTBL &&
202 regnum < IOAPIC_REDTBL + REDIR_ENTRIES * 2) {
203 pin = (regnum - IOAPIC_REDTBL) / 2;
204 if ((regnum - IOAPIC_REDTBL) % 2)
209 return (ioapic->redtbl[pin] >> rshift);
216 ioapic_write(struct ioapic *ioapic, uint32_t addr, uint32_t data)
218 int regnum, pin, lshift;
220 assert(ioapic->inited);
222 regnum = addr & 0xff;
225 ioapic->id = data & APIC_ID_MASK;
235 /* redirection table entries */
236 if (regnum >= IOAPIC_REDTBL &&
237 regnum < IOAPIC_REDTBL + REDIR_ENTRIES * 2) {
238 pin = (regnum - IOAPIC_REDTBL) / 2;
239 if ((regnum - IOAPIC_REDTBL) % 2)
244 ioapic->redtbl[pin] &= ~((uint64_t)0xffffffff << lshift);
245 ioapic->redtbl[pin] |= ((uint64_t)data << lshift);
250 ioapic_region_read(struct ioapic *ioapic, uintptr_t paddr, int size,
255 offset = paddr - ioapic->paddr;
258 * The IOAPIC specification allows 32-bit wide accesses to the
259 * IOREGSEL (offset 0) and IOWIN (offset 16) registers.
261 if (size != 4 || (offset != IOREGSEL && offset != IOWIN)) {
263 printf("invalid access to ioapic%d: size %d, offset %d\n",
264 (int)(ioapic - ioapics), size, offset);
270 if (offset == IOREGSEL)
271 *data = ioapic->ioregsel;
273 *data = ioapic_read(ioapic, ioapic->ioregsel);
279 ioapic_region_write(struct ioapic *ioapic, uintptr_t paddr, int size,
284 offset = paddr - ioapic->paddr;
287 * The ioapic specification allows 32-bit wide accesses to the
288 * IOREGSEL (offset 0) and IOWIN (offset 16) registers.
290 if (size != 4 || (offset != IOREGSEL && offset != IOWIN)) {
292 printf("invalid access to ioapic%d: size %d, offset %d\n",
293 (int)(ioapic - ioapics), size, offset);
298 if (offset == IOREGSEL)
299 ioapic->ioregsel = data;
301 ioapic_write(ioapic, ioapic->ioregsel, data);
307 ioapic_region_handler(struct vmctx *vm, int vcpu, int dir, uintptr_t paddr,
308 int size, uint64_t *val, void *arg1, long arg2)
310 struct ioapic *ioapic;
316 assert(ioapic == &ioapics[which]);
318 if (dir == MEM_F_READ)
319 ioapic_region_read(ioapic, paddr, size, val);
321 ioapic_region_write(ioapic, paddr, size, *val);