2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 NetApp, Inc.
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8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/types.h>
35 #include <sys/errno.h>
36 #include <x86/mptable.h>
46 #define MPTABLE_BASE 0xF0000
48 /* floating pointer length + maximum length of configuration table */
49 #define MPTABLE_MAX_LENGTH (65536 + 16)
51 #define LAPIC_PADDR 0xFEE00000
52 #define LAPIC_VERSION 16
54 #define IOAPIC_PADDR 0xFEC00000
55 #define IOAPIC_VERSION 0x11
58 #define MPFP_SIG "_MP_"
60 /* Configuration header defines */
61 #define MPCH_SIG "PCMP"
62 #define MPCH_OEMID "BHyVe "
63 #define MPCH_OEMID_LEN 8
64 #define MPCH_PRODID "Hypervisor "
65 #define MPCH_PRODID_LEN 12
67 /* Processor entry defines */
68 #define MPEP_SIG_FAMILY 6 /* XXX bhyve should supply this */
69 #define MPEP_SIG_MODEL 26
70 #define MPEP_SIG_STEPPING 5
72 ((MPEP_SIG_FAMILY << 8) | \
73 (MPEP_SIG_MODEL << 4) | \
76 #define MPEP_FEATURES (0xBFEBFBFF) /* XXX Intel i7 */
78 /* Number of local intr entries */
79 #define MPEII_NUM_LOCAL_IRQ 2
81 /* Bus entry defines */
82 #define MPE_NUM_BUSES 2
83 #define MPE_BUSNAME_LEN 6
84 #define MPE_BUSNAME_ISA "ISA "
85 #define MPE_BUSNAME_PCI "PCI "
87 static void *oem_tbl_start;
88 static int oem_tbl_size;
91 mpt_compute_checksum(void *base, size_t len)
96 for(bytes = base, sum = 0; len > 0; len--) {
104 mpt_build_mpfp(mpfps_t mpfp, vm_paddr_t gpa)
107 memset(mpfp, 0, sizeof(*mpfp));
108 memcpy(mpfp->signature, MPFP_SIG, 4);
109 mpfp->pap = gpa + sizeof(*mpfp);
111 mpfp->spec_rev = MP_SPECREV;
112 mpfp->checksum = mpt_compute_checksum(mpfp, sizeof(*mpfp));
116 mpt_build_mpch(mpcth_t mpch)
119 memset(mpch, 0, sizeof(*mpch));
120 memcpy(mpch->signature, MPCH_SIG, 4);
121 mpch->spec_rev = MP_SPECREV;
122 memcpy(mpch->oem_id, MPCH_OEMID, MPCH_OEMID_LEN);
123 memcpy(mpch->product_id, MPCH_PRODID, MPCH_PRODID_LEN);
124 mpch->apic_address = LAPIC_PADDR;
128 mpt_build_proc_entries(proc_entry_ptr mpep, int ncpu)
132 for (i = 0; i < ncpu; i++) {
133 memset(mpep, 0, sizeof(*mpep));
134 mpep->type = MPCT_ENTRY_PROCESSOR;
135 mpep->apic_id = i; // XXX
136 mpep->apic_version = LAPIC_VERSION;
137 mpep->cpu_flags = PROCENTRY_FLAG_EN;
139 mpep->cpu_flags |= PROCENTRY_FLAG_BP;
140 mpep->cpu_signature = MPEP_SIG;
141 mpep->feature_flags = MPEP_FEATURES;
147 mpt_build_localint_entries(int_entry_ptr mpie)
150 /* Hardcode LINT0 as ExtINT on all CPUs. */
151 memset(mpie, 0, sizeof(*mpie));
152 mpie->type = MPCT_ENTRY_LOCAL_INT;
153 mpie->int_type = INTENTRY_TYPE_EXTINT;
154 mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
155 INTENTRY_FLAGS_TRIGGER_CONFORM;
156 mpie->dst_apic_id = 0xff;
157 mpie->dst_apic_int = 0;
160 /* Hardcode LINT1 as NMI on all CPUs. */
161 memset(mpie, 0, sizeof(*mpie));
162 mpie->type = MPCT_ENTRY_LOCAL_INT;
163 mpie->int_type = INTENTRY_TYPE_NMI;
164 mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
165 INTENTRY_FLAGS_TRIGGER_CONFORM;
166 mpie->dst_apic_id = 0xff;
167 mpie->dst_apic_int = 1;
171 mpt_build_bus_entries(bus_entry_ptr mpeb)
174 memset(mpeb, 0, sizeof(*mpeb));
175 mpeb->type = MPCT_ENTRY_BUS;
177 memcpy(mpeb->bus_type, MPE_BUSNAME_PCI, MPE_BUSNAME_LEN);
180 memset(mpeb, 0, sizeof(*mpeb));
181 mpeb->type = MPCT_ENTRY_BUS;
183 memcpy(mpeb->bus_type, MPE_BUSNAME_ISA, MPE_BUSNAME_LEN);
187 mpt_build_ioapic_entries(io_apic_entry_ptr mpei, int id)
190 memset(mpei, 0, sizeof(*mpei));
191 mpei->type = MPCT_ENTRY_IOAPIC;
193 mpei->apic_version = IOAPIC_VERSION;
194 mpei->apic_flags = IOAPICENTRY_FLAG_EN;
195 mpei->apic_address = IOAPIC_PADDR;
199 mpt_count_ioint_entries(void)
204 for (bus = 0; bus <= PCI_BUSMAX; bus++)
205 count += pci_count_lintr(bus);
208 * Always include entries for the first 16 pins along with a entry
209 * for each active PCI INTx pin.
215 mpt_generate_pci_int(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
218 int_entry_ptr *mpiep, mpie;
222 memset(mpie, 0, sizeof(*mpie));
225 * This is always after another I/O interrupt entry, so cheat
226 * and fetch the I/O APIC ID from the prior entry.
228 mpie->type = MPCT_ENTRY_INT;
229 mpie->int_type = INTENTRY_TYPE_INT;
230 mpie->src_bus_id = bus;
231 mpie->src_bus_irq = slot << 2 | (pin - 1);
232 mpie->dst_apic_id = mpie[-1].dst_apic_id;
233 mpie->dst_apic_int = ioapic_irq;
239 mpt_build_ioint_entries(int_entry_ptr mpie, int id)
244 * The following config is taken from kernel mptable.c
245 * mptable_parse_default_config_ints(...), for now
246 * just use the default config, tweek later if needed.
249 /* First, generate the first 16 pins. */
250 for (pin = 0; pin < 16; pin++) {
251 memset(mpie, 0, sizeof(*mpie));
252 mpie->type = MPCT_ENTRY_INT;
253 mpie->src_bus_id = 1;
254 mpie->dst_apic_id = id;
257 * All default configs route IRQs from bus 0 to the first 16
258 * pins of the first I/O APIC with an APIC ID of 2.
260 mpie->dst_apic_int = pin;
263 /* Pin 0 is an ExtINT pin. */
264 mpie->int_type = INTENTRY_TYPE_EXTINT;
267 /* IRQ 0 is routed to pin 2. */
268 mpie->int_type = INTENTRY_TYPE_INT;
269 mpie->src_bus_irq = 0;
272 /* ACPI SCI is level triggered and active-lo. */
273 mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO |
274 INTENTRY_FLAGS_TRIGGER_LEVEL;
275 mpie->int_type = INTENTRY_TYPE_INT;
276 mpie->src_bus_irq = SCI_INT;
279 /* All other pins are identity mapped. */
280 mpie->int_type = INTENTRY_TYPE_INT;
281 mpie->src_bus_irq = pin;
287 /* Next, generate entries for any PCI INTx interrupts. */
288 for (bus = 0; bus <= PCI_BUSMAX; bus++)
289 pci_walk_lintr(bus, mpt_generate_pci_int, &mpie);
293 mptable_add_oemtbl(void *tbl, int tblsz)
297 oem_tbl_size = tblsz;
301 mptable_build(struct vmctx *ctx, int ncpu)
305 io_apic_entry_ptr mpei;
313 startaddr = paddr_guest2host(ctx, MPTABLE_BASE, MPTABLE_MAX_LENGTH);
314 if (startaddr == NULL) {
315 fprintf(stderr, "mptable requires mapped mem\n");
320 * There is no way to advertise multiple PCI hierarchies via MPtable
321 * so require that there is no PCI hierarchy with a non-zero bus
324 for (bus = 1; bus <= PCI_BUSMAX; bus++) {
325 if (pci_bus_configured(bus)) {
326 fprintf(stderr, "MPtable is incompatible with "
327 "multiple PCI hierarchies.\r\n");
328 fprintf(stderr, "MPtable generation can be disabled "
329 "by passing the -Y option to bhyve(8).\r\n");
334 curraddr = startaddr;
335 mpfp = (mpfps_t)curraddr;
336 mpt_build_mpfp(mpfp, MPTABLE_BASE);
337 curraddr += sizeof(*mpfp);
339 mpch = (mpcth_t)curraddr;
340 mpt_build_mpch(mpch);
341 curraddr += sizeof(*mpch);
343 mpep = (proc_entry_ptr)curraddr;
344 mpt_build_proc_entries(mpep, ncpu);
345 curraddr += sizeof(*mpep) * ncpu;
346 mpch->entry_count += ncpu;
348 mpeb = (bus_entry_ptr) curraddr;
349 mpt_build_bus_entries(mpeb);
350 curraddr += sizeof(*mpeb) * MPE_NUM_BUSES;
351 mpch->entry_count += MPE_NUM_BUSES;
353 mpei = (io_apic_entry_ptr)curraddr;
354 mpt_build_ioapic_entries(mpei, 0);
355 curraddr += sizeof(*mpei);
358 mpie = (int_entry_ptr) curraddr;
359 ioints = mpt_count_ioint_entries();
360 mpt_build_ioint_entries(mpie, 0);
361 curraddr += sizeof(*mpie) * ioints;
362 mpch->entry_count += ioints;
364 mpie = (int_entry_ptr)curraddr;
365 mpt_build_localint_entries(mpie);
366 curraddr += sizeof(*mpie) * MPEII_NUM_LOCAL_IRQ;
367 mpch->entry_count += MPEII_NUM_LOCAL_IRQ;
370 mpch->oem_table_pointer = curraddr - startaddr + MPTABLE_BASE;
371 mpch->oem_table_size = oem_tbl_size;
372 memcpy(curraddr, oem_tbl_start, oem_tbl_size);
375 mpch->base_table_length = curraddr - (char *)mpch;
376 mpch->checksum = mpt_compute_checksum(mpch, mpch->base_table_length);