2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
3 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/linker_set.h>
37 #include <sys/ioctl.h>
40 #include <sys/endian.h>
52 #include <pthread_np.h>
61 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
62 #define MAX_PORTS 32 /* AHCI supports 32 ports */
64 #define PxSIG_ATA 0x00000101 /* ATA drive */
65 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
68 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
69 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
70 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
71 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
72 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
73 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
74 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
75 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
81 #define TEST_UNIT_READY 0x00
82 #define REQUEST_SENSE 0x03
84 #define START_STOP_UNIT 0x1B
85 #define PREVENT_ALLOW 0x1E
86 #define READ_CAPACITY 0x25
88 #define POSITION_TO_ELEMENT 0x2B
90 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
91 #define MODE_SENSE_10 0x5A
92 #define REPORT_LUNS 0xA0
97 * SCSI mode page codes
99 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
100 #define MODEPAGE_CD_CAPABILITIES 0x2A
105 #define ATA_SF_ENAB_SATA_SF 0x10
106 #define ATA_SATA_SF_AN 0x05
107 #define ATA_SF_DIS_SATA_SF 0x90
114 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
116 #define DPRINTF(format, arg...)
118 #define WPRINTF(format, arg...) printf(format, ##arg)
121 struct blockif_req io_req;
122 struct ahci_port *io_pr;
123 STAILQ_ENTRY(ahci_ioreq) io_flist;
124 TAILQ_ENTRY(ahci_ioreq) io_blist;
133 struct blockif_ctxt *bctx;
134 struct pci_ahci_softc *pr_sc;
144 uint8_t err_cfis[20];
171 struct ahci_ioreq *ioreq;
173 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
174 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
177 struct ahci_cmd_hdr {
182 uint32_t reserved[4];
185 struct ahci_prdt_entry {
188 #define DBCMASK 0x3fffff
192 struct pci_ahci_softc {
193 struct pci_devinst *asc_pi;
208 struct ahci_port port[MAX_PORTS];
210 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
212 static void ahci_handle_port(struct ahci_port *p);
214 static inline void lba_to_msf(uint8_t *buf, int lba)
217 buf[0] = (lba / 75) / 60;
218 buf[1] = (lba / 75) % 60;
223 * Generate HBA interrupts on global IS register write.
226 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask)
228 struct pci_devinst *pi = sc->asc_pi;
233 /* Update global IS from PxIS/PxIE. */
234 for (i = 0; i < sc->ports; i++) {
239 DPRINTF("%s(%08x) %08x\n", __func__, mask, sc->is);
241 /* If there is nothing enabled -- clear legacy interrupt and exit. */
242 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) {
244 pci_lintr_deassert(pi);
250 /* If there is anything and no MSI -- assert legacy interrupt. */
251 nmsg = pci_msi_maxmsgnum(pi);
255 pci_lintr_assert(pi);
260 /* Assert respective MSIs for ports that were touched. */
261 for (i = 0; i < nmsg; i++) {
262 if (sc->ports <= nmsg || i < nmsg - 1)
265 mmask = 0xffffffff << i;
266 if (sc->is & mask && mmask & mask)
267 pci_generate_msi(pi, i);
272 * Generate HBA interrupt on specific port event.
275 ahci_port_intr(struct ahci_port *p)
277 struct pci_ahci_softc *sc = p->pr_sc;
278 struct pci_devinst *pi = sc->asc_pi;
281 DPRINTF("%s(%d) %08x/%08x %08x\n", __func__,
282 p->port, p->is, p->ie, sc->is);
284 /* If there is nothing enabled -- we are done. */
285 if ((p->is & p->ie) == 0)
288 /* In case of non-shared MSI always generate interrupt. */
289 nmsg = pci_msi_maxmsgnum(pi);
290 if (sc->ports <= nmsg || p->port < nmsg - 1) {
291 sc->is |= (1 << p->port);
292 if ((sc->ghc & AHCI_GHC_IE) == 0)
294 pci_generate_msi(pi, p->port);
298 /* If IS for this port is already set -- do nothing. */
299 if (sc->is & (1 << p->port))
302 sc->is |= (1 << p->port);
304 /* If interrupts are enabled -- generate one. */
305 if ((sc->ghc & AHCI_GHC_IE) == 0)
308 pci_generate_msi(pi, nmsg - 1);
309 } else if (!sc->lintr) {
311 pci_lintr_assert(pi);
316 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
318 int offset, len, irq;
320 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
324 case FIS_TYPE_REGD2H:
327 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0;
329 case FIS_TYPE_SETDEVBITS:
332 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0;
334 case FIS_TYPE_PIOSETUP:
337 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
340 WPRINTF("unsupported fis type %d\n", ft);
343 if (fis[2] & ATA_S_ERROR) {
345 irq |= AHCI_P_IX_TFE;
347 memcpy(p->rfis + offset, fis, len);
357 ahci_write_fis_piosetup(struct ahci_port *p)
361 memset(fis, 0, sizeof(fis));
362 fis[0] = FIS_TYPE_PIOSETUP;
363 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
367 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
372 error = (tfd >> 8) & 0xff;
374 memset(fis, 0, sizeof(fis));
375 fis[0] = FIS_TYPE_SETDEVBITS;
379 if (fis[2] & ATA_S_ERROR) {
380 p->err_cfis[0] = slot;
381 p->err_cfis[2] = tfd;
382 p->err_cfis[3] = error;
383 memcpy(&p->err_cfis[4], cfis + 4, 16);
385 *(uint32_t *)(fis + 4) = (1 << slot);
386 p->sact &= ~(1 << slot);
390 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
394 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
399 error = (tfd >> 8) & 0xff;
400 memset(fis, 0, sizeof(fis));
401 fis[0] = FIS_TYPE_REGD2H;
415 if (fis[2] & ATA_S_ERROR) {
416 p->err_cfis[0] = 0x80;
417 p->err_cfis[2] = tfd & 0xff;
418 p->err_cfis[3] = error;
419 memcpy(&p->err_cfis[4], cfis + 4, 16);
421 p->ci &= ~(1 << slot);
423 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
427 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot)
431 p->tfd = ATA_S_READY | ATA_S_DSC;
432 memset(fis, 0, sizeof(fis));
433 fis[0] = FIS_TYPE_REGD2H;
434 fis[1] = 0; /* No interrupt */
435 fis[2] = p->tfd; /* Status */
436 fis[3] = 0; /* No error */
437 p->ci &= ~(1 << slot);
438 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
442 ahci_write_reset_fis_d2h(struct ahci_port *p)
446 memset(fis, 0, sizeof(fis));
447 fis[0] = FIS_TYPE_REGD2H;
455 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
459 ahci_check_stopped(struct ahci_port *p)
462 * If we are no longer processing the command list and nothing
463 * is in-flight, clear the running bit, the current command
464 * slot, the command issue and active bits.
466 if (!(p->cmd & AHCI_P_CMD_ST)) {
467 if (p->pending == 0) {
469 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
478 ahci_port_stop(struct ahci_port *p)
480 struct ahci_ioreq *aior;
485 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
487 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
489 * Try to cancel the outstanding blockif request.
491 error = blockif_cancel(p->bctx, &aior->io_req);
497 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
498 cfis[2] == ATA_READ_FPDMA_QUEUED ||
499 cfis[2] == ATA_SEND_FPDMA_QUEUED)
500 p->sact &= ~(1 << slot); /* NCQ */
502 p->ci &= ~(1 << slot);
505 * This command is now done.
507 p->pending &= ~(1 << slot);
510 * Delete the blockif request from the busy list
512 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
515 * Move the blockif request back to the free list
517 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
520 ahci_check_stopped(p);
524 ahci_port_reset(struct ahci_port *pr)
528 pr->xfermode = ATA_UDMA6;
529 pr->mult_sectors = 128;
532 pr->ssts = ATA_SS_DET_NO_DEVICE;
533 pr->sig = 0xFFFFFFFF;
537 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
538 if (pr->sctl & ATA_SC_SPD_MASK)
539 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
541 pr->ssts |= ATA_SS_SPD_GEN3;
542 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
545 pr->tfd |= ATA_S_READY;
547 pr->sig = PxSIG_ATAPI;
548 ahci_write_reset_fis_d2h(pr);
552 ahci_reset(struct pci_ahci_softc *sc)
556 sc->ghc = AHCI_GHC_AE;
560 pci_lintr_deassert(sc->asc_pi);
564 for (i = 0; i < sc->ports; i++) {
567 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD);
568 if (sc->port[i].bctx)
569 sc->port[i].cmd |= AHCI_P_CMD_CPS;
570 sc->port[i].sctl = 0;
571 ahci_port_reset(&sc->port[i]);
576 ata_string(uint8_t *dest, const char *src, int len)
580 for (i = 0; i < len; i++) {
582 dest[i ^ 1] = *src++;
589 atapi_string(uint8_t *dest, const char *src, int len)
593 for (i = 0; i < len; i++) {
602 * Build up the iovec based on the PRDT, 'done' and 'len'.
605 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior,
606 struct ahci_prdt_entry *prdt, uint16_t prdtl)
608 struct blockif_req *breq = &aior->io_req;
609 int i, j, skip, todo, left, extra;
612 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */
614 left = aior->len - aior->done;
616 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0;
618 dbcsz = (prdt->dbc & DBCMASK) + 1;
619 /* Skip already done part of the PRDT */
627 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc),
628 prdt->dba + skip, dbcsz);
629 breq->br_iov[j].iov_len = dbcsz;
636 /* If we got limited by IOV length, round I/O down to sector size. */
637 if (j == BLOCKIF_IOV_MAX) {
638 extra = todo % blockif_sectsz(p->bctx);
642 if (breq->br_iov[j - 1].iov_len > extra) {
643 breq->br_iov[j - 1].iov_len -= extra;
646 extra -= breq->br_iov[j - 1].iov_len;
652 breq->br_resid = todo;
654 aior->more = (aior->done < aior->len && i < prdtl);
658 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
660 struct ahci_ioreq *aior;
661 struct blockif_req *breq;
662 struct ahci_prdt_entry *prdt;
663 struct ahci_cmd_hdr *hdr;
666 int err, first, ncq, readop;
668 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
669 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
674 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
675 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
676 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
677 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
680 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
681 cfis[2] == ATA_READ_FPDMA_QUEUED) {
682 lba = ((uint64_t)cfis[10] << 40) |
683 ((uint64_t)cfis[9] << 32) |
684 ((uint64_t)cfis[8] << 24) |
685 ((uint64_t)cfis[6] << 16) |
686 ((uint64_t)cfis[5] << 8) |
688 len = cfis[11] << 8 | cfis[3];
692 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
693 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
694 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
695 lba = ((uint64_t)cfis[10] << 40) |
696 ((uint64_t)cfis[9] << 32) |
697 ((uint64_t)cfis[8] << 24) |
698 ((uint64_t)cfis[6] << 16) |
699 ((uint64_t)cfis[5] << 8) |
701 len = cfis[13] << 8 | cfis[12];
705 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
706 (cfis[5] << 8) | cfis[4];
711 lba *= blockif_sectsz(p->bctx);
712 len *= blockif_sectsz(p->bctx);
714 /* Pull request off free list */
715 aior = STAILQ_FIRST(&p->iofhd);
716 assert(aior != NULL);
717 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
723 breq = &aior->io_req;
724 breq->br_offset = lba + done;
725 ahci_build_iov(p, aior, prdt, hdr->prdtl);
727 /* Mark this command in-flight. */
728 p->pending |= 1 << slot;
730 /* Stuff request onto busy list. */
731 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
734 ahci_write_fis_d2h_ncq(p, slot);
737 err = blockif_read(p->bctx, breq);
739 err = blockif_write(p->bctx, breq);
744 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
746 struct ahci_ioreq *aior;
747 struct blockif_req *breq;
751 * Pull request off free list
753 aior = STAILQ_FIRST(&p->iofhd);
754 assert(aior != NULL);
755 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
761 breq = &aior->io_req;
764 * Mark this command in-flight.
766 p->pending |= 1 << slot;
769 * Stuff request onto busy list
771 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
773 err = blockif_flush(p->bctx, breq);
778 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
781 struct ahci_cmd_hdr *hdr;
782 struct ahci_prdt_entry *prdt;
786 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
789 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
790 for (i = 0; i < hdr->prdtl && len; i++) {
795 dbcsz = (prdt->dbc & DBCMASK) + 1;
796 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
797 sublen = MIN(len, dbcsz);
798 memcpy(to, ptr, sublen);
806 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
808 struct ahci_ioreq *aior;
809 struct blockif_req *breq;
817 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
818 len = (uint16_t)cfis[13] << 8 | cfis[12];
821 } else { /* ATA_SEND_FPDMA_QUEUED */
822 len = (uint16_t)cfis[11] << 8 | cfis[3];
826 read_prdt(p, slot, cfis, buf, sizeof(buf));
830 elba = ((uint64_t)entry[5] << 40) |
831 ((uint64_t)entry[4] << 32) |
832 ((uint64_t)entry[3] << 24) |
833 ((uint64_t)entry[2] << 16) |
834 ((uint64_t)entry[1] << 8) |
836 elen = (uint16_t)entry[7] << 8 | entry[6];
842 ahci_write_fis_d2h_ncq(p, slot);
843 ahci_write_fis_sdb(p, slot, cfis,
844 ATA_S_READY | ATA_S_DSC);
846 ahci_write_fis_d2h(p, slot, cfis,
847 ATA_S_READY | ATA_S_DSC);
849 p->pending &= ~(1 << slot);
850 ahci_check_stopped(p);
859 * Pull request off free list
861 aior = STAILQ_FIRST(&p->iofhd);
862 assert(aior != NULL);
863 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
868 aior->more = (len != done);
870 breq = &aior->io_req;
871 breq->br_offset = elba * blockif_sectsz(p->bctx);
872 breq->br_resid = elen * blockif_sectsz(p->bctx);
875 * Mark this command in-flight.
877 p->pending |= 1 << slot;
880 * Stuff request onto busy list
882 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
885 ahci_write_fis_d2h_ncq(p, slot);
887 err = blockif_delete(p->bctx, breq);
892 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
895 struct ahci_cmd_hdr *hdr;
896 struct ahci_prdt_entry *prdt;
900 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
903 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
904 for (i = 0; i < hdr->prdtl && len; i++) {
909 dbcsz = (prdt->dbc & DBCMASK) + 1;
910 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
911 sublen = MIN(len, dbcsz);
912 memcpy(ptr, from, sublen);
917 hdr->prdbc = size - len;
921 ahci_checksum(uint8_t *buf, int size)
926 for (i = 0; i < size - 1; i++)
928 buf[size - 1] = 0x100 - sum;
932 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
934 struct ahci_cmd_hdr *hdr;
936 uint8_t *buf8 = (uint8_t *)buf;
937 uint16_t *buf16 = (uint16_t *)buf;
939 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
940 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 ||
941 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
942 ahci_write_fis_d2h(p, slot, cfis,
943 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
947 memset(buf, 0, sizeof(buf));
948 if (cfis[4] == 0x00) { /* Log directory */
949 buf16[0x00] = 1; /* Version -- 1 */
950 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */
951 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */
952 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */
953 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis));
954 ahci_checksum(buf8, sizeof(buf));
955 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */
956 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) {
957 buf[0x00] = 1; /* SFQ DSM supported */
958 buf[0x01] = 1; /* SFQ DSM TRIM supported */
961 ahci_write_fis_d2h(p, slot, cfis,
962 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
966 if (cfis[2] == ATA_READ_LOG_EXT)
967 ahci_write_fis_piosetup(p);
968 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
969 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
973 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
975 struct ahci_cmd_hdr *hdr;
977 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
978 if (p->atapi || hdr->prdtl == 0) {
979 ahci_write_fis_d2h(p, slot, cfis,
980 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
984 int sectsz, psectsz, psectoff, candelete, ro;
988 ro = blockif_is_ro(p->bctx);
989 candelete = blockif_candelete(p->bctx);
990 sectsz = blockif_sectsz(p->bctx);
991 sectors = blockif_size(p->bctx) / sectsz;
992 blockif_chs(p->bctx, &cyl, &heads, &sech);
993 blockif_psectsz(p->bctx, &psectsz, &psectoff);
994 memset(buf, 0, sizeof(buf));
999 ata_string((uint8_t *)(buf+10), p->ident, 20);
1000 ata_string((uint8_t *)(buf+23), "001", 8);
1001 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
1002 buf[47] = (0x8000 | 128);
1004 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
1005 buf[50] = (1 << 14);
1006 buf[53] = (1 << 1 | 1 << 2);
1007 if (p->mult_sectors)
1008 buf[59] = (0x100 | p->mult_sectors);
1009 if (sectors <= 0x0fffffff) {
1011 buf[61] = (sectors >> 16);
1017 if (p->xfermode & ATA_WDMA0)
1018 buf[63] |= (1 << ((p->xfermode & 7) + 8));
1026 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
1028 buf[77] = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
1029 (p->ssts & ATA_SS_SPD_MASK) >> 3);
1032 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
1033 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1034 buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1035 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
1036 buf[84] = (1 << 14);
1037 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
1038 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1039 buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1040 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
1041 buf[87] = (1 << 14);
1043 if (p->xfermode & ATA_UDMA0)
1044 buf[88] |= (1 << ((p->xfermode & 7) + 8));
1046 buf[101] = (sectors >> 16);
1047 buf[102] = (sectors >> 32);
1048 buf[103] = (sectors >> 48);
1049 if (candelete && !ro) {
1050 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
1052 buf[169] = ATA_SUPPORT_DSM_TRIM;
1056 if (psectsz > sectsz) {
1058 buf[106] |= ffsl(psectsz / sectsz) - 1;
1059 buf[209] |= (psectoff / sectsz);
1063 buf[117] = sectsz / 2;
1064 buf[118] = ((sectsz / 2) >> 16);
1066 buf[119] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1067 buf[120] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1070 ahci_checksum((uint8_t *)buf, sizeof(buf));
1071 ahci_write_fis_piosetup(p);
1072 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
1073 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1078 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1081 ahci_write_fis_d2h(p, slot, cfis,
1082 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1086 memset(buf, 0, sizeof(buf));
1087 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
1088 ata_string((uint8_t *)(buf+10), p->ident, 20);
1089 ata_string((uint8_t *)(buf+23), "001", 8);
1090 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
1091 buf[49] = (1 << 9 | 1 << 8);
1092 buf[50] = (1 << 14 | 1);
1093 buf[53] = (1 << 2 | 1 << 1);
1096 if (p->xfermode & ATA_WDMA0)
1097 buf[63] |= (1 << ((p->xfermode & 7) + 8));
1103 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
1104 buf[77] = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
1107 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1108 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1109 buf[83] = (1 << 14);
1110 buf[84] = (1 << 14);
1111 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1112 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1113 buf[87] = (1 << 14);
1115 if (p->xfermode & ATA_UDMA0)
1116 buf[88] |= (1 << ((p->xfermode & 7) + 8));
1119 ahci_checksum((uint8_t *)buf, sizeof(buf));
1120 ahci_write_fis_piosetup(p);
1121 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
1122 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1127 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
1136 if (acmd[1] & 1) { /* VPD */
1137 if (acmd[2] == 0) { /* Supported VPD pages */
1145 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1147 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1148 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1149 ahci_write_fis_d2h(p, slot, cfis, tfd);
1161 atapi_string(buf + 8, "BHYVE", 8);
1162 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1163 atapi_string(buf + 32, "001", 4);
1169 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1170 write_prdt(p, slot, cfis, buf, len);
1171 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1175 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1180 sectors = blockif_size(p->bctx) / 2048;
1181 be32enc(buf, sectors - 1);
1182 be32enc(buf + 4, 2048);
1183 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1184 write_prdt(p, slot, cfis, buf, sizeof(buf));
1185 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1189 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1197 len = be16dec(acmd + 7);
1198 format = acmd[9] >> 6;
1204 uint8_t start_track, buf[20], *bp;
1206 msf = (acmd[1] >> 1) & 1;
1207 start_track = acmd[6];
1208 if (start_track > 1 && start_track != 0xaa) {
1210 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1212 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1213 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1214 ahci_write_fis_d2h(p, slot, cfis, tfd);
1220 if (start_track <= 1) {
1240 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1244 lba_to_msf(bp, sectors);
1247 be32enc(bp, sectors);
1251 be16enc(buf, size - 2);
1254 write_prdt(p, slot, cfis, buf, len);
1255 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1256 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1263 memset(buf, 0, sizeof(buf));
1267 if (len > sizeof(buf))
1269 write_prdt(p, slot, cfis, buf, len);
1270 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1271 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1278 uint8_t *bp, buf[50];
1280 msf = (acmd[1] >> 1) & 1;
1316 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1320 lba_to_msf(bp, sectors);
1323 be32enc(bp, sectors);
1346 be16enc(buf, size - 2);
1349 write_prdt(p, slot, cfis, buf, len);
1350 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1351 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1358 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1360 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1361 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1362 ahci_write_fis_d2h(p, slot, cfis, tfd);
1369 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1373 memset(buf, 0, sizeof(buf));
1376 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1377 write_prdt(p, slot, cfis, buf, sizeof(buf));
1378 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1382 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
1384 struct ahci_ioreq *aior;
1385 struct ahci_cmd_hdr *hdr;
1386 struct ahci_prdt_entry *prdt;
1387 struct blockif_req *breq;
1394 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1395 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1397 lba = be32dec(acmd + 2);
1398 if (acmd[0] == READ_10)
1399 len = be16dec(acmd + 7);
1401 len = be32dec(acmd + 6);
1403 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1404 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1410 * Pull request off free list
1412 aior = STAILQ_FIRST(&p->iofhd);
1413 assert(aior != NULL);
1414 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1419 breq = &aior->io_req;
1420 breq->br_offset = lba + done;
1421 ahci_build_iov(p, aior, prdt, hdr->prdtl);
1423 /* Mark this command in-flight. */
1424 p->pending |= 1 << slot;
1426 /* Stuff request onto busy list. */
1427 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1429 err = blockif_read(p->bctx, breq);
1434 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1442 if (len > sizeof(buf))
1444 memset(buf, 0, len);
1445 buf[0] = 0x70 | (1 << 7);
1446 buf[2] = p->sense_key;
1449 write_prdt(p, slot, cfis, buf, len);
1450 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1451 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1455 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1457 uint8_t *acmd = cfis + 0x40;
1460 switch (acmd[4] & 3) {
1464 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1465 tfd = ATA_S_READY | ATA_S_DSC;
1468 /* TODO eject media */
1469 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1470 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1472 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1475 ahci_write_fis_d2h(p, slot, cfis, tfd);
1479 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1487 len = be16dec(acmd + 7);
1489 code = acmd[2] & 0x3f;
1494 case MODEPAGE_RW_ERROR_RECOVERY:
1498 if (len > sizeof(buf))
1501 memset(buf, 0, sizeof(buf));
1502 be16enc(buf, 16 - 2);
1507 write_prdt(p, slot, cfis, buf, len);
1508 tfd = ATA_S_READY | ATA_S_DSC;
1511 case MODEPAGE_CD_CAPABILITIES:
1515 if (len > sizeof(buf))
1518 memset(buf, 0, sizeof(buf));
1519 be16enc(buf, 30 - 2);
1525 be16enc(&buf[18], 2);
1526 be16enc(&buf[20], 512);
1527 write_prdt(p, slot, cfis, buf, len);
1528 tfd = ATA_S_READY | ATA_S_DSC;
1537 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1539 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1544 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1546 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1549 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1550 ahci_write_fis_d2h(p, slot, cfis, tfd);
1554 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1562 /* we don't support asynchronous operation */
1563 if (!(acmd[1] & 1)) {
1564 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1566 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1571 len = be16dec(acmd + 7);
1572 if (len > sizeof(buf))
1575 memset(buf, 0, sizeof(buf));
1576 be16enc(buf, 8 - 2);
1580 write_prdt(p, slot, cfis, buf, len);
1581 tfd = ATA_S_READY | ATA_S_DSC;
1583 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1584 ahci_write_fis_d2h(p, slot, cfis, tfd);
1588 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1598 for (i = 0; i < 16; i++)
1599 DPRINTF("%02x ", acmd[i]);
1605 case TEST_UNIT_READY:
1606 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1607 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1610 atapi_inquiry(p, slot, cfis);
1613 atapi_read_capacity(p, slot, cfis);
1617 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1618 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1621 atapi_read_toc(p, slot, cfis);
1624 atapi_report_luns(p, slot, cfis);
1628 atapi_read(p, slot, cfis, 0);
1631 atapi_request_sense(p, slot, cfis);
1633 case START_STOP_UNIT:
1634 atapi_start_stop_unit(p, slot, cfis);
1637 atapi_mode_sense(p, slot, cfis);
1639 case GET_EVENT_STATUS_NOTIFICATION:
1640 atapi_get_event_status_notification(p, slot, cfis);
1643 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1644 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1646 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1647 ATA_S_READY | ATA_S_ERROR);
1653 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1656 p->tfd |= ATA_S_BUSY;
1658 case ATA_ATA_IDENTIFY:
1659 handle_identify(p, slot, cfis);
1661 case ATA_SETFEATURES:
1664 case ATA_SF_ENAB_SATA_SF:
1666 case ATA_SATA_SF_AN:
1667 p->tfd = ATA_S_DSC | ATA_S_READY;
1670 p->tfd = ATA_S_ERROR | ATA_S_READY;
1671 p->tfd |= (ATA_ERROR_ABORT << 8);
1675 case ATA_SF_ENAB_WCACHE:
1676 case ATA_SF_DIS_WCACHE:
1677 case ATA_SF_ENAB_RCACHE:
1678 case ATA_SF_DIS_RCACHE:
1679 p->tfd = ATA_S_DSC | ATA_S_READY;
1681 case ATA_SF_SETXFER:
1683 switch (cfis[12] & 0xf8) {
1689 p->xfermode = (cfis[12] & 0x7);
1692 p->tfd = ATA_S_DSC | ATA_S_READY;
1696 p->tfd = ATA_S_ERROR | ATA_S_READY;
1697 p->tfd |= (ATA_ERROR_ABORT << 8);
1700 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1704 if (cfis[12] != 0 &&
1705 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1706 p->tfd = ATA_S_ERROR | ATA_S_READY;
1707 p->tfd |= (ATA_ERROR_ABORT << 8);
1709 p->mult_sectors = cfis[12];
1710 p->tfd = ATA_S_DSC | ATA_S_READY;
1712 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1720 case ATA_READ_MUL48:
1721 case ATA_WRITE_MUL48:
1724 case ATA_READ_DMA48:
1725 case ATA_WRITE_DMA48:
1726 case ATA_READ_FPDMA_QUEUED:
1727 case ATA_WRITE_FPDMA_QUEUED:
1728 ahci_handle_rw(p, slot, cfis, 0);
1730 case ATA_FLUSHCACHE:
1731 case ATA_FLUSHCACHE48:
1732 ahci_handle_flush(p, slot, cfis);
1734 case ATA_DATA_SET_MANAGEMENT:
1735 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1736 cfis[13] == 0 && cfis[12] == 1) {
1737 ahci_handle_dsm_trim(p, slot, cfis, 0);
1740 ahci_write_fis_d2h(p, slot, cfis,
1741 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1743 case ATA_SEND_FPDMA_QUEUED:
1744 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1745 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1746 cfis[11] == 0 && cfis[3] == 1) {
1747 ahci_handle_dsm_trim(p, slot, cfis, 0);
1750 ahci_write_fis_d2h(p, slot, cfis,
1751 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1753 case ATA_READ_LOG_EXT:
1754 case ATA_READ_LOG_DMA_EXT:
1755 ahci_handle_read_log(p, slot, cfis);
1757 case ATA_SECURITY_FREEZE_LOCK:
1760 ahci_write_fis_d2h(p, slot, cfis,
1761 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1763 case ATA_CHECK_POWER_MODE:
1764 cfis[12] = 0xff; /* always on */
1765 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1767 case ATA_STANDBY_CMD:
1768 case ATA_STANDBY_IMMEDIATE:
1770 case ATA_IDLE_IMMEDIATE:
1772 case ATA_READ_VERIFY:
1773 case ATA_READ_VERIFY48:
1774 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1776 case ATA_ATAPI_IDENTIFY:
1777 handle_atapi_identify(p, slot, cfis);
1779 case ATA_PACKET_CMD:
1781 ahci_write_fis_d2h(p, slot, cfis,
1782 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1784 handle_packet_cmd(p, slot, cfis);
1787 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1788 ahci_write_fis_d2h(p, slot, cfis,
1789 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1795 ahci_handle_slot(struct ahci_port *p, int slot)
1797 struct ahci_cmd_hdr *hdr;
1799 struct ahci_prdt_entry *prdt;
1801 struct pci_ahci_softc *sc;
1808 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1810 cfl = (hdr->flags & 0x1f) * 4;
1812 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1813 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1815 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1818 for (i = 0; i < cfl; i++) {
1821 DPRINTF("%02x ", cfis[i]);
1825 for (i = 0; i < hdr->prdtl; i++) {
1826 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1831 if (cfis[0] != FIS_TYPE_REGH2D) {
1832 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1836 if (cfis[1] & 0x80) {
1837 ahci_handle_cmd(p, slot, cfis);
1839 if (cfis[15] & (1 << 2))
1841 else if (p->reset) {
1845 p->ci &= ~(1 << slot);
1850 ahci_handle_port(struct ahci_port *p)
1853 if (!(p->cmd & AHCI_P_CMD_ST))
1857 * Search for any new commands to issue ignoring those that
1858 * are already in-flight. Stop if device is busy or in error.
1860 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) {
1861 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0)
1863 if (p->waitforclear)
1865 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) {
1866 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1867 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT;
1868 ahci_handle_slot(p, p->ccs);
1874 * blockif callback routine - this runs in the context of the blockif
1875 * i/o thread, so the mutex needs to be acquired.
1878 ata_ioreq_cb(struct blockif_req *br, int err)
1880 struct ahci_cmd_hdr *hdr;
1881 struct ahci_ioreq *aior;
1882 struct ahci_port *p;
1883 struct pci_ahci_softc *sc;
1888 DPRINTF("%s %d\n", __func__, err);
1891 aior = br->br_param;
1896 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1898 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1899 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1900 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1902 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1903 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1904 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1907 pthread_mutex_lock(&sc->mtx);
1910 * Delete the blockif request from the busy list
1912 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1915 * Move the blockif request back to the free list
1917 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1920 hdr->prdbc = aior->done;
1922 if (!err && aior->more) {
1924 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1926 ahci_handle_rw(p, slot, cfis, aior->done);
1931 tfd = ATA_S_READY | ATA_S_DSC;
1933 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1935 ahci_write_fis_sdb(p, slot, cfis, tfd);
1937 ahci_write_fis_d2h(p, slot, cfis, tfd);
1940 * This command is now complete.
1942 p->pending &= ~(1 << slot);
1944 ahci_check_stopped(p);
1945 ahci_handle_port(p);
1947 pthread_mutex_unlock(&sc->mtx);
1948 DPRINTF("%s exit\n", __func__);
1952 atapi_ioreq_cb(struct blockif_req *br, int err)
1954 struct ahci_cmd_hdr *hdr;
1955 struct ahci_ioreq *aior;
1956 struct ahci_port *p;
1957 struct pci_ahci_softc *sc;
1962 DPRINTF("%s %d\n", __func__, err);
1964 aior = br->br_param;
1969 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1971 pthread_mutex_lock(&sc->mtx);
1974 * Delete the blockif request from the busy list
1976 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1979 * Move the blockif request back to the free list
1981 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1984 hdr->prdbc = aior->done;
1986 if (!err && aior->more) {
1987 atapi_read(p, slot, cfis, aior->done);
1992 tfd = ATA_S_READY | ATA_S_DSC;
1994 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1996 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1998 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1999 ahci_write_fis_d2h(p, slot, cfis, tfd);
2002 * This command is now complete.
2004 p->pending &= ~(1 << slot);
2006 ahci_check_stopped(p);
2007 ahci_handle_port(p);
2009 pthread_mutex_unlock(&sc->mtx);
2010 DPRINTF("%s exit\n", __func__);
2014 pci_ahci_ioreq_init(struct ahci_port *pr)
2016 struct ahci_ioreq *vr;
2019 pr->ioqsz = blockif_queuesz(pr->bctx);
2020 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
2021 STAILQ_INIT(&pr->iofhd);
2024 * Add all i/o request entries to the free queue
2026 for (i = 0; i < pr->ioqsz; i++) {
2030 vr->io_req.br_callback = ata_ioreq_cb;
2032 vr->io_req.br_callback = atapi_ioreq_cb;
2033 vr->io_req.br_param = vr;
2034 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
2037 TAILQ_INIT(&pr->iobhd);
2041 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2043 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2044 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2045 struct ahci_port *p = &sc->port[port];
2047 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
2048 port, offset, value);
2068 p->ie = value & 0xFDC000FF;
2073 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2074 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2075 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2076 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK);
2077 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2078 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2079 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2080 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value;
2082 if (!(value & AHCI_P_CMD_ST)) {
2087 p->cmd |= AHCI_P_CMD_CR;
2088 clb = (uint64_t)p->clbu << 32 | p->clb;
2089 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
2090 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
2093 if (value & AHCI_P_CMD_FRE) {
2096 p->cmd |= AHCI_P_CMD_FR;
2097 fb = (uint64_t)p->fbu << 32 | p->fb;
2098 /* we don't support FBSCP, so rfis size is 256Bytes */
2099 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
2101 p->cmd &= ~AHCI_P_CMD_FR;
2104 if (value & AHCI_P_CMD_CLO) {
2105 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ);
2106 p->cmd &= ~AHCI_P_CMD_CLO;
2109 if (value & AHCI_P_CMD_ICC_MASK) {
2110 p->cmd &= ~AHCI_P_CMD_ICC_MASK;
2113 ahci_handle_port(p);
2119 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
2123 if (!(p->cmd & AHCI_P_CMD_ST)) {
2124 if (value & ATA_SC_DET_RESET)
2136 ahci_handle_port(p);
2146 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2148 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
2156 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
2159 if (value & AHCI_GHC_HR) {
2163 if (value & AHCI_GHC_IE)
2164 sc->ghc |= AHCI_GHC_IE;
2166 sc->ghc &= ~AHCI_GHC_IE;
2167 ahci_generate_intr(sc, 0xffffffff);
2171 ahci_generate_intr(sc, value);
2179 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
2180 int baridx, uint64_t offset, int size, uint64_t value)
2182 struct pci_ahci_softc *sc = pi->pi_arg;
2184 assert(baridx == 5);
2185 assert((offset % 4) == 0 && size == 4);
2187 pthread_mutex_lock(&sc->mtx);
2189 if (offset < AHCI_OFFSET)
2190 pci_ahci_host_write(sc, offset, value);
2191 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2192 pci_ahci_port_write(sc, offset, value);
2194 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
2196 pthread_mutex_unlock(&sc->mtx);
2200 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2216 uint32_t *p = &sc->cap;
2217 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2225 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
2232 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2235 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2236 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2256 uint32_t *p= &sc->port[port].clb;
2257 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2266 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
2267 port, offset, value);
2273 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2274 uint64_t regoff, int size)
2276 struct pci_ahci_softc *sc = pi->pi_arg;
2280 assert(baridx == 5);
2281 assert(size == 1 || size == 2 || size == 4);
2282 assert((regoff & (size - 1)) == 0);
2284 pthread_mutex_lock(&sc->mtx);
2286 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */
2287 if (offset < AHCI_OFFSET)
2288 value = pci_ahci_host_read(sc, offset);
2289 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2290 value = pci_ahci_port_read(sc, offset);
2293 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n",
2296 value >>= 8 * (regoff & 0x3);
2298 pthread_mutex_unlock(&sc->mtx);
2304 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2306 char bident[sizeof("XX:XX:XX")];
2307 struct blockif_ctxt *bctxt;
2308 struct pci_ahci_softc *sc;
2317 dbg = fopen("/tmp/log", "w+");
2320 sc = calloc(1, sizeof(struct pci_ahci_softc));
2323 pthread_mutex_init(&sc->mtx, NULL);
2328 for (p = 0; p < MAX_PORTS && opts != NULL; p++, opts = next) {
2329 /* Identify and cut off type of present port. */
2330 if (strncmp(opts, "hd:", 3) == 0) {
2333 } else if (strncmp(opts, "cd:", 3) == 0) {
2338 /* Find and cut off the next port options. */
2339 next = strstr(opts, ",hd:");
2340 next2 = strstr(opts, ",cd:");
2341 if (next == NULL || (next2 != NULL && next2 < next))
2352 * Attempt to open the backing image. Use the PCI slot/func
2353 * and the port number for the identifier string.
2355 snprintf(bident, sizeof(bident), "%d:%d:%d", pi->pi_slot,
2357 bctxt = blockif_open(opts, bident);
2358 if (bctxt == NULL) {
2363 sc->port[p].bctx = bctxt;
2364 sc->port[p].pr_sc = sc;
2365 sc->port[p].port = p;
2366 sc->port[p].atapi = atapi;
2369 * Create an identifier for the backing file.
2370 * Use parts of the md5 sum of the filename
2373 MD5Update(&mdctx, opts, strlen(opts));
2374 MD5Final(digest, &mdctx);
2375 sprintf(sc->port[p].ident, "BHYVE-%02X%02X-%02X%02X-%02X%02X",
2376 digest[0], digest[1], digest[2], digest[3], digest[4],
2380 * Allocate blockif request structures and add them
2383 pci_ahci_ioreq_init(&sc->port[p]);
2386 if (sc->port[p].ioqsz < slots)
2387 slots = sc->port[p].ioqsz;
2391 /* Intel ICH8 AHCI */
2393 if (sc->ports < DEF_PORTS)
2394 sc->ports = DEF_PORTS;
2395 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2396 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2397 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2398 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2399 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2402 sc->cap2 = AHCI_CAP2_APST;
2405 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2406 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2407 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2408 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2409 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2410 p = MIN(sc->ports, 16);
2411 p = flsl(p) - ((p & (p - 1)) ? 0 : 1);
2412 pci_emul_add_msicap(pi, 1 << p);
2413 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2414 AHCI_OFFSET + sc->ports * AHCI_STEP);
2416 pci_lintr_request(pi);
2420 for (p = 0; p < sc->ports; p++) {
2421 if (sc->port[p].bctx != NULL)
2422 blockif_close(sc->port[p].bctx);
2431 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2434 return (pci_ahci_init(ctx, pi, opts, 0));
2438 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2441 return (pci_ahci_init(ctx, pi, opts, 1));
2445 * Use separate emulation names to distinguish drive and atapi devices
2447 struct pci_devemu pci_de_ahci = {
2449 .pe_init = pci_ahci_hd_init,
2450 .pe_barwrite = pci_ahci_write,
2451 .pe_barread = pci_ahci_read
2453 PCI_EMUL_SET(pci_de_ahci);
2455 struct pci_devemu pci_de_ahci_hd = {
2456 .pe_emu = "ahci-hd",
2457 .pe_init = pci_ahci_hd_init,
2458 .pe_barwrite = pci_ahci_write,
2459 .pe_barread = pci_ahci_read
2461 PCI_EMUL_SET(pci_de_ahci_hd);
2463 struct pci_devemu pci_de_ahci_cd = {
2464 .pe_emu = "ahci-cd",
2465 .pe_init = pci_ahci_atapi_init,
2466 .pe_barwrite = pci_ahci_write,
2467 .pe_barread = pci_ahci_read
2469 PCI_EMUL_SET(pci_de_ahci_cd);