2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/linker_set.h>
39 #include <sys/ioctl.h>
42 #include <sys/endian.h>
54 #include <pthread_np.h>
63 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
64 #define MAX_PORTS 32 /* AHCI supports 32 ports */
66 #define PxSIG_ATA 0x00000101 /* ATA drive */
67 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
70 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
71 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
72 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
73 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
74 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
75 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
76 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
77 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
83 #define TEST_UNIT_READY 0x00
84 #define REQUEST_SENSE 0x03
86 #define START_STOP_UNIT 0x1B
87 #define PREVENT_ALLOW 0x1E
88 #define READ_CAPACITY 0x25
90 #define POSITION_TO_ELEMENT 0x2B
92 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
93 #define MODE_SENSE_10 0x5A
94 #define REPORT_LUNS 0xA0
99 * SCSI mode page codes
101 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
102 #define MODEPAGE_CD_CAPABILITIES 0x2A
107 #define ATA_SF_ENAB_SATA_SF 0x10
108 #define ATA_SATA_SF_AN 0x05
109 #define ATA_SF_DIS_SATA_SF 0x90
116 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
118 #define DPRINTF(format, arg...)
120 #define WPRINTF(format, arg...) printf(format, ##arg)
122 #define AHCI_PORT_IDENT 20 + 1
125 struct blockif_req io_req;
126 struct ahci_port *io_pr;
127 STAILQ_ENTRY(ahci_ioreq) io_flist;
128 TAILQ_ENTRY(ahci_ioreq) io_blist;
137 struct blockif_ctxt *bctx;
138 struct pci_ahci_softc *pr_sc;
141 char ident[AHCI_PORT_IDENT];
148 uint8_t err_cfis[20];
175 struct ahci_ioreq *ioreq;
177 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
178 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
181 struct ahci_cmd_hdr {
186 uint32_t reserved[4];
189 struct ahci_prdt_entry {
192 #define DBCMASK 0x3fffff
196 struct pci_ahci_softc {
197 struct pci_devinst *asc_pi;
212 struct ahci_port port[MAX_PORTS];
214 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
216 static void ahci_handle_port(struct ahci_port *p);
218 static inline void lba_to_msf(uint8_t *buf, int lba)
221 buf[0] = (lba / 75) / 60;
222 buf[1] = (lba / 75) % 60;
227 * Generate HBA interrupts on global IS register write.
230 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask)
232 struct pci_devinst *pi = sc->asc_pi;
237 /* Update global IS from PxIS/PxIE. */
238 for (i = 0; i < sc->ports; i++) {
243 DPRINTF("%s(%08x) %08x\n", __func__, mask, sc->is);
245 /* If there is nothing enabled -- clear legacy interrupt and exit. */
246 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) {
248 pci_lintr_deassert(pi);
254 /* If there is anything and no MSI -- assert legacy interrupt. */
255 nmsg = pci_msi_maxmsgnum(pi);
259 pci_lintr_assert(pi);
264 /* Assert respective MSIs for ports that were touched. */
265 for (i = 0; i < nmsg; i++) {
266 if (sc->ports <= nmsg || i < nmsg - 1)
269 mmask = 0xffffffff << i;
270 if (sc->is & mask && mmask & mask)
271 pci_generate_msi(pi, i);
276 * Generate HBA interrupt on specific port event.
279 ahci_port_intr(struct ahci_port *p)
281 struct pci_ahci_softc *sc = p->pr_sc;
282 struct pci_devinst *pi = sc->asc_pi;
285 DPRINTF("%s(%d) %08x/%08x %08x\n", __func__,
286 p->port, p->is, p->ie, sc->is);
288 /* If there is nothing enabled -- we are done. */
289 if ((p->is & p->ie) == 0)
292 /* In case of non-shared MSI always generate interrupt. */
293 nmsg = pci_msi_maxmsgnum(pi);
294 if (sc->ports <= nmsg || p->port < nmsg - 1) {
295 sc->is |= (1 << p->port);
296 if ((sc->ghc & AHCI_GHC_IE) == 0)
298 pci_generate_msi(pi, p->port);
302 /* If IS for this port is already set -- do nothing. */
303 if (sc->is & (1 << p->port))
306 sc->is |= (1 << p->port);
308 /* If interrupts are enabled -- generate one. */
309 if ((sc->ghc & AHCI_GHC_IE) == 0)
312 pci_generate_msi(pi, nmsg - 1);
313 } else if (!sc->lintr) {
315 pci_lintr_assert(pi);
320 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
322 int offset, len, irq;
324 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
328 case FIS_TYPE_REGD2H:
331 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0;
333 case FIS_TYPE_SETDEVBITS:
336 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0;
338 case FIS_TYPE_PIOSETUP:
341 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
344 WPRINTF("unsupported fis type %d\n", ft);
347 if (fis[2] & ATA_S_ERROR) {
349 irq |= AHCI_P_IX_TFE;
351 memcpy(p->rfis + offset, fis, len);
361 ahci_write_fis_piosetup(struct ahci_port *p)
365 memset(fis, 0, sizeof(fis));
366 fis[0] = FIS_TYPE_PIOSETUP;
367 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
371 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
376 error = (tfd >> 8) & 0xff;
378 memset(fis, 0, sizeof(fis));
379 fis[0] = FIS_TYPE_SETDEVBITS;
383 if (fis[2] & ATA_S_ERROR) {
384 p->err_cfis[0] = slot;
385 p->err_cfis[2] = tfd;
386 p->err_cfis[3] = error;
387 memcpy(&p->err_cfis[4], cfis + 4, 16);
389 *(uint32_t *)(fis + 4) = (1 << slot);
390 p->sact &= ~(1 << slot);
394 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
398 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
403 error = (tfd >> 8) & 0xff;
404 memset(fis, 0, sizeof(fis));
405 fis[0] = FIS_TYPE_REGD2H;
419 if (fis[2] & ATA_S_ERROR) {
420 p->err_cfis[0] = 0x80;
421 p->err_cfis[2] = tfd & 0xff;
422 p->err_cfis[3] = error;
423 memcpy(&p->err_cfis[4], cfis + 4, 16);
425 p->ci &= ~(1 << slot);
427 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
431 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot)
435 p->tfd = ATA_S_READY | ATA_S_DSC;
436 memset(fis, 0, sizeof(fis));
437 fis[0] = FIS_TYPE_REGD2H;
438 fis[1] = 0; /* No interrupt */
439 fis[2] = p->tfd; /* Status */
440 fis[3] = 0; /* No error */
441 p->ci &= ~(1 << slot);
442 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
446 ahci_write_reset_fis_d2h(struct ahci_port *p)
450 memset(fis, 0, sizeof(fis));
451 fis[0] = FIS_TYPE_REGD2H;
459 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
463 ahci_check_stopped(struct ahci_port *p)
466 * If we are no longer processing the command list and nothing
467 * is in-flight, clear the running bit, the current command
468 * slot, the command issue and active bits.
470 if (!(p->cmd & AHCI_P_CMD_ST)) {
471 if (p->pending == 0) {
473 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
482 ahci_port_stop(struct ahci_port *p)
484 struct ahci_ioreq *aior;
489 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
491 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
493 * Try to cancel the outstanding blockif request.
495 error = blockif_cancel(p->bctx, &aior->io_req);
501 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
502 cfis[2] == ATA_READ_FPDMA_QUEUED ||
503 cfis[2] == ATA_SEND_FPDMA_QUEUED)
504 p->sact &= ~(1 << slot); /* NCQ */
506 p->ci &= ~(1 << slot);
509 * This command is now done.
511 p->pending &= ~(1 << slot);
514 * Delete the blockif request from the busy list
516 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
519 * Move the blockif request back to the free list
521 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
524 ahci_check_stopped(p);
528 ahci_port_reset(struct ahci_port *pr)
532 pr->xfermode = ATA_UDMA6;
533 pr->mult_sectors = 128;
536 pr->ssts = ATA_SS_DET_NO_DEVICE;
537 pr->sig = 0xFFFFFFFF;
541 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
542 if (pr->sctl & ATA_SC_SPD_MASK)
543 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
545 pr->ssts |= ATA_SS_SPD_GEN3;
546 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
549 pr->tfd |= ATA_S_READY;
551 pr->sig = PxSIG_ATAPI;
552 ahci_write_reset_fis_d2h(pr);
556 ahci_reset(struct pci_ahci_softc *sc)
560 sc->ghc = AHCI_GHC_AE;
564 pci_lintr_deassert(sc->asc_pi);
568 for (i = 0; i < sc->ports; i++) {
571 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD);
572 if (sc->port[i].bctx)
573 sc->port[i].cmd |= AHCI_P_CMD_CPS;
574 sc->port[i].sctl = 0;
575 ahci_port_reset(&sc->port[i]);
580 ata_string(uint8_t *dest, const char *src, int len)
584 for (i = 0; i < len; i++) {
586 dest[i ^ 1] = *src++;
593 atapi_string(uint8_t *dest, const char *src, int len)
597 for (i = 0; i < len; i++) {
606 * Build up the iovec based on the PRDT, 'done' and 'len'.
609 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior,
610 struct ahci_prdt_entry *prdt, uint16_t prdtl)
612 struct blockif_req *breq = &aior->io_req;
613 int i, j, skip, todo, left, extra;
616 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */
618 left = aior->len - aior->done;
620 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0;
622 dbcsz = (prdt->dbc & DBCMASK) + 1;
623 /* Skip already done part of the PRDT */
631 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc),
632 prdt->dba + skip, dbcsz);
633 breq->br_iov[j].iov_len = dbcsz;
640 /* If we got limited by IOV length, round I/O down to sector size. */
641 if (j == BLOCKIF_IOV_MAX) {
642 extra = todo % blockif_sectsz(p->bctx);
646 if (breq->br_iov[j - 1].iov_len > extra) {
647 breq->br_iov[j - 1].iov_len -= extra;
650 extra -= breq->br_iov[j - 1].iov_len;
656 breq->br_resid = todo;
658 aior->more = (aior->done < aior->len && i < prdtl);
662 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
664 struct ahci_ioreq *aior;
665 struct blockif_req *breq;
666 struct ahci_prdt_entry *prdt;
667 struct ahci_cmd_hdr *hdr;
670 int err, first, ncq, readop;
672 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
673 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
678 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
679 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
680 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
681 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
684 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
685 cfis[2] == ATA_READ_FPDMA_QUEUED) {
686 lba = ((uint64_t)cfis[10] << 40) |
687 ((uint64_t)cfis[9] << 32) |
688 ((uint64_t)cfis[8] << 24) |
689 ((uint64_t)cfis[6] << 16) |
690 ((uint64_t)cfis[5] << 8) |
692 len = cfis[11] << 8 | cfis[3];
696 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
697 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
698 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
699 lba = ((uint64_t)cfis[10] << 40) |
700 ((uint64_t)cfis[9] << 32) |
701 ((uint64_t)cfis[8] << 24) |
702 ((uint64_t)cfis[6] << 16) |
703 ((uint64_t)cfis[5] << 8) |
705 len = cfis[13] << 8 | cfis[12];
709 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
710 (cfis[5] << 8) | cfis[4];
715 lba *= blockif_sectsz(p->bctx);
716 len *= blockif_sectsz(p->bctx);
718 /* Pull request off free list */
719 aior = STAILQ_FIRST(&p->iofhd);
720 assert(aior != NULL);
721 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
727 breq = &aior->io_req;
728 breq->br_offset = lba + done;
729 ahci_build_iov(p, aior, prdt, hdr->prdtl);
731 /* Mark this command in-flight. */
732 p->pending |= 1 << slot;
734 /* Stuff request onto busy list. */
735 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
738 ahci_write_fis_d2h_ncq(p, slot);
741 err = blockif_read(p->bctx, breq);
743 err = blockif_write(p->bctx, breq);
748 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
750 struct ahci_ioreq *aior;
751 struct blockif_req *breq;
755 * Pull request off free list
757 aior = STAILQ_FIRST(&p->iofhd);
758 assert(aior != NULL);
759 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
765 breq = &aior->io_req;
768 * Mark this command in-flight.
770 p->pending |= 1 << slot;
773 * Stuff request onto busy list
775 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
777 err = blockif_flush(p->bctx, breq);
782 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
785 struct ahci_cmd_hdr *hdr;
786 struct ahci_prdt_entry *prdt;
790 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
793 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
794 for (i = 0; i < hdr->prdtl && len; i++) {
799 dbcsz = (prdt->dbc & DBCMASK) + 1;
800 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
801 sublen = MIN(len, dbcsz);
802 memcpy(to, ptr, sublen);
810 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
812 struct ahci_ioreq *aior;
813 struct blockif_req *breq;
821 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
822 len = (uint16_t)cfis[13] << 8 | cfis[12];
825 } else { /* ATA_SEND_FPDMA_QUEUED */
826 len = (uint16_t)cfis[11] << 8 | cfis[3];
830 read_prdt(p, slot, cfis, buf, sizeof(buf));
834 elba = ((uint64_t)entry[5] << 40) |
835 ((uint64_t)entry[4] << 32) |
836 ((uint64_t)entry[3] << 24) |
837 ((uint64_t)entry[2] << 16) |
838 ((uint64_t)entry[1] << 8) |
840 elen = (uint16_t)entry[7] << 8 | entry[6];
846 ahci_write_fis_d2h_ncq(p, slot);
847 ahci_write_fis_sdb(p, slot, cfis,
848 ATA_S_READY | ATA_S_DSC);
850 ahci_write_fis_d2h(p, slot, cfis,
851 ATA_S_READY | ATA_S_DSC);
853 p->pending &= ~(1 << slot);
854 ahci_check_stopped(p);
863 * Pull request off free list
865 aior = STAILQ_FIRST(&p->iofhd);
866 assert(aior != NULL);
867 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
872 aior->more = (len != done);
874 breq = &aior->io_req;
875 breq->br_offset = elba * blockif_sectsz(p->bctx);
876 breq->br_resid = elen * blockif_sectsz(p->bctx);
879 * Mark this command in-flight.
881 p->pending |= 1 << slot;
884 * Stuff request onto busy list
886 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
889 ahci_write_fis_d2h_ncq(p, slot);
891 err = blockif_delete(p->bctx, breq);
896 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
899 struct ahci_cmd_hdr *hdr;
900 struct ahci_prdt_entry *prdt;
904 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
907 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
908 for (i = 0; i < hdr->prdtl && len; i++) {
913 dbcsz = (prdt->dbc & DBCMASK) + 1;
914 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
915 sublen = MIN(len, dbcsz);
916 memcpy(ptr, from, sublen);
921 hdr->prdbc = size - len;
925 ahci_checksum(uint8_t *buf, int size)
930 for (i = 0; i < size - 1; i++)
932 buf[size - 1] = 0x100 - sum;
936 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
938 struct ahci_cmd_hdr *hdr;
940 uint8_t *buf8 = (uint8_t *)buf;
941 uint16_t *buf16 = (uint16_t *)buf;
943 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
944 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 ||
945 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
946 ahci_write_fis_d2h(p, slot, cfis,
947 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
951 memset(buf, 0, sizeof(buf));
952 if (cfis[4] == 0x00) { /* Log directory */
953 buf16[0x00] = 1; /* Version -- 1 */
954 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */
955 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */
956 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */
957 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis));
958 ahci_checksum(buf8, sizeof(buf));
959 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */
960 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) {
961 buf[0x00] = 1; /* SFQ DSM supported */
962 buf[0x01] = 1; /* SFQ DSM TRIM supported */
965 ahci_write_fis_d2h(p, slot, cfis,
966 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
970 if (cfis[2] == ATA_READ_LOG_EXT)
971 ahci_write_fis_piosetup(p);
972 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
973 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
977 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
979 struct ahci_cmd_hdr *hdr;
981 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
982 if (p->atapi || hdr->prdtl == 0) {
983 ahci_write_fis_d2h(p, slot, cfis,
984 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
988 int sectsz, psectsz, psectoff, candelete, ro;
992 ro = blockif_is_ro(p->bctx);
993 candelete = blockif_candelete(p->bctx);
994 sectsz = blockif_sectsz(p->bctx);
995 sectors = blockif_size(p->bctx) / sectsz;
996 blockif_chs(p->bctx, &cyl, &heads, &sech);
997 blockif_psectsz(p->bctx, &psectsz, &psectoff);
998 memset(buf, 0, sizeof(buf));
1003 ata_string((uint8_t *)(buf+10), p->ident, 20);
1004 ata_string((uint8_t *)(buf+23), "001", 8);
1005 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
1006 buf[47] = (0x8000 | 128);
1008 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
1009 buf[50] = (1 << 14);
1010 buf[53] = (1 << 1 | 1 << 2);
1011 if (p->mult_sectors)
1012 buf[59] = (0x100 | p->mult_sectors);
1013 if (sectors <= 0x0fffffff) {
1015 buf[61] = (sectors >> 16);
1021 if (p->xfermode & ATA_WDMA0)
1022 buf[63] |= (1 << ((p->xfermode & 7) + 8));
1030 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
1032 buf[77] = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
1033 (p->ssts & ATA_SS_SPD_MASK) >> 3);
1036 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
1037 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1038 buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1039 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
1040 buf[84] = (1 << 14);
1041 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
1042 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1043 buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1044 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
1045 buf[87] = (1 << 14);
1047 if (p->xfermode & ATA_UDMA0)
1048 buf[88] |= (1 << ((p->xfermode & 7) + 8));
1050 buf[101] = (sectors >> 16);
1051 buf[102] = (sectors >> 32);
1052 buf[103] = (sectors >> 48);
1053 if (candelete && !ro) {
1054 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
1056 buf[169] = ATA_SUPPORT_DSM_TRIM;
1060 if (psectsz > sectsz) {
1062 buf[106] |= ffsl(psectsz / sectsz) - 1;
1063 buf[209] |= (psectoff / sectsz);
1067 buf[117] = sectsz / 2;
1068 buf[118] = ((sectsz / 2) >> 16);
1070 buf[119] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1071 buf[120] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1074 ahci_checksum((uint8_t *)buf, sizeof(buf));
1075 ahci_write_fis_piosetup(p);
1076 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
1077 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1082 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1085 ahci_write_fis_d2h(p, slot, cfis,
1086 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1090 memset(buf, 0, sizeof(buf));
1091 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
1092 ata_string((uint8_t *)(buf+10), p->ident, 20);
1093 ata_string((uint8_t *)(buf+23), "001", 8);
1094 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
1095 buf[49] = (1 << 9 | 1 << 8);
1096 buf[50] = (1 << 14 | 1);
1097 buf[53] = (1 << 2 | 1 << 1);
1100 if (p->xfermode & ATA_WDMA0)
1101 buf[63] |= (1 << ((p->xfermode & 7) + 8));
1107 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
1108 buf[77] = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
1111 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1112 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1113 buf[83] = (1 << 14);
1114 buf[84] = (1 << 14);
1115 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1116 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1117 buf[87] = (1 << 14);
1119 if (p->xfermode & ATA_UDMA0)
1120 buf[88] |= (1 << ((p->xfermode & 7) + 8));
1123 ahci_checksum((uint8_t *)buf, sizeof(buf));
1124 ahci_write_fis_piosetup(p);
1125 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
1126 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1131 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
1140 if (acmd[1] & 1) { /* VPD */
1141 if (acmd[2] == 0) { /* Supported VPD pages */
1149 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1151 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1152 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1153 ahci_write_fis_d2h(p, slot, cfis, tfd);
1165 atapi_string(buf + 8, "BHYVE", 8);
1166 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1167 atapi_string(buf + 32, "001", 4);
1173 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1174 write_prdt(p, slot, cfis, buf, len);
1175 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1179 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1184 sectors = blockif_size(p->bctx) / 2048;
1185 be32enc(buf, sectors - 1);
1186 be32enc(buf + 4, 2048);
1187 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1188 write_prdt(p, slot, cfis, buf, sizeof(buf));
1189 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1193 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1201 len = be16dec(acmd + 7);
1202 format = acmd[9] >> 6;
1208 uint8_t start_track, buf[20], *bp;
1210 msf = (acmd[1] >> 1) & 1;
1211 start_track = acmd[6];
1212 if (start_track > 1 && start_track != 0xaa) {
1214 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1216 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1217 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1218 ahci_write_fis_d2h(p, slot, cfis, tfd);
1224 if (start_track <= 1) {
1244 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1248 lba_to_msf(bp, sectors);
1251 be32enc(bp, sectors);
1255 be16enc(buf, size - 2);
1258 write_prdt(p, slot, cfis, buf, len);
1259 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1260 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1267 memset(buf, 0, sizeof(buf));
1271 if (len > sizeof(buf))
1273 write_prdt(p, slot, cfis, buf, len);
1274 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1275 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1282 uint8_t *bp, buf[50];
1284 msf = (acmd[1] >> 1) & 1;
1320 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1324 lba_to_msf(bp, sectors);
1327 be32enc(bp, sectors);
1350 be16enc(buf, size - 2);
1353 write_prdt(p, slot, cfis, buf, len);
1354 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1355 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1362 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1364 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1365 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1366 ahci_write_fis_d2h(p, slot, cfis, tfd);
1373 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1377 memset(buf, 0, sizeof(buf));
1380 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1381 write_prdt(p, slot, cfis, buf, sizeof(buf));
1382 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1386 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
1388 struct ahci_ioreq *aior;
1389 struct ahci_cmd_hdr *hdr;
1390 struct ahci_prdt_entry *prdt;
1391 struct blockif_req *breq;
1398 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1399 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1401 lba = be32dec(acmd + 2);
1402 if (acmd[0] == READ_10)
1403 len = be16dec(acmd + 7);
1405 len = be32dec(acmd + 6);
1407 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1408 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1414 * Pull request off free list
1416 aior = STAILQ_FIRST(&p->iofhd);
1417 assert(aior != NULL);
1418 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1423 breq = &aior->io_req;
1424 breq->br_offset = lba + done;
1425 ahci_build_iov(p, aior, prdt, hdr->prdtl);
1427 /* Mark this command in-flight. */
1428 p->pending |= 1 << slot;
1430 /* Stuff request onto busy list. */
1431 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1433 err = blockif_read(p->bctx, breq);
1438 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1446 if (len > sizeof(buf))
1448 memset(buf, 0, len);
1449 buf[0] = 0x70 | (1 << 7);
1450 buf[2] = p->sense_key;
1453 write_prdt(p, slot, cfis, buf, len);
1454 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1455 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1459 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1461 uint8_t *acmd = cfis + 0x40;
1464 switch (acmd[4] & 3) {
1468 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1469 tfd = ATA_S_READY | ATA_S_DSC;
1472 /* TODO eject media */
1473 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1474 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1476 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1479 ahci_write_fis_d2h(p, slot, cfis, tfd);
1483 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1491 len = be16dec(acmd + 7);
1493 code = acmd[2] & 0x3f;
1498 case MODEPAGE_RW_ERROR_RECOVERY:
1502 if (len > sizeof(buf))
1505 memset(buf, 0, sizeof(buf));
1506 be16enc(buf, 16 - 2);
1511 write_prdt(p, slot, cfis, buf, len);
1512 tfd = ATA_S_READY | ATA_S_DSC;
1515 case MODEPAGE_CD_CAPABILITIES:
1519 if (len > sizeof(buf))
1522 memset(buf, 0, sizeof(buf));
1523 be16enc(buf, 30 - 2);
1529 be16enc(&buf[18], 2);
1530 be16enc(&buf[20], 512);
1531 write_prdt(p, slot, cfis, buf, len);
1532 tfd = ATA_S_READY | ATA_S_DSC;
1541 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1543 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1548 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1550 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1553 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1554 ahci_write_fis_d2h(p, slot, cfis, tfd);
1558 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1566 /* we don't support asynchronous operation */
1567 if (!(acmd[1] & 1)) {
1568 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1570 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1575 len = be16dec(acmd + 7);
1576 if (len > sizeof(buf))
1579 memset(buf, 0, sizeof(buf));
1580 be16enc(buf, 8 - 2);
1584 write_prdt(p, slot, cfis, buf, len);
1585 tfd = ATA_S_READY | ATA_S_DSC;
1587 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1588 ahci_write_fis_d2h(p, slot, cfis, tfd);
1592 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1602 for (i = 0; i < 16; i++)
1603 DPRINTF("%02x ", acmd[i]);
1609 case TEST_UNIT_READY:
1610 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1611 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1614 atapi_inquiry(p, slot, cfis);
1617 atapi_read_capacity(p, slot, cfis);
1621 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1622 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1625 atapi_read_toc(p, slot, cfis);
1628 atapi_report_luns(p, slot, cfis);
1632 atapi_read(p, slot, cfis, 0);
1635 atapi_request_sense(p, slot, cfis);
1637 case START_STOP_UNIT:
1638 atapi_start_stop_unit(p, slot, cfis);
1641 atapi_mode_sense(p, slot, cfis);
1643 case GET_EVENT_STATUS_NOTIFICATION:
1644 atapi_get_event_status_notification(p, slot, cfis);
1647 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1648 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1650 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1651 ATA_S_READY | ATA_S_ERROR);
1657 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1660 p->tfd |= ATA_S_BUSY;
1662 case ATA_ATA_IDENTIFY:
1663 handle_identify(p, slot, cfis);
1665 case ATA_SETFEATURES:
1668 case ATA_SF_ENAB_SATA_SF:
1670 case ATA_SATA_SF_AN:
1671 p->tfd = ATA_S_DSC | ATA_S_READY;
1674 p->tfd = ATA_S_ERROR | ATA_S_READY;
1675 p->tfd |= (ATA_ERROR_ABORT << 8);
1679 case ATA_SF_ENAB_WCACHE:
1680 case ATA_SF_DIS_WCACHE:
1681 case ATA_SF_ENAB_RCACHE:
1682 case ATA_SF_DIS_RCACHE:
1683 p->tfd = ATA_S_DSC | ATA_S_READY;
1685 case ATA_SF_SETXFER:
1687 switch (cfis[12] & 0xf8) {
1693 p->xfermode = (cfis[12] & 0x7);
1696 p->tfd = ATA_S_DSC | ATA_S_READY;
1700 p->tfd = ATA_S_ERROR | ATA_S_READY;
1701 p->tfd |= (ATA_ERROR_ABORT << 8);
1704 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1708 if (cfis[12] != 0 &&
1709 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1710 p->tfd = ATA_S_ERROR | ATA_S_READY;
1711 p->tfd |= (ATA_ERROR_ABORT << 8);
1713 p->mult_sectors = cfis[12];
1714 p->tfd = ATA_S_DSC | ATA_S_READY;
1716 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1724 case ATA_READ_MUL48:
1725 case ATA_WRITE_MUL48:
1728 case ATA_READ_DMA48:
1729 case ATA_WRITE_DMA48:
1730 case ATA_READ_FPDMA_QUEUED:
1731 case ATA_WRITE_FPDMA_QUEUED:
1732 ahci_handle_rw(p, slot, cfis, 0);
1734 case ATA_FLUSHCACHE:
1735 case ATA_FLUSHCACHE48:
1736 ahci_handle_flush(p, slot, cfis);
1738 case ATA_DATA_SET_MANAGEMENT:
1739 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1740 cfis[13] == 0 && cfis[12] == 1) {
1741 ahci_handle_dsm_trim(p, slot, cfis, 0);
1744 ahci_write_fis_d2h(p, slot, cfis,
1745 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1747 case ATA_SEND_FPDMA_QUEUED:
1748 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1749 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1750 cfis[11] == 0 && cfis[3] == 1) {
1751 ahci_handle_dsm_trim(p, slot, cfis, 0);
1754 ahci_write_fis_d2h(p, slot, cfis,
1755 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1757 case ATA_READ_LOG_EXT:
1758 case ATA_READ_LOG_DMA_EXT:
1759 ahci_handle_read_log(p, slot, cfis);
1761 case ATA_SECURITY_FREEZE_LOCK:
1764 ahci_write_fis_d2h(p, slot, cfis,
1765 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1767 case ATA_CHECK_POWER_MODE:
1768 cfis[12] = 0xff; /* always on */
1769 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1771 case ATA_STANDBY_CMD:
1772 case ATA_STANDBY_IMMEDIATE:
1774 case ATA_IDLE_IMMEDIATE:
1776 case ATA_READ_VERIFY:
1777 case ATA_READ_VERIFY48:
1778 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1780 case ATA_ATAPI_IDENTIFY:
1781 handle_atapi_identify(p, slot, cfis);
1783 case ATA_PACKET_CMD:
1785 ahci_write_fis_d2h(p, slot, cfis,
1786 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1788 handle_packet_cmd(p, slot, cfis);
1791 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1792 ahci_write_fis_d2h(p, slot, cfis,
1793 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1799 ahci_handle_slot(struct ahci_port *p, int slot)
1801 struct ahci_cmd_hdr *hdr;
1803 struct ahci_prdt_entry *prdt;
1805 struct pci_ahci_softc *sc;
1812 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1814 cfl = (hdr->flags & 0x1f) * 4;
1816 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1817 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1819 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1822 for (i = 0; i < cfl; i++) {
1825 DPRINTF("%02x ", cfis[i]);
1829 for (i = 0; i < hdr->prdtl; i++) {
1830 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1835 if (cfis[0] != FIS_TYPE_REGH2D) {
1836 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1840 if (cfis[1] & 0x80) {
1841 ahci_handle_cmd(p, slot, cfis);
1843 if (cfis[15] & (1 << 2))
1845 else if (p->reset) {
1849 p->ci &= ~(1 << slot);
1854 ahci_handle_port(struct ahci_port *p)
1857 if (!(p->cmd & AHCI_P_CMD_ST))
1861 * Search for any new commands to issue ignoring those that
1862 * are already in-flight. Stop if device is busy or in error.
1864 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) {
1865 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0)
1867 if (p->waitforclear)
1869 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) {
1870 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1871 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT;
1872 ahci_handle_slot(p, p->ccs);
1878 * blockif callback routine - this runs in the context of the blockif
1879 * i/o thread, so the mutex needs to be acquired.
1882 ata_ioreq_cb(struct blockif_req *br, int err)
1884 struct ahci_cmd_hdr *hdr;
1885 struct ahci_ioreq *aior;
1886 struct ahci_port *p;
1887 struct pci_ahci_softc *sc;
1892 DPRINTF("%s %d\n", __func__, err);
1895 aior = br->br_param;
1900 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1902 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1903 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1904 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1906 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1907 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1908 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1911 pthread_mutex_lock(&sc->mtx);
1914 * Delete the blockif request from the busy list
1916 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1919 * Move the blockif request back to the free list
1921 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1924 hdr->prdbc = aior->done;
1926 if (!err && aior->more) {
1928 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1930 ahci_handle_rw(p, slot, cfis, aior->done);
1935 tfd = ATA_S_READY | ATA_S_DSC;
1937 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1939 ahci_write_fis_sdb(p, slot, cfis, tfd);
1941 ahci_write_fis_d2h(p, slot, cfis, tfd);
1944 * This command is now complete.
1946 p->pending &= ~(1 << slot);
1948 ahci_check_stopped(p);
1949 ahci_handle_port(p);
1951 pthread_mutex_unlock(&sc->mtx);
1952 DPRINTF("%s exit\n", __func__);
1956 atapi_ioreq_cb(struct blockif_req *br, int err)
1958 struct ahci_cmd_hdr *hdr;
1959 struct ahci_ioreq *aior;
1960 struct ahci_port *p;
1961 struct pci_ahci_softc *sc;
1966 DPRINTF("%s %d\n", __func__, err);
1968 aior = br->br_param;
1973 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1975 pthread_mutex_lock(&sc->mtx);
1978 * Delete the blockif request from the busy list
1980 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1983 * Move the blockif request back to the free list
1985 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1988 hdr->prdbc = aior->done;
1990 if (!err && aior->more) {
1991 atapi_read(p, slot, cfis, aior->done);
1996 tfd = ATA_S_READY | ATA_S_DSC;
1998 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
2000 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
2002 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
2003 ahci_write_fis_d2h(p, slot, cfis, tfd);
2006 * This command is now complete.
2008 p->pending &= ~(1 << slot);
2010 ahci_check_stopped(p);
2011 ahci_handle_port(p);
2013 pthread_mutex_unlock(&sc->mtx);
2014 DPRINTF("%s exit\n", __func__);
2018 pci_ahci_ioreq_init(struct ahci_port *pr)
2020 struct ahci_ioreq *vr;
2023 pr->ioqsz = blockif_queuesz(pr->bctx);
2024 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
2025 STAILQ_INIT(&pr->iofhd);
2028 * Add all i/o request entries to the free queue
2030 for (i = 0; i < pr->ioqsz; i++) {
2034 vr->io_req.br_callback = ata_ioreq_cb;
2036 vr->io_req.br_callback = atapi_ioreq_cb;
2037 vr->io_req.br_param = vr;
2038 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
2041 TAILQ_INIT(&pr->iobhd);
2045 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2047 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2048 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2049 struct ahci_port *p = &sc->port[port];
2051 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
2052 port, offset, value);
2072 p->ie = value & 0xFDC000FF;
2077 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2078 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2079 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2080 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK);
2081 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2082 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2083 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2084 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value;
2086 if (!(value & AHCI_P_CMD_ST)) {
2091 p->cmd |= AHCI_P_CMD_CR;
2092 clb = (uint64_t)p->clbu << 32 | p->clb;
2093 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
2094 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
2097 if (value & AHCI_P_CMD_FRE) {
2100 p->cmd |= AHCI_P_CMD_FR;
2101 fb = (uint64_t)p->fbu << 32 | p->fb;
2102 /* we don't support FBSCP, so rfis size is 256Bytes */
2103 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
2105 p->cmd &= ~AHCI_P_CMD_FR;
2108 if (value & AHCI_P_CMD_CLO) {
2109 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ);
2110 p->cmd &= ~AHCI_P_CMD_CLO;
2113 if (value & AHCI_P_CMD_ICC_MASK) {
2114 p->cmd &= ~AHCI_P_CMD_ICC_MASK;
2117 ahci_handle_port(p);
2123 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
2127 if (!(p->cmd & AHCI_P_CMD_ST)) {
2128 if (value & ATA_SC_DET_RESET)
2140 ahci_handle_port(p);
2150 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2152 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
2160 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
2163 if (value & AHCI_GHC_HR) {
2167 if (value & AHCI_GHC_IE)
2168 sc->ghc |= AHCI_GHC_IE;
2170 sc->ghc &= ~AHCI_GHC_IE;
2171 ahci_generate_intr(sc, 0xffffffff);
2175 ahci_generate_intr(sc, value);
2183 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
2184 int baridx, uint64_t offset, int size, uint64_t value)
2186 struct pci_ahci_softc *sc = pi->pi_arg;
2188 assert(baridx == 5);
2189 assert((offset % 4) == 0 && size == 4);
2191 pthread_mutex_lock(&sc->mtx);
2193 if (offset < AHCI_OFFSET)
2194 pci_ahci_host_write(sc, offset, value);
2195 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2196 pci_ahci_port_write(sc, offset, value);
2198 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
2200 pthread_mutex_unlock(&sc->mtx);
2204 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2220 uint32_t *p = &sc->cap;
2221 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2229 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
2236 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2239 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2240 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2260 uint32_t *p= &sc->port[port].clb;
2261 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2270 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
2271 port, offset, value);
2277 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2278 uint64_t regoff, int size)
2280 struct pci_ahci_softc *sc = pi->pi_arg;
2284 assert(baridx == 5);
2285 assert(size == 1 || size == 2 || size == 4);
2286 assert((regoff & (size - 1)) == 0);
2288 pthread_mutex_lock(&sc->mtx);
2290 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */
2291 if (offset < AHCI_OFFSET)
2292 value = pci_ahci_host_read(sc, offset);
2293 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2294 value = pci_ahci_port_read(sc, offset);
2297 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n",
2300 value >>= 8 * (regoff & 0x3);
2302 pthread_mutex_unlock(&sc->mtx);
2308 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2310 char bident[sizeof("XX:XX:XX")];
2311 struct blockif_ctxt *bctxt;
2312 struct pci_ahci_softc *sc;
2321 dbg = fopen("/tmp/log", "w+");
2324 sc = calloc(1, sizeof(struct pci_ahci_softc));
2327 pthread_mutex_init(&sc->mtx, NULL);
2332 for (p = 0; p < MAX_PORTS && opts != NULL; p++, opts = next) {
2333 /* Identify and cut off type of present port. */
2334 if (strncmp(opts, "hd:", 3) == 0) {
2337 } else if (strncmp(opts, "cd:", 3) == 0) {
2342 /* Find and cut off the next port options. */
2343 next = strstr(opts, ",hd:");
2344 next2 = strstr(opts, ",cd:");
2345 if (next == NULL || (next2 != NULL && next2 < next))
2356 * Attempt to open the backing image. Use the PCI slot/func
2357 * and the port number for the identifier string.
2359 snprintf(bident, sizeof(bident), "%d:%d:%d", pi->pi_slot,
2361 bctxt = blockif_open(opts, bident);
2362 if (bctxt == NULL) {
2367 sc->port[p].bctx = bctxt;
2368 sc->port[p].pr_sc = sc;
2369 sc->port[p].port = p;
2370 sc->port[p].atapi = atapi;
2373 * Create an identifier for the backing file.
2374 * Use parts of the md5 sum of the filename
2377 MD5Update(&mdctx, opts, strlen(opts));
2378 MD5Final(digest, &mdctx);
2379 snprintf(sc->port[p].ident, AHCI_PORT_IDENT,
2380 "BHYVE-%02X%02X-%02X%02X-%02X%02X",
2381 digest[0], digest[1], digest[2], digest[3], digest[4],
2385 * Allocate blockif request structures and add them
2388 pci_ahci_ioreq_init(&sc->port[p]);
2391 if (sc->port[p].ioqsz < slots)
2392 slots = sc->port[p].ioqsz;
2396 /* Intel ICH8 AHCI */
2398 if (sc->ports < DEF_PORTS)
2399 sc->ports = DEF_PORTS;
2400 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2401 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2402 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2403 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2404 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2407 sc->cap2 = AHCI_CAP2_APST;
2410 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2411 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2412 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2413 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2414 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2415 p = MIN(sc->ports, 16);
2416 p = flsl(p) - ((p & (p - 1)) ? 0 : 1);
2417 pci_emul_add_msicap(pi, 1 << p);
2418 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2419 AHCI_OFFSET + sc->ports * AHCI_STEP);
2421 pci_lintr_request(pi);
2425 for (p = 0; p < sc->ports; p++) {
2426 if (sc->port[p].bctx != NULL)
2427 blockif_close(sc->port[p].bctx);
2436 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2439 return (pci_ahci_init(ctx, pi, opts, 0));
2443 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2446 return (pci_ahci_init(ctx, pi, opts, 1));
2450 * Use separate emulation names to distinguish drive and atapi devices
2452 struct pci_devemu pci_de_ahci = {
2454 .pe_init = pci_ahci_hd_init,
2455 .pe_barwrite = pci_ahci_write,
2456 .pe_barread = pci_ahci_read
2458 PCI_EMUL_SET(pci_de_ahci);
2460 struct pci_devemu pci_de_ahci_hd = {
2461 .pe_emu = "ahci-hd",
2462 .pe_init = pci_ahci_hd_init,
2463 .pe_barwrite = pci_ahci_write,
2464 .pe_barread = pci_ahci_read
2466 PCI_EMUL_SET(pci_de_ahci_hd);
2468 struct pci_devemu pci_de_ahci_cd = {
2469 .pe_emu = "ahci-cd",
2470 .pe_init = pci_ahci_atapi_init,
2471 .pe_barwrite = pci_ahci_write,
2472 .pe_barread = pci_ahci_read
2474 PCI_EMUL_SET(pci_de_ahci_cd);