2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/linker_set.h>
39 #include <sys/ioctl.h>
42 #include <sys/endian.h>
44 #include <machine/vmm_snapshot.h>
56 #include <pthread_np.h>
67 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
68 #define MAX_PORTS 32 /* AHCI supports 32 ports */
70 #define PxSIG_ATA 0x00000101 /* ATA drive */
71 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
74 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
75 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
76 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
77 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
78 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
79 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
80 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
81 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
87 #define TEST_UNIT_READY 0x00
88 #define REQUEST_SENSE 0x03
90 #define START_STOP_UNIT 0x1B
91 #define PREVENT_ALLOW 0x1E
92 #define READ_CAPACITY 0x25
94 #define POSITION_TO_ELEMENT 0x2B
96 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
97 #define MODE_SENSE_10 0x5A
98 #define REPORT_LUNS 0xA0
103 * SCSI mode page codes
105 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
106 #define MODEPAGE_CD_CAPABILITIES 0x2A
111 #define ATA_SF_ENAB_SATA_SF 0x10
112 #define ATA_SATA_SF_AN 0x05
113 #define ATA_SF_DIS_SATA_SF 0x90
120 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
122 #define DPRINTF(format, arg...)
124 #define WPRINTF(format, arg...) printf(format, ##arg)
126 #define AHCI_PORT_IDENT 20 + 1
129 struct blockif_req io_req;
130 struct ahci_port *io_pr;
131 STAILQ_ENTRY(ahci_ioreq) io_flist;
132 TAILQ_ENTRY(ahci_ioreq) io_blist;
142 struct blockif_ctxt *bctx;
143 struct pci_ahci_softc *pr_sc;
144 struct ata_params ata_ident;
153 uint8_t err_cfis[20];
180 struct ahci_ioreq *ioreq;
182 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
183 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
186 struct ahci_cmd_hdr {
191 uint32_t reserved[4];
194 struct ahci_prdt_entry {
197 #define DBCMASK 0x3fffff
201 struct pci_ahci_softc {
202 struct pci_devinst *asc_pi;
217 struct ahci_port port[MAX_PORTS];
219 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
221 static void ahci_handle_port(struct ahci_port *p);
223 static inline void lba_to_msf(uint8_t *buf, int lba)
226 buf[0] = (lba / 75) / 60;
227 buf[1] = (lba / 75) % 60;
232 * Generate HBA interrupts on global IS register write.
235 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask)
237 struct pci_devinst *pi = sc->asc_pi;
242 /* Update global IS from PxIS/PxIE. */
243 for (i = 0; i < sc->ports; i++) {
248 DPRINTF("%s(%08x) %08x", __func__, mask, sc->is);
250 /* If there is nothing enabled -- clear legacy interrupt and exit. */
251 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) {
253 pci_lintr_deassert(pi);
259 /* If there is anything and no MSI -- assert legacy interrupt. */
260 nmsg = pci_msi_maxmsgnum(pi);
264 pci_lintr_assert(pi);
269 /* Assert respective MSIs for ports that were touched. */
270 for (i = 0; i < nmsg; i++) {
271 if (sc->ports <= nmsg || i < nmsg - 1)
274 mmask = 0xffffffff << i;
275 if (sc->is & mask && mmask & mask)
276 pci_generate_msi(pi, i);
281 * Generate HBA interrupt on specific port event.
284 ahci_port_intr(struct ahci_port *p)
286 struct pci_ahci_softc *sc = p->pr_sc;
287 struct pci_devinst *pi = sc->asc_pi;
290 DPRINTF("%s(%d) %08x/%08x %08x", __func__,
291 p->port, p->is, p->ie, sc->is);
293 /* If there is nothing enabled -- we are done. */
294 if ((p->is & p->ie) == 0)
297 /* In case of non-shared MSI always generate interrupt. */
298 nmsg = pci_msi_maxmsgnum(pi);
299 if (sc->ports <= nmsg || p->port < nmsg - 1) {
300 sc->is |= (1 << p->port);
301 if ((sc->ghc & AHCI_GHC_IE) == 0)
303 pci_generate_msi(pi, p->port);
307 /* If IS for this port is already set -- do nothing. */
308 if (sc->is & (1 << p->port))
311 sc->is |= (1 << p->port);
313 /* If interrupts are enabled -- generate one. */
314 if ((sc->ghc & AHCI_GHC_IE) == 0)
317 pci_generate_msi(pi, nmsg - 1);
318 } else if (!sc->lintr) {
320 pci_lintr_assert(pi);
325 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
327 int offset, len, irq;
329 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
333 case FIS_TYPE_REGD2H:
336 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0;
338 case FIS_TYPE_SETDEVBITS:
341 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0;
343 case FIS_TYPE_PIOSETUP:
346 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
349 WPRINTF("unsupported fis type %d", ft);
352 if (fis[2] & ATA_S_ERROR) {
354 irq |= AHCI_P_IX_TFE;
356 memcpy(p->rfis + offset, fis, len);
366 ahci_write_fis_piosetup(struct ahci_port *p)
370 memset(fis, 0, sizeof(fis));
371 fis[0] = FIS_TYPE_PIOSETUP;
372 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
376 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
381 error = (tfd >> 8) & 0xff;
383 memset(fis, 0, sizeof(fis));
384 fis[0] = FIS_TYPE_SETDEVBITS;
388 if (fis[2] & ATA_S_ERROR) {
389 p->err_cfis[0] = slot;
390 p->err_cfis[2] = tfd;
391 p->err_cfis[3] = error;
392 memcpy(&p->err_cfis[4], cfis + 4, 16);
394 *(uint32_t *)(fis + 4) = (1 << slot);
395 p->sact &= ~(1 << slot);
399 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
403 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
408 error = (tfd >> 8) & 0xff;
409 memset(fis, 0, sizeof(fis));
410 fis[0] = FIS_TYPE_REGD2H;
424 if (fis[2] & ATA_S_ERROR) {
425 p->err_cfis[0] = 0x80;
426 p->err_cfis[2] = tfd & 0xff;
427 p->err_cfis[3] = error;
428 memcpy(&p->err_cfis[4], cfis + 4, 16);
430 p->ci &= ~(1 << slot);
432 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
436 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot)
440 p->tfd = ATA_S_READY | ATA_S_DSC;
441 memset(fis, 0, sizeof(fis));
442 fis[0] = FIS_TYPE_REGD2H;
443 fis[1] = 0; /* No interrupt */
444 fis[2] = p->tfd; /* Status */
445 fis[3] = 0; /* No error */
446 p->ci &= ~(1 << slot);
447 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
451 ahci_write_reset_fis_d2h(struct ahci_port *p)
455 memset(fis, 0, sizeof(fis));
456 fis[0] = FIS_TYPE_REGD2H;
464 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
468 ahci_check_stopped(struct ahci_port *p)
471 * If we are no longer processing the command list and nothing
472 * is in-flight, clear the running bit, the current command
473 * slot, the command issue and active bits.
475 if (!(p->cmd & AHCI_P_CMD_ST)) {
476 if (p->pending == 0) {
478 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
487 ahci_port_stop(struct ahci_port *p)
489 struct ahci_ioreq *aior;
494 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
496 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
498 * Try to cancel the outstanding blockif request.
500 error = blockif_cancel(p->bctx, &aior->io_req);
506 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
507 cfis[2] == ATA_READ_FPDMA_QUEUED ||
508 cfis[2] == ATA_SEND_FPDMA_QUEUED)
509 p->sact &= ~(1 << slot); /* NCQ */
511 p->ci &= ~(1 << slot);
514 * This command is now done.
516 p->pending &= ~(1 << slot);
519 * Delete the blockif request from the busy list
521 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
524 * Move the blockif request back to the free list
526 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
529 ahci_check_stopped(p);
533 ahci_port_reset(struct ahci_port *pr)
537 pr->xfermode = ATA_UDMA6;
538 pr->mult_sectors = 128;
541 pr->ssts = ATA_SS_DET_NO_DEVICE;
542 pr->sig = 0xFFFFFFFF;
546 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
547 if (pr->sctl & ATA_SC_SPD_MASK)
548 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
550 pr->ssts |= ATA_SS_SPD_GEN3;
551 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
554 pr->tfd |= ATA_S_READY;
556 pr->sig = PxSIG_ATAPI;
557 ahci_write_reset_fis_d2h(pr);
561 ahci_reset(struct pci_ahci_softc *sc)
565 sc->ghc = AHCI_GHC_AE;
569 pci_lintr_deassert(sc->asc_pi);
573 for (i = 0; i < sc->ports; i++) {
576 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD);
577 if (sc->port[i].bctx)
578 sc->port[i].cmd |= AHCI_P_CMD_CPS;
579 sc->port[i].sctl = 0;
580 ahci_port_reset(&sc->port[i]);
585 ata_string(uint8_t *dest, const char *src, int len)
589 for (i = 0; i < len; i++) {
591 dest[i ^ 1] = *src++;
598 atapi_string(uint8_t *dest, const char *src, int len)
602 for (i = 0; i < len; i++) {
611 * Build up the iovec based on the PRDT, 'done' and 'len'.
614 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior,
615 struct ahci_prdt_entry *prdt, uint16_t prdtl)
617 struct blockif_req *breq = &aior->io_req;
618 int i, j, skip, todo, left, extra;
621 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */
623 left = aior->len - aior->done;
625 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0;
627 dbcsz = (prdt->dbc & DBCMASK) + 1;
628 /* Skip already done part of the PRDT */
636 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc),
637 prdt->dba + skip, dbcsz);
638 breq->br_iov[j].iov_len = dbcsz;
645 /* If we got limited by IOV length, round I/O down to sector size. */
646 if (j == BLOCKIF_IOV_MAX) {
647 extra = todo % blockif_sectsz(p->bctx);
651 if (breq->br_iov[j - 1].iov_len > extra) {
652 breq->br_iov[j - 1].iov_len -= extra;
655 extra -= breq->br_iov[j - 1].iov_len;
661 breq->br_resid = todo;
663 aior->more = (aior->done < aior->len && i < prdtl);
667 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
669 struct ahci_ioreq *aior;
670 struct blockif_req *breq;
671 struct ahci_prdt_entry *prdt;
672 struct ahci_cmd_hdr *hdr;
675 int err, first, ncq, readop;
677 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
678 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
683 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
684 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
685 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
686 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
689 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
690 cfis[2] == ATA_READ_FPDMA_QUEUED) {
691 lba = ((uint64_t)cfis[10] << 40) |
692 ((uint64_t)cfis[9] << 32) |
693 ((uint64_t)cfis[8] << 24) |
694 ((uint64_t)cfis[6] << 16) |
695 ((uint64_t)cfis[5] << 8) |
697 len = cfis[11] << 8 | cfis[3];
701 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
702 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
703 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
704 lba = ((uint64_t)cfis[10] << 40) |
705 ((uint64_t)cfis[9] << 32) |
706 ((uint64_t)cfis[8] << 24) |
707 ((uint64_t)cfis[6] << 16) |
708 ((uint64_t)cfis[5] << 8) |
710 len = cfis[13] << 8 | cfis[12];
714 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
715 (cfis[5] << 8) | cfis[4];
720 lba *= blockif_sectsz(p->bctx);
721 len *= blockif_sectsz(p->bctx);
723 /* Pull request off free list */
724 aior = STAILQ_FIRST(&p->iofhd);
725 assert(aior != NULL);
726 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
732 aior->readop = readop;
733 breq = &aior->io_req;
734 breq->br_offset = lba + done;
735 ahci_build_iov(p, aior, prdt, hdr->prdtl);
737 /* Mark this command in-flight. */
738 p->pending |= 1 << slot;
740 /* Stuff request onto busy list. */
741 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
744 ahci_write_fis_d2h_ncq(p, slot);
747 err = blockif_read(p->bctx, breq);
749 err = blockif_write(p->bctx, breq);
754 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
756 struct ahci_ioreq *aior;
757 struct blockif_req *breq;
761 * Pull request off free list
763 aior = STAILQ_FIRST(&p->iofhd);
764 assert(aior != NULL);
765 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
771 breq = &aior->io_req;
774 * Mark this command in-flight.
776 p->pending |= 1 << slot;
779 * Stuff request onto busy list
781 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
783 err = blockif_flush(p->bctx, breq);
788 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf, int size)
790 struct ahci_cmd_hdr *hdr;
791 struct ahci_prdt_entry *prdt;
795 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
798 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
799 for (i = 0; i < hdr->prdtl && len; i++) {
804 dbcsz = (prdt->dbc & DBCMASK) + 1;
805 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
806 sublen = MIN(len, dbcsz);
807 memcpy(to, ptr, sublen);
815 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
817 struct ahci_ioreq *aior;
818 struct blockif_req *breq;
826 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
827 len = (uint16_t)cfis[13] << 8 | cfis[12];
830 } else { /* ATA_SEND_FPDMA_QUEUED */
831 len = (uint16_t)cfis[11] << 8 | cfis[3];
835 read_prdt(p, slot, cfis, buf, sizeof(buf));
839 elba = ((uint64_t)entry[5] << 40) |
840 ((uint64_t)entry[4] << 32) |
841 ((uint64_t)entry[3] << 24) |
842 ((uint64_t)entry[2] << 16) |
843 ((uint64_t)entry[1] << 8) |
845 elen = (uint16_t)entry[7] << 8 | entry[6];
851 ahci_write_fis_d2h_ncq(p, slot);
852 ahci_write_fis_sdb(p, slot, cfis,
853 ATA_S_READY | ATA_S_DSC);
855 ahci_write_fis_d2h(p, slot, cfis,
856 ATA_S_READY | ATA_S_DSC);
858 p->pending &= ~(1 << slot);
859 ahci_check_stopped(p);
868 * Pull request off free list
870 aior = STAILQ_FIRST(&p->iofhd);
871 assert(aior != NULL);
872 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
877 aior->more = (len != done);
879 breq = &aior->io_req;
880 breq->br_offset = elba * blockif_sectsz(p->bctx);
881 breq->br_resid = elen * blockif_sectsz(p->bctx);
884 * Mark this command in-flight.
886 p->pending |= 1 << slot;
889 * Stuff request onto busy list
891 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
894 ahci_write_fis_d2h_ncq(p, slot);
896 err = blockif_delete(p->bctx, breq);
901 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf, int size)
903 struct ahci_cmd_hdr *hdr;
904 struct ahci_prdt_entry *prdt;
908 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
911 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
912 for (i = 0; i < hdr->prdtl && len; i++) {
917 dbcsz = (prdt->dbc & DBCMASK) + 1;
918 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
919 sublen = MIN(len, dbcsz);
920 memcpy(ptr, from, sublen);
925 hdr->prdbc = size - len;
929 ahci_checksum(uint8_t *buf, int size)
934 for (i = 0; i < size - 1; i++)
936 buf[size - 1] = 0x100 - sum;
940 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
942 struct ahci_cmd_hdr *hdr;
944 uint8_t *buf8 = (uint8_t *)buf;
945 uint16_t *buf16 = (uint16_t *)buf;
947 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
948 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 ||
949 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
950 ahci_write_fis_d2h(p, slot, cfis,
951 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
955 memset(buf, 0, sizeof(buf));
956 if (cfis[4] == 0x00) { /* Log directory */
957 buf16[0x00] = 1; /* Version -- 1 */
958 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */
959 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */
960 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */
961 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis));
962 ahci_checksum(buf8, sizeof(buf));
963 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */
964 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) {
965 buf[0x00] = 1; /* SFQ DSM supported */
966 buf[0x01] = 1; /* SFQ DSM TRIM supported */
969 ahci_write_fis_d2h(p, slot, cfis,
970 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
974 if (cfis[2] == ATA_READ_LOG_EXT)
975 ahci_write_fis_piosetup(p);
976 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
977 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
981 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
983 struct ahci_cmd_hdr *hdr;
985 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
986 if (p->atapi || hdr->prdtl == 0) {
987 ahci_write_fis_d2h(p, slot, cfis,
988 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
990 ahci_write_fis_piosetup(p);
991 write_prdt(p, slot, cfis, (void*)&p->ata_ident, sizeof(struct ata_params));
992 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
997 ata_identify_init(struct ahci_port* p, int atapi)
999 struct ata_params* ata_ident = &p->ata_ident;
1002 ata_ident->config = ATA_PROTO_ATAPI | ATA_ATAPI_TYPE_CDROM |
1003 ATA_ATAPI_REMOVABLE | ATA_DRQ_FAST;
1004 ata_ident->capabilities1 = ATA_SUPPORT_LBA |
1006 ata_ident->capabilities2 = (1 << 14 | 1);
1007 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1008 ata_ident->obsolete62 = 0x3f;
1009 ata_ident->mwdmamodes = 7;
1010 if (p->xfermode & ATA_WDMA0)
1011 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1012 ata_ident->apiomodes = 3;
1013 ata_ident->mwdmamin = 0x0078;
1014 ata_ident->mwdmarec = 0x0078;
1015 ata_ident->pioblind = 0x0078;
1016 ata_ident->pioiordy = 0x0078;
1017 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
1018 ata_ident->satacapabilities2 = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
1019 ata_ident->satasupport = ATA_SUPPORT_NCQ_STREAM;
1020 ata_ident->version_major = 0x3f0;
1021 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1022 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1023 ata_ident->support.command2 = (1 << 14);
1024 ata_ident->support.extension = (1 << 14);
1025 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1026 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1027 ata_ident->enabled.extension = (1 << 14);
1028 ata_ident->udmamodes = 0x7f;
1029 if (p->xfermode & ATA_UDMA0)
1030 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1031 ata_ident->transport_major = 0x1020;
1032 ata_ident->integrity = 0x00a5;
1035 int sectsz, psectsz, psectoff, candelete, ro;
1037 uint8_t sech, heads;
1039 ro = blockif_is_ro(p->bctx);
1040 candelete = blockif_candelete(p->bctx);
1041 sectsz = blockif_sectsz(p->bctx);
1042 sectors = blockif_size(p->bctx) / sectsz;
1043 blockif_chs(p->bctx, &cyl, &heads, &sech);
1044 blockif_psectsz(p->bctx, &psectsz, &psectoff);
1045 ata_ident->config = ATA_DRQ_FAST;
1046 ata_ident->cylinders = cyl;
1047 ata_ident->heads = heads;
1048 ata_ident->sectors = sech;
1050 ata_ident->sectors_intr = (0x8000 | 128);
1053 ata_ident->capabilities1 = ATA_SUPPORT_DMA |
1054 ATA_SUPPORT_LBA | ATA_SUPPORT_IORDY;
1055 ata_ident->capabilities2 = (1 << 14);
1056 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1057 if (p->mult_sectors)
1058 ata_ident->multi = (ATA_MULTI_VALID | p->mult_sectors);
1059 if (sectors <= 0x0fffffff) {
1060 ata_ident->lba_size_1 = sectors;
1061 ata_ident->lba_size_2 = (sectors >> 16);
1063 ata_ident->lba_size_1 = 0xffff;
1064 ata_ident->lba_size_2 = 0x0fff;
1066 ata_ident->mwdmamodes = 0x7;
1067 if (p->xfermode & ATA_WDMA0)
1068 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1069 ata_ident->apiomodes = 0x3;
1070 ata_ident->mwdmamin = 0x0078;
1071 ata_ident->mwdmarec = 0x0078;
1072 ata_ident->pioblind = 0x0078;
1073 ata_ident->pioiordy = 0x0078;
1074 ata_ident->support3 = 0;
1075 ata_ident->queue = 31;
1076 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
1078 ata_ident->satacapabilities2 = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
1079 (p->ssts & ATA_SS_SPD_MASK) >> 3);
1080 ata_ident->version_major = 0x3f0;
1081 ata_ident->version_minor = 0x28;
1082 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1083 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1084 ata_ident->support.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1085 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
1086 ata_ident->support.extension = (1 << 14);
1087 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1088 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1089 ata_ident->enabled.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1090 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
1091 ata_ident->enabled.extension = (1 << 14);
1092 ata_ident->udmamodes = 0x7f;
1093 if (p->xfermode & ATA_UDMA0)
1094 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1095 ata_ident->lba_size48_1 = sectors;
1096 ata_ident->lba_size48_2 = (sectors >> 16);
1097 ata_ident->lba_size48_3 = (sectors >> 32);
1098 ata_ident->lba_size48_4 = (sectors >> 48);
1100 if (candelete && !ro) {
1101 ata_ident->support3 |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
1102 ata_ident->max_dsm_blocks = 1;
1103 ata_ident->support_dsm = ATA_SUPPORT_DSM_TRIM;
1105 ata_ident->pss = ATA_PSS_VALID_VALUE;
1106 ata_ident->lsalign = 0x4000;
1107 if (psectsz > sectsz) {
1108 ata_ident->pss |= ATA_PSS_MULTLS;
1109 ata_ident->pss |= ffsl(psectsz / sectsz) - 1;
1110 ata_ident->lsalign |= (psectoff / sectsz);
1113 ata_ident->pss |= ATA_PSS_LSSABOVE512;
1114 ata_ident->lss_1 = sectsz / 2;
1115 ata_ident->lss_2 = ((sectsz / 2) >> 16);
1117 ata_ident->support2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1118 ata_ident->enabled2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1119 ata_ident->transport_major = 0x1020;
1120 ata_ident->integrity = 0x00a5;
1122 ahci_checksum((uint8_t*)ata_ident, sizeof(struct ata_params));
1126 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1129 ahci_write_fis_d2h(p, slot, cfis,
1130 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1132 ahci_write_fis_piosetup(p);
1133 write_prdt(p, slot, cfis, (void *)&p->ata_ident, sizeof(struct ata_params));
1134 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1139 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
1148 if (acmd[1] & 1) { /* VPD */
1149 if (acmd[2] == 0) { /* Supported VPD pages */
1157 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1159 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1160 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1161 ahci_write_fis_d2h(p, slot, cfis, tfd);
1173 atapi_string(buf + 8, "BHYVE", 8);
1174 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1175 atapi_string(buf + 32, "001", 4);
1181 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1182 write_prdt(p, slot, cfis, buf, len);
1183 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1187 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1192 sectors = blockif_size(p->bctx) / 2048;
1193 be32enc(buf, sectors - 1);
1194 be32enc(buf + 4, 2048);
1195 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1196 write_prdt(p, slot, cfis, buf, sizeof(buf));
1197 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1201 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1209 len = be16dec(acmd + 7);
1210 format = acmd[9] >> 6;
1216 uint8_t start_track, buf[20], *bp;
1218 msf = (acmd[1] >> 1) & 1;
1219 start_track = acmd[6];
1220 if (start_track > 1 && start_track != 0xaa) {
1222 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1224 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1225 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1226 ahci_write_fis_d2h(p, slot, cfis, tfd);
1232 if (start_track <= 1) {
1252 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1256 lba_to_msf(bp, sectors);
1259 be32enc(bp, sectors);
1263 be16enc(buf, size - 2);
1266 write_prdt(p, slot, cfis, buf, len);
1267 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1268 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1275 memset(buf, 0, sizeof(buf));
1279 if (len > sizeof(buf))
1281 write_prdt(p, slot, cfis, buf, len);
1282 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1283 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1290 uint8_t *bp, buf[50];
1292 msf = (acmd[1] >> 1) & 1;
1328 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1332 lba_to_msf(bp, sectors);
1335 be32enc(bp, sectors);
1358 be16enc(buf, size - 2);
1361 write_prdt(p, slot, cfis, buf, len);
1362 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1363 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1370 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1372 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1373 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1374 ahci_write_fis_d2h(p, slot, cfis, tfd);
1381 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1385 memset(buf, 0, sizeof(buf));
1388 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1389 write_prdt(p, slot, cfis, buf, sizeof(buf));
1390 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1394 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
1396 struct ahci_ioreq *aior;
1397 struct ahci_cmd_hdr *hdr;
1398 struct ahci_prdt_entry *prdt;
1399 struct blockif_req *breq;
1406 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1407 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1409 lba = be32dec(acmd + 2);
1410 if (acmd[0] == READ_10)
1411 len = be16dec(acmd + 7);
1413 len = be32dec(acmd + 6);
1415 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1416 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1422 * Pull request off free list
1424 aior = STAILQ_FIRST(&p->iofhd);
1425 assert(aior != NULL);
1426 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1432 breq = &aior->io_req;
1433 breq->br_offset = lba + done;
1434 ahci_build_iov(p, aior, prdt, hdr->prdtl);
1436 /* Mark this command in-flight. */
1437 p->pending |= 1 << slot;
1439 /* Stuff request onto busy list. */
1440 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1442 err = blockif_read(p->bctx, breq);
1447 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1455 if (len > sizeof(buf))
1457 memset(buf, 0, len);
1458 buf[0] = 0x70 | (1 << 7);
1459 buf[2] = p->sense_key;
1462 write_prdt(p, slot, cfis, buf, len);
1463 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1464 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1468 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1470 uint8_t *acmd = cfis + 0x40;
1473 switch (acmd[4] & 3) {
1477 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1478 tfd = ATA_S_READY | ATA_S_DSC;
1481 /* TODO eject media */
1482 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1483 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1485 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1488 ahci_write_fis_d2h(p, slot, cfis, tfd);
1492 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1500 len = be16dec(acmd + 7);
1502 code = acmd[2] & 0x3f;
1507 case MODEPAGE_RW_ERROR_RECOVERY:
1511 if (len > sizeof(buf))
1514 memset(buf, 0, sizeof(buf));
1515 be16enc(buf, 16 - 2);
1520 write_prdt(p, slot, cfis, buf, len);
1521 tfd = ATA_S_READY | ATA_S_DSC;
1524 case MODEPAGE_CD_CAPABILITIES:
1528 if (len > sizeof(buf))
1531 memset(buf, 0, sizeof(buf));
1532 be16enc(buf, 30 - 2);
1538 be16enc(&buf[18], 2);
1539 be16enc(&buf[20], 512);
1540 write_prdt(p, slot, cfis, buf, len);
1541 tfd = ATA_S_READY | ATA_S_DSC;
1550 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1552 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1557 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1559 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1562 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1563 ahci_write_fis_d2h(p, slot, cfis, tfd);
1567 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1575 /* we don't support asynchronous operation */
1576 if (!(acmd[1] & 1)) {
1577 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1579 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1584 len = be16dec(acmd + 7);
1585 if (len > sizeof(buf))
1588 memset(buf, 0, sizeof(buf));
1589 be16enc(buf, 8 - 2);
1593 write_prdt(p, slot, cfis, buf, len);
1594 tfd = ATA_S_READY | ATA_S_DSC;
1596 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1597 ahci_write_fis_d2h(p, slot, cfis, tfd);
1601 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1611 for (i = 0; i < 16; i++)
1612 DPRINTF("%02x ", acmd[i]);
1618 case TEST_UNIT_READY:
1619 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1620 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1623 atapi_inquiry(p, slot, cfis);
1626 atapi_read_capacity(p, slot, cfis);
1630 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1631 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1634 atapi_read_toc(p, slot, cfis);
1637 atapi_report_luns(p, slot, cfis);
1641 atapi_read(p, slot, cfis, 0);
1644 atapi_request_sense(p, slot, cfis);
1646 case START_STOP_UNIT:
1647 atapi_start_stop_unit(p, slot, cfis);
1650 atapi_mode_sense(p, slot, cfis);
1652 case GET_EVENT_STATUS_NOTIFICATION:
1653 atapi_get_event_status_notification(p, slot, cfis);
1656 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1657 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1659 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1660 ATA_S_READY | ATA_S_ERROR);
1666 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1669 p->tfd |= ATA_S_BUSY;
1671 case ATA_ATA_IDENTIFY:
1672 handle_identify(p, slot, cfis);
1674 case ATA_SETFEATURES:
1677 case ATA_SF_ENAB_SATA_SF:
1679 case ATA_SATA_SF_AN:
1680 p->tfd = ATA_S_DSC | ATA_S_READY;
1683 p->tfd = ATA_S_ERROR | ATA_S_READY;
1684 p->tfd |= (ATA_ERROR_ABORT << 8);
1688 case ATA_SF_ENAB_WCACHE:
1689 case ATA_SF_DIS_WCACHE:
1690 case ATA_SF_ENAB_RCACHE:
1691 case ATA_SF_DIS_RCACHE:
1692 p->tfd = ATA_S_DSC | ATA_S_READY;
1694 case ATA_SF_SETXFER:
1696 switch (cfis[12] & 0xf8) {
1702 p->xfermode = (cfis[12] & 0x7);
1705 p->tfd = ATA_S_DSC | ATA_S_READY;
1709 p->tfd = ATA_S_ERROR | ATA_S_READY;
1710 p->tfd |= (ATA_ERROR_ABORT << 8);
1713 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1717 if (cfis[12] != 0 &&
1718 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1719 p->tfd = ATA_S_ERROR | ATA_S_READY;
1720 p->tfd |= (ATA_ERROR_ABORT << 8);
1722 p->mult_sectors = cfis[12];
1723 p->tfd = ATA_S_DSC | ATA_S_READY;
1725 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1733 case ATA_READ_MUL48:
1734 case ATA_WRITE_MUL48:
1737 case ATA_READ_DMA48:
1738 case ATA_WRITE_DMA48:
1739 case ATA_READ_FPDMA_QUEUED:
1740 case ATA_WRITE_FPDMA_QUEUED:
1741 ahci_handle_rw(p, slot, cfis, 0);
1743 case ATA_FLUSHCACHE:
1744 case ATA_FLUSHCACHE48:
1745 ahci_handle_flush(p, slot, cfis);
1747 case ATA_DATA_SET_MANAGEMENT:
1748 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1749 cfis[13] == 0 && cfis[12] == 1) {
1750 ahci_handle_dsm_trim(p, slot, cfis, 0);
1753 ahci_write_fis_d2h(p, slot, cfis,
1754 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1756 case ATA_SEND_FPDMA_QUEUED:
1757 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1758 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1759 cfis[11] == 0 && cfis[3] == 1) {
1760 ahci_handle_dsm_trim(p, slot, cfis, 0);
1763 ahci_write_fis_d2h(p, slot, cfis,
1764 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1766 case ATA_READ_LOG_EXT:
1767 case ATA_READ_LOG_DMA_EXT:
1768 ahci_handle_read_log(p, slot, cfis);
1770 case ATA_SECURITY_FREEZE_LOCK:
1773 ahci_write_fis_d2h(p, slot, cfis,
1774 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1776 case ATA_CHECK_POWER_MODE:
1777 cfis[12] = 0xff; /* always on */
1778 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1780 case ATA_STANDBY_CMD:
1781 case ATA_STANDBY_IMMEDIATE:
1783 case ATA_IDLE_IMMEDIATE:
1785 case ATA_READ_VERIFY:
1786 case ATA_READ_VERIFY48:
1787 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1789 case ATA_ATAPI_IDENTIFY:
1790 handle_atapi_identify(p, slot, cfis);
1792 case ATA_PACKET_CMD:
1794 ahci_write_fis_d2h(p, slot, cfis,
1795 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1797 handle_packet_cmd(p, slot, cfis);
1800 WPRINTF("Unsupported cmd:%02x", cfis[2]);
1801 ahci_write_fis_d2h(p, slot, cfis,
1802 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1808 ahci_handle_slot(struct ahci_port *p, int slot)
1810 struct ahci_cmd_hdr *hdr;
1812 struct ahci_prdt_entry *prdt;
1814 struct pci_ahci_softc *sc;
1821 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1823 cfl = (hdr->flags & 0x1f) * 4;
1825 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1826 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1828 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1831 for (i = 0; i < cfl; i++) {
1834 DPRINTF("%02x ", cfis[i]);
1838 for (i = 0; i < hdr->prdtl; i++) {
1839 DPRINTF("%d@%08"PRIx64"", prdt->dbc & 0x3fffff, prdt->dba);
1844 if (cfis[0] != FIS_TYPE_REGH2D) {
1845 WPRINTF("Not a H2D FIS:%02x", cfis[0]);
1849 if (cfis[1] & 0x80) {
1850 ahci_handle_cmd(p, slot, cfis);
1852 if (cfis[15] & (1 << 2))
1854 else if (p->reset) {
1858 p->ci &= ~(1 << slot);
1863 ahci_handle_port(struct ahci_port *p)
1866 if (!(p->cmd & AHCI_P_CMD_ST))
1870 * Search for any new commands to issue ignoring those that
1871 * are already in-flight. Stop if device is busy or in error.
1873 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) {
1874 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0)
1876 if (p->waitforclear)
1878 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) {
1879 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1880 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT;
1881 ahci_handle_slot(p, p->ccs);
1887 * blockif callback routine - this runs in the context of the blockif
1888 * i/o thread, so the mutex needs to be acquired.
1891 ata_ioreq_cb(struct blockif_req *br, int err)
1893 struct ahci_cmd_hdr *hdr;
1894 struct ahci_ioreq *aior;
1895 struct ahci_port *p;
1896 struct pci_ahci_softc *sc;
1901 DPRINTF("%s %d", __func__, err);
1904 aior = br->br_param;
1909 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1911 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1912 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1913 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1915 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1916 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1917 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1920 pthread_mutex_lock(&sc->mtx);
1923 * Delete the blockif request from the busy list
1925 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1928 * Move the blockif request back to the free list
1930 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1933 hdr->prdbc = aior->done;
1935 if (!err && aior->more) {
1937 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1939 ahci_handle_rw(p, slot, cfis, aior->done);
1944 tfd = ATA_S_READY | ATA_S_DSC;
1946 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1948 ahci_write_fis_sdb(p, slot, cfis, tfd);
1950 ahci_write_fis_d2h(p, slot, cfis, tfd);
1953 * This command is now complete.
1955 p->pending &= ~(1 << slot);
1957 ahci_check_stopped(p);
1958 ahci_handle_port(p);
1960 pthread_mutex_unlock(&sc->mtx);
1961 DPRINTF("%s exit", __func__);
1965 atapi_ioreq_cb(struct blockif_req *br, int err)
1967 struct ahci_cmd_hdr *hdr;
1968 struct ahci_ioreq *aior;
1969 struct ahci_port *p;
1970 struct pci_ahci_softc *sc;
1975 DPRINTF("%s %d", __func__, err);
1977 aior = br->br_param;
1982 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1984 pthread_mutex_lock(&sc->mtx);
1987 * Delete the blockif request from the busy list
1989 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1992 * Move the blockif request back to the free list
1994 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1997 hdr->prdbc = aior->done;
1999 if (!err && aior->more) {
2000 atapi_read(p, slot, cfis, aior->done);
2005 tfd = ATA_S_READY | ATA_S_DSC;
2007 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
2009 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
2011 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
2012 ahci_write_fis_d2h(p, slot, cfis, tfd);
2015 * This command is now complete.
2017 p->pending &= ~(1 << slot);
2019 ahci_check_stopped(p);
2020 ahci_handle_port(p);
2022 pthread_mutex_unlock(&sc->mtx);
2023 DPRINTF("%s exit", __func__);
2027 pci_ahci_ioreq_init(struct ahci_port *pr)
2029 struct ahci_ioreq *vr;
2032 pr->ioqsz = blockif_queuesz(pr->bctx);
2033 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
2034 STAILQ_INIT(&pr->iofhd);
2037 * Add all i/o request entries to the free queue
2039 for (i = 0; i < pr->ioqsz; i++) {
2043 vr->io_req.br_callback = ata_ioreq_cb;
2045 vr->io_req.br_callback = atapi_ioreq_cb;
2046 vr->io_req.br_param = vr;
2047 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
2050 TAILQ_INIT(&pr->iobhd);
2054 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2056 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2057 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2058 struct ahci_port *p = &sc->port[port];
2060 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2061 port, offset, value);
2081 p->ie = value & 0xFDC000FF;
2086 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2087 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2088 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2089 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK);
2090 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2091 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2092 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2093 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value;
2095 if (!(value & AHCI_P_CMD_ST)) {
2100 p->cmd |= AHCI_P_CMD_CR;
2101 clb = (uint64_t)p->clbu << 32 | p->clb;
2102 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
2103 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
2106 if (value & AHCI_P_CMD_FRE) {
2109 p->cmd |= AHCI_P_CMD_FR;
2110 fb = (uint64_t)p->fbu << 32 | p->fb;
2111 /* we don't support FBSCP, so rfis size is 256Bytes */
2112 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
2114 p->cmd &= ~AHCI_P_CMD_FR;
2117 if (value & AHCI_P_CMD_CLO) {
2118 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ);
2119 p->cmd &= ~AHCI_P_CMD_CLO;
2122 if (value & AHCI_P_CMD_ICC_MASK) {
2123 p->cmd &= ~AHCI_P_CMD_ICC_MASK;
2126 ahci_handle_port(p);
2132 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"", offset);
2136 if (!(p->cmd & AHCI_P_CMD_ST)) {
2137 if (value & ATA_SC_DET_RESET)
2149 ahci_handle_port(p);
2159 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2161 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2169 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"", offset);
2172 if (value & AHCI_GHC_HR) {
2176 if (value & AHCI_GHC_IE)
2177 sc->ghc |= AHCI_GHC_IE;
2179 sc->ghc &= ~AHCI_GHC_IE;
2180 ahci_generate_intr(sc, 0xffffffff);
2184 ahci_generate_intr(sc, value);
2192 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
2193 int baridx, uint64_t offset, int size, uint64_t value)
2195 struct pci_ahci_softc *sc = pi->pi_arg;
2197 assert(baridx == 5);
2198 assert((offset % 4) == 0 && size == 4);
2200 pthread_mutex_lock(&sc->mtx);
2202 if (offset < AHCI_OFFSET)
2203 pci_ahci_host_write(sc, offset, value);
2204 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2205 pci_ahci_port_write(sc, offset, value);
2207 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"", offset);
2209 pthread_mutex_unlock(&sc->mtx);
2213 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2229 uint32_t *p = &sc->cap;
2230 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2238 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x",
2245 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2248 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2249 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2269 uint32_t *p= &sc->port[port].clb;
2270 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2279 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x",
2280 port, offset, value);
2286 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2287 uint64_t regoff, int size)
2289 struct pci_ahci_softc *sc = pi->pi_arg;
2293 assert(baridx == 5);
2294 assert(size == 1 || size == 2 || size == 4);
2295 assert((regoff & (size - 1)) == 0);
2297 pthread_mutex_lock(&sc->mtx);
2299 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */
2300 if (offset < AHCI_OFFSET)
2301 value = pci_ahci_host_read(sc, offset);
2302 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2303 value = pci_ahci_port_read(sc, offset);
2306 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"",
2309 value >>= 8 * (regoff & 0x3);
2311 pthread_mutex_unlock(&sc->mtx);
2317 * Each AHCI controller has a "port" node which contains nodes for
2318 * each port named after the decimal number of the port (no leading
2319 * zeroes). Port nodes contain a "type" ("hd" or "cd"), as well as
2320 * options for blockif. For example:
2327 * .path="/path/to/image"
2330 pci_ahci_legacy_config_port(nvlist_t *nvl, int port, const char *type,
2333 char node_name[sizeof("XX")];
2336 snprintf(node_name, sizeof(node_name), "%d", port);
2337 port_nvl = create_relative_config_node(nvl, node_name);
2338 set_config_value_node(port_nvl, "type", type);
2339 return (blockif_legacy_config(port_nvl, opts));
2343 pci_ahci_legacy_config(nvlist_t *nvl, const char *opts)
2345 nvlist_t *ports_nvl;
2347 char *next, *next2, *str, *tofree;
2353 ports_nvl = create_relative_config_node(nvl, "port");
2355 tofree = str = strdup(opts);
2356 for (p = 0; p < MAX_PORTS && str != NULL; p++, str = next) {
2357 /* Identify and cut off type of present port. */
2358 if (strncmp(str, "hd:", 3) == 0) {
2361 } else if (strncmp(str, "cd:", 3) == 0) {
2367 /* Find and cut off the next port options. */
2368 next = strstr(str, ",hd:");
2369 next2 = strstr(str, ",cd:");
2370 if (next == NULL || (next2 != NULL && next2 < next))
2381 EPRINTLN("Missing or invalid type for port %d: \"%s\"",
2386 if (pci_ahci_legacy_config_port(ports_nvl, p, type, str) != 0)
2396 pci_ahci_cd_legacy_config(nvlist_t *nvl, const char *opts)
2398 nvlist_t *ports_nvl;
2400 ports_nvl = create_relative_config_node(nvl, "port");
2401 return (pci_ahci_legacy_config_port(ports_nvl, 0, "cd", opts));
2405 pci_ahci_hd_legacy_config(nvlist_t *nvl, const char *opts)
2407 nvlist_t *ports_nvl;
2409 ports_nvl = create_relative_config_node(nvl, "port");
2410 return (pci_ahci_legacy_config_port(ports_nvl, 0, "hd", opts));
2414 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
2416 char bident[sizeof("XX:XX:XX")];
2417 char node_name[sizeof("XX")];
2418 struct blockif_ctxt *bctxt;
2419 struct pci_ahci_softc *sc;
2420 int atapi, ret, slots, p;
2423 const char *path, *type, *value;
2424 nvlist_t *ports_nvl, *port_nvl;
2429 dbg = fopen("/tmp/log", "w+");
2432 sc = calloc(1, sizeof(struct pci_ahci_softc));
2435 pthread_mutex_init(&sc->mtx, NULL);
2440 ports_nvl = find_relative_config_node(nvl, "port");
2441 for (p = 0; ports_nvl != NULL && p < MAX_PORTS; p++) {
2442 struct ata_params *ata_ident = &sc->port[p].ata_ident;
2443 char ident[AHCI_PORT_IDENT];
2445 snprintf(node_name, sizeof(node_name), "%d", p);
2446 port_nvl = find_relative_config_node(ports_nvl, node_name);
2447 if (port_nvl == NULL)
2450 type = get_config_value_node(port_nvl, "type");
2454 if (strcmp(type, "hd") == 0)
2460 * Attempt to open the backing image. Use the PCI slot/func
2461 * and the port number for the identifier string.
2463 snprintf(bident, sizeof(bident), "%d:%d:%d", pi->pi_slot,
2466 bctxt = blockif_open(port_nvl, bident);
2467 if (bctxt == NULL) {
2472 sc->port[p].bctx = bctxt;
2473 sc->port[p].pr_sc = sc;
2474 sc->port[p].port = p;
2475 sc->port[p].atapi = atapi;
2478 * Create an identifier for the backing file.
2479 * Use parts of the md5 sum of the filename
2481 path = get_config_value_node(port_nvl, "path");
2483 MD5Update(&mdctx, path, strlen(path));
2484 MD5Final(digest, &mdctx);
2485 snprintf(ident, AHCI_PORT_IDENT,
2486 "BHYVE-%02X%02X-%02X%02X-%02X%02X",
2487 digest[0], digest[1], digest[2], digest[3], digest[4],
2490 memset(ata_ident, 0, sizeof(struct ata_params));
2491 ata_string((uint8_t*)&ata_ident->serial, ident, 20);
2492 ata_string((uint8_t*)&ata_ident->revision, "001", 8);
2494 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DVD ROM", 40);
2496 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DISK", 40);
2497 value = get_config_value_node(port_nvl, "nmrr");
2499 ata_ident->media_rotation_rate = atoi(value);
2500 value = get_config_value_node(port_nvl, "ser");
2502 ata_string((uint8_t*)(&ata_ident->serial), value, 20);
2503 value = get_config_value_node(port_nvl, "rev");
2505 ata_string((uint8_t*)(&ata_ident->revision), value, 8);
2506 value = get_config_value_node(port_nvl, "model");
2508 ata_string((uint8_t*)(&ata_ident->model), value, 40);
2509 ata_identify_init(&sc->port[p], atapi);
2512 * Allocate blockif request structures and add them
2515 pci_ahci_ioreq_init(&sc->port[p]);
2518 if (sc->port[p].ioqsz < slots)
2519 slots = sc->port[p].ioqsz;
2523 /* Intel ICH8 AHCI */
2525 if (sc->ports < DEF_PORTS)
2526 sc->ports = DEF_PORTS;
2527 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2528 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2529 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2530 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2531 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2534 sc->cap2 = AHCI_CAP2_APST;
2537 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2538 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2539 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2540 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2541 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2542 p = MIN(sc->ports, 16);
2543 p = flsl(p) - ((p & (p - 1)) ? 0 : 1);
2544 pci_emul_add_msicap(pi, 1 << p);
2545 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2546 AHCI_OFFSET + sc->ports * AHCI_STEP);
2548 pci_lintr_request(pi);
2552 for (p = 0; p < sc->ports; p++) {
2553 if (sc->port[p].bctx != NULL)
2554 blockif_close(sc->port[p].bctx);
2562 #ifdef BHYVE_SNAPSHOT
2564 pci_ahci_snapshot_save_queues(struct ahci_port *port,
2565 struct vm_snapshot_meta *meta)
2569 struct ahci_ioreq *ioreq;
2571 STAILQ_FOREACH(ioreq, &port->iofhd, io_flist) {
2572 idx = ((void *) ioreq - (void *) port->ioreq) / sizeof(*ioreq);
2573 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2577 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2579 TAILQ_FOREACH(ioreq, &port->iobhd, io_blist) {
2580 idx = ((void *) ioreq - (void *) port->ioreq) / sizeof(*ioreq);
2581 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2584 * Snapshot only the busy requests; other requests are
2587 ret = blockif_snapshot_req(&ioreq->io_req, meta);
2589 fprintf(stderr, "%s: failed to snapshot req\r\n",
2596 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2603 pci_ahci_snapshot_restore_queues(struct ahci_port *port,
2604 struct vm_snapshot_meta *meta)
2608 struct ahci_ioreq *ioreq;
2610 /* Empty the free queue before restoring. */
2611 while (!STAILQ_EMPTY(&port->iofhd))
2612 STAILQ_REMOVE_HEAD(&port->iofhd, io_flist);
2614 /* Restore the free queue. */
2616 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2620 STAILQ_INSERT_TAIL(&port->iofhd, &port->ioreq[idx], io_flist);
2623 /* Restore the busy queue. */
2625 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2629 ioreq = &port->ioreq[idx];
2630 TAILQ_INSERT_TAIL(&port->iobhd, ioreq, io_blist);
2633 * Restore only the busy requests; other requests are
2636 ret = blockif_snapshot_req(&ioreq->io_req, meta);
2638 fprintf(stderr, "%s: failed to restore request\r\n",
2643 /* Re-enqueue the requests in the block interface. */
2645 ret = blockif_read(port->bctx, &ioreq->io_req);
2647 ret = blockif_write(port->bctx, &ioreq->io_req);
2651 "%s: failed to re-enqueue request\r\n",
2662 pci_ahci_snapshot(struct vm_snapshot_meta *meta)
2666 struct pci_devinst *pi;
2667 struct pci_ahci_softc *sc;
2668 struct ahci_port *port;
2669 struct ahci_cmd_hdr *hdr;
2670 struct ahci_ioreq *ioreq;
2672 pi = meta->dev_data;
2675 /* TODO: add mtx lock/unlock */
2677 SNAPSHOT_VAR_OR_LEAVE(sc->ports, meta, ret, done);
2678 SNAPSHOT_VAR_OR_LEAVE(sc->cap, meta, ret, done);
2679 SNAPSHOT_VAR_OR_LEAVE(sc->ghc, meta, ret, done);
2680 SNAPSHOT_VAR_OR_LEAVE(sc->is, meta, ret, done);
2681 SNAPSHOT_VAR_OR_LEAVE(sc->pi, meta, ret, done);
2682 SNAPSHOT_VAR_OR_LEAVE(sc->vs, meta, ret, done);
2683 SNAPSHOT_VAR_OR_LEAVE(sc->ccc_ctl, meta, ret, done);
2684 SNAPSHOT_VAR_OR_LEAVE(sc->ccc_pts, meta, ret, done);
2685 SNAPSHOT_VAR_OR_LEAVE(sc->em_loc, meta, ret, done);
2686 SNAPSHOT_VAR_OR_LEAVE(sc->em_ctl, meta, ret, done);
2687 SNAPSHOT_VAR_OR_LEAVE(sc->cap2, meta, ret, done);
2688 SNAPSHOT_VAR_OR_LEAVE(sc->bohc, meta, ret, done);
2689 SNAPSHOT_VAR_OR_LEAVE(sc->lintr, meta, ret, done);
2691 for (i = 0; i < MAX_PORTS; i++) {
2692 port = &sc->port[i];
2694 if (meta->op == VM_SNAPSHOT_SAVE)
2697 SNAPSHOT_VAR_OR_LEAVE(bctx, meta, ret, done);
2698 SNAPSHOT_VAR_OR_LEAVE(port->port, meta, ret, done);
2700 /* Mostly for restore; save is ensured by the lines above. */
2701 if (((bctx == NULL) && (port->bctx != NULL)) ||
2702 ((bctx != NULL) && (port->bctx == NULL))) {
2703 fprintf(stderr, "%s: ports not matching\r\n", __func__);
2708 if (port->bctx == NULL)
2711 if (port->port != i) {
2712 fprintf(stderr, "%s: ports not matching: "
2713 "actual: %d expected: %d\r\n",
2714 __func__, port->port, i);
2719 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(port->cmd_lst,
2720 AHCI_CL_SIZE * AHCI_MAX_SLOTS, false, meta, ret, done);
2721 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(port->rfis, 256, false, meta,
2724 SNAPSHOT_VAR_OR_LEAVE(port->ata_ident, meta, ret, done);
2725 SNAPSHOT_VAR_OR_LEAVE(port->atapi, meta, ret, done);
2726 SNAPSHOT_VAR_OR_LEAVE(port->reset, meta, ret, done);
2727 SNAPSHOT_VAR_OR_LEAVE(port->waitforclear, meta, ret, done);
2728 SNAPSHOT_VAR_OR_LEAVE(port->mult_sectors, meta, ret, done);
2729 SNAPSHOT_VAR_OR_LEAVE(port->xfermode, meta, ret, done);
2730 SNAPSHOT_VAR_OR_LEAVE(port->err_cfis, meta, ret, done);
2731 SNAPSHOT_VAR_OR_LEAVE(port->sense_key, meta, ret, done);
2732 SNAPSHOT_VAR_OR_LEAVE(port->asc, meta, ret, done);
2733 SNAPSHOT_VAR_OR_LEAVE(port->ccs, meta, ret, done);
2734 SNAPSHOT_VAR_OR_LEAVE(port->pending, meta, ret, done);
2736 SNAPSHOT_VAR_OR_LEAVE(port->clb, meta, ret, done);
2737 SNAPSHOT_VAR_OR_LEAVE(port->clbu, meta, ret, done);
2738 SNAPSHOT_VAR_OR_LEAVE(port->fb, meta, ret, done);
2739 SNAPSHOT_VAR_OR_LEAVE(port->fbu, meta, ret, done);
2740 SNAPSHOT_VAR_OR_LEAVE(port->ie, meta, ret, done);
2741 SNAPSHOT_VAR_OR_LEAVE(port->cmd, meta, ret, done);
2742 SNAPSHOT_VAR_OR_LEAVE(port->unused0, meta, ret, done);
2743 SNAPSHOT_VAR_OR_LEAVE(port->tfd, meta, ret, done);
2744 SNAPSHOT_VAR_OR_LEAVE(port->sig, meta, ret, done);
2745 SNAPSHOT_VAR_OR_LEAVE(port->ssts, meta, ret, done);
2746 SNAPSHOT_VAR_OR_LEAVE(port->sctl, meta, ret, done);
2747 SNAPSHOT_VAR_OR_LEAVE(port->serr, meta, ret, done);
2748 SNAPSHOT_VAR_OR_LEAVE(port->sact, meta, ret, done);
2749 SNAPSHOT_VAR_OR_LEAVE(port->ci, meta, ret, done);
2750 SNAPSHOT_VAR_OR_LEAVE(port->sntf, meta, ret, done);
2751 SNAPSHOT_VAR_OR_LEAVE(port->fbs, meta, ret, done);
2752 SNAPSHOT_VAR_OR_LEAVE(port->ioqsz, meta, ret, done);
2754 for (j = 0; j < port->ioqsz; j++) {
2755 ioreq = &port->ioreq[j];
2757 /* blockif_req snapshot done only for busy requests. */
2758 hdr = (struct ahci_cmd_hdr *)(port->cmd_lst +
2759 ioreq->slot * AHCI_CL_SIZE);
2760 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(ioreq->cfis,
2761 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry),
2762 false, meta, ret, done);
2764 SNAPSHOT_VAR_OR_LEAVE(ioreq->len, meta, ret, done);
2765 SNAPSHOT_VAR_OR_LEAVE(ioreq->done, meta, ret, done);
2766 SNAPSHOT_VAR_OR_LEAVE(ioreq->slot, meta, ret, done);
2767 SNAPSHOT_VAR_OR_LEAVE(ioreq->more, meta, ret, done);
2768 SNAPSHOT_VAR_OR_LEAVE(ioreq->readop, meta, ret, done);
2771 /* Perform save / restore specific operations. */
2772 if (meta->op == VM_SNAPSHOT_SAVE) {
2773 ret = pci_ahci_snapshot_save_queues(port, meta);
2776 } else if (meta->op == VM_SNAPSHOT_RESTORE) {
2777 ret = pci_ahci_snapshot_restore_queues(port, meta);
2785 ret = blockif_snapshot(port->bctx, meta);
2787 fprintf(stderr, "%s: failed to restore blockif\r\n",
2798 pci_ahci_pause(struct vmctx *ctx, struct pci_devinst *pi)
2800 struct pci_ahci_softc *sc;
2801 struct blockif_ctxt *bctxt;
2806 for (i = 0; i < MAX_PORTS; i++) {
2807 bctxt = sc->port[i].bctx;
2811 blockif_pause(bctxt);
2818 pci_ahci_resume(struct vmctx *ctx, struct pci_devinst *pi)
2820 struct pci_ahci_softc *sc;
2821 struct blockif_ctxt *bctxt;
2826 for (i = 0; i < MAX_PORTS; i++) {
2827 bctxt = sc->port[i].bctx;
2831 blockif_resume(bctxt);
2839 * Use separate emulation names to distinguish drive and atapi devices
2841 static const struct pci_devemu pci_de_ahci = {
2843 .pe_init = pci_ahci_init,
2844 .pe_legacy_config = pci_ahci_legacy_config,
2845 .pe_barwrite = pci_ahci_write,
2846 .pe_barread = pci_ahci_read,
2847 #ifdef BHYVE_SNAPSHOT
2848 .pe_snapshot = pci_ahci_snapshot,
2849 .pe_pause = pci_ahci_pause,
2850 .pe_resume = pci_ahci_resume,
2853 PCI_EMUL_SET(pci_de_ahci);
2855 static const struct pci_devemu pci_de_ahci_hd = {
2856 .pe_emu = "ahci-hd",
2857 .pe_legacy_config = pci_ahci_hd_legacy_config,
2860 PCI_EMUL_SET(pci_de_ahci_hd);
2862 static const struct pci_devemu pci_de_ahci_cd = {
2863 .pe_emu = "ahci-cd",
2864 .pe_legacy_config = pci_ahci_cd_legacy_config,
2867 PCI_EMUL_SET(pci_de_ahci_cd);