2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/linker_set.h>
39 #include <sys/ioctl.h>
42 #include <sys/endian.h>
54 #include <pthread_np.h>
63 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
64 #define MAX_PORTS 32 /* AHCI supports 32 ports */
66 #define PxSIG_ATA 0x00000101 /* ATA drive */
67 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
70 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
71 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
72 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
73 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
74 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
75 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
76 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
77 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
83 #define TEST_UNIT_READY 0x00
84 #define REQUEST_SENSE 0x03
86 #define START_STOP_UNIT 0x1B
87 #define PREVENT_ALLOW 0x1E
88 #define READ_CAPACITY 0x25
90 #define POSITION_TO_ELEMENT 0x2B
92 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
93 #define MODE_SENSE_10 0x5A
94 #define REPORT_LUNS 0xA0
99 * SCSI mode page codes
101 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
102 #define MODEPAGE_CD_CAPABILITIES 0x2A
107 #define ATA_SF_ENAB_SATA_SF 0x10
108 #define ATA_SATA_SF_AN 0x05
109 #define ATA_SF_DIS_SATA_SF 0x90
116 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
118 #define DPRINTF(format, arg...)
120 #define WPRINTF(format, arg...) printf(format, ##arg)
122 #define AHCI_PORT_IDENT 20 + 1
125 struct blockif_req io_req;
126 struct ahci_port *io_pr;
127 STAILQ_ENTRY(ahci_ioreq) io_flist;
128 TAILQ_ENTRY(ahci_ioreq) io_blist;
137 struct blockif_ctxt *bctx;
138 struct pci_ahci_softc *pr_sc;
139 struct ata_params ata_ident;
148 uint8_t err_cfis[20];
175 struct ahci_ioreq *ioreq;
177 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
178 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
181 struct ahci_cmd_hdr {
186 uint32_t reserved[4];
189 struct ahci_prdt_entry {
192 #define DBCMASK 0x3fffff
196 struct pci_ahci_softc {
197 struct pci_devinst *asc_pi;
212 struct ahci_port port[MAX_PORTS];
214 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
216 static void ahci_handle_port(struct ahci_port *p);
218 static inline void lba_to_msf(uint8_t *buf, int lba)
221 buf[0] = (lba / 75) / 60;
222 buf[1] = (lba / 75) % 60;
227 * Generate HBA interrupts on global IS register write.
230 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask)
232 struct pci_devinst *pi = sc->asc_pi;
237 /* Update global IS from PxIS/PxIE. */
238 for (i = 0; i < sc->ports; i++) {
243 DPRINTF("%s(%08x) %08x\n", __func__, mask, sc->is);
245 /* If there is nothing enabled -- clear legacy interrupt and exit. */
246 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) {
248 pci_lintr_deassert(pi);
254 /* If there is anything and no MSI -- assert legacy interrupt. */
255 nmsg = pci_msi_maxmsgnum(pi);
259 pci_lintr_assert(pi);
264 /* Assert respective MSIs for ports that were touched. */
265 for (i = 0; i < nmsg; i++) {
266 if (sc->ports <= nmsg || i < nmsg - 1)
269 mmask = 0xffffffff << i;
270 if (sc->is & mask && mmask & mask)
271 pci_generate_msi(pi, i);
276 * Generate HBA interrupt on specific port event.
279 ahci_port_intr(struct ahci_port *p)
281 struct pci_ahci_softc *sc = p->pr_sc;
282 struct pci_devinst *pi = sc->asc_pi;
285 DPRINTF("%s(%d) %08x/%08x %08x\n", __func__,
286 p->port, p->is, p->ie, sc->is);
288 /* If there is nothing enabled -- we are done. */
289 if ((p->is & p->ie) == 0)
292 /* In case of non-shared MSI always generate interrupt. */
293 nmsg = pci_msi_maxmsgnum(pi);
294 if (sc->ports <= nmsg || p->port < nmsg - 1) {
295 sc->is |= (1 << p->port);
296 if ((sc->ghc & AHCI_GHC_IE) == 0)
298 pci_generate_msi(pi, p->port);
302 /* If IS for this port is already set -- do nothing. */
303 if (sc->is & (1 << p->port))
306 sc->is |= (1 << p->port);
308 /* If interrupts are enabled -- generate one. */
309 if ((sc->ghc & AHCI_GHC_IE) == 0)
312 pci_generate_msi(pi, nmsg - 1);
313 } else if (!sc->lintr) {
315 pci_lintr_assert(pi);
320 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
322 int offset, len, irq;
324 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
328 case FIS_TYPE_REGD2H:
331 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0;
333 case FIS_TYPE_SETDEVBITS:
336 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0;
338 case FIS_TYPE_PIOSETUP:
341 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
344 WPRINTF("unsupported fis type %d\n", ft);
347 if (fis[2] & ATA_S_ERROR) {
349 irq |= AHCI_P_IX_TFE;
351 memcpy(p->rfis + offset, fis, len);
361 ahci_write_fis_piosetup(struct ahci_port *p)
365 memset(fis, 0, sizeof(fis));
366 fis[0] = FIS_TYPE_PIOSETUP;
367 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
371 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
376 error = (tfd >> 8) & 0xff;
378 memset(fis, 0, sizeof(fis));
379 fis[0] = FIS_TYPE_SETDEVBITS;
383 if (fis[2] & ATA_S_ERROR) {
384 p->err_cfis[0] = slot;
385 p->err_cfis[2] = tfd;
386 p->err_cfis[3] = error;
387 memcpy(&p->err_cfis[4], cfis + 4, 16);
389 *(uint32_t *)(fis + 4) = (1 << slot);
390 p->sact &= ~(1 << slot);
394 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
398 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
403 error = (tfd >> 8) & 0xff;
404 memset(fis, 0, sizeof(fis));
405 fis[0] = FIS_TYPE_REGD2H;
419 if (fis[2] & ATA_S_ERROR) {
420 p->err_cfis[0] = 0x80;
421 p->err_cfis[2] = tfd & 0xff;
422 p->err_cfis[3] = error;
423 memcpy(&p->err_cfis[4], cfis + 4, 16);
425 p->ci &= ~(1 << slot);
427 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
431 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot)
435 p->tfd = ATA_S_READY | ATA_S_DSC;
436 memset(fis, 0, sizeof(fis));
437 fis[0] = FIS_TYPE_REGD2H;
438 fis[1] = 0; /* No interrupt */
439 fis[2] = p->tfd; /* Status */
440 fis[3] = 0; /* No error */
441 p->ci &= ~(1 << slot);
442 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
446 ahci_write_reset_fis_d2h(struct ahci_port *p)
450 memset(fis, 0, sizeof(fis));
451 fis[0] = FIS_TYPE_REGD2H;
459 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
463 ahci_check_stopped(struct ahci_port *p)
466 * If we are no longer processing the command list and nothing
467 * is in-flight, clear the running bit, the current command
468 * slot, the command issue and active bits.
470 if (!(p->cmd & AHCI_P_CMD_ST)) {
471 if (p->pending == 0) {
473 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
482 ahci_port_stop(struct ahci_port *p)
484 struct ahci_ioreq *aior;
489 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
491 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
493 * Try to cancel the outstanding blockif request.
495 error = blockif_cancel(p->bctx, &aior->io_req);
501 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
502 cfis[2] == ATA_READ_FPDMA_QUEUED ||
503 cfis[2] == ATA_SEND_FPDMA_QUEUED)
504 p->sact &= ~(1 << slot); /* NCQ */
506 p->ci &= ~(1 << slot);
509 * This command is now done.
511 p->pending &= ~(1 << slot);
514 * Delete the blockif request from the busy list
516 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
519 * Move the blockif request back to the free list
521 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
524 ahci_check_stopped(p);
528 ahci_port_reset(struct ahci_port *pr)
532 pr->xfermode = ATA_UDMA6;
533 pr->mult_sectors = 128;
536 pr->ssts = ATA_SS_DET_NO_DEVICE;
537 pr->sig = 0xFFFFFFFF;
541 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
542 if (pr->sctl & ATA_SC_SPD_MASK)
543 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
545 pr->ssts |= ATA_SS_SPD_GEN3;
546 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
549 pr->tfd |= ATA_S_READY;
551 pr->sig = PxSIG_ATAPI;
552 ahci_write_reset_fis_d2h(pr);
556 ahci_reset(struct pci_ahci_softc *sc)
560 sc->ghc = AHCI_GHC_AE;
564 pci_lintr_deassert(sc->asc_pi);
568 for (i = 0; i < sc->ports; i++) {
571 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD);
572 if (sc->port[i].bctx)
573 sc->port[i].cmd |= AHCI_P_CMD_CPS;
574 sc->port[i].sctl = 0;
575 ahci_port_reset(&sc->port[i]);
580 ata_string(uint8_t *dest, const char *src, int len)
584 for (i = 0; i < len; i++) {
586 dest[i ^ 1] = *src++;
593 atapi_string(uint8_t *dest, const char *src, int len)
597 for (i = 0; i < len; i++) {
606 * Build up the iovec based on the PRDT, 'done' and 'len'.
609 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior,
610 struct ahci_prdt_entry *prdt, uint16_t prdtl)
612 struct blockif_req *breq = &aior->io_req;
613 int i, j, skip, todo, left, extra;
616 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */
618 left = aior->len - aior->done;
620 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0;
622 dbcsz = (prdt->dbc & DBCMASK) + 1;
623 /* Skip already done part of the PRDT */
631 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc),
632 prdt->dba + skip, dbcsz);
633 breq->br_iov[j].iov_len = dbcsz;
640 /* If we got limited by IOV length, round I/O down to sector size. */
641 if (j == BLOCKIF_IOV_MAX) {
642 extra = todo % blockif_sectsz(p->bctx);
646 if (breq->br_iov[j - 1].iov_len > extra) {
647 breq->br_iov[j - 1].iov_len -= extra;
650 extra -= breq->br_iov[j - 1].iov_len;
656 breq->br_resid = todo;
658 aior->more = (aior->done < aior->len && i < prdtl);
662 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
664 struct ahci_ioreq *aior;
665 struct blockif_req *breq;
666 struct ahci_prdt_entry *prdt;
667 struct ahci_cmd_hdr *hdr;
670 int err, first, ncq, readop;
672 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
673 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
678 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
679 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
680 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
681 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
684 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
685 cfis[2] == ATA_READ_FPDMA_QUEUED) {
686 lba = ((uint64_t)cfis[10] << 40) |
687 ((uint64_t)cfis[9] << 32) |
688 ((uint64_t)cfis[8] << 24) |
689 ((uint64_t)cfis[6] << 16) |
690 ((uint64_t)cfis[5] << 8) |
692 len = cfis[11] << 8 | cfis[3];
696 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
697 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
698 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
699 lba = ((uint64_t)cfis[10] << 40) |
700 ((uint64_t)cfis[9] << 32) |
701 ((uint64_t)cfis[8] << 24) |
702 ((uint64_t)cfis[6] << 16) |
703 ((uint64_t)cfis[5] << 8) |
705 len = cfis[13] << 8 | cfis[12];
709 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
710 (cfis[5] << 8) | cfis[4];
715 lba *= blockif_sectsz(p->bctx);
716 len *= blockif_sectsz(p->bctx);
718 /* Pull request off free list */
719 aior = STAILQ_FIRST(&p->iofhd);
720 assert(aior != NULL);
721 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
727 breq = &aior->io_req;
728 breq->br_offset = lba + done;
729 ahci_build_iov(p, aior, prdt, hdr->prdtl);
731 /* Mark this command in-flight. */
732 p->pending |= 1 << slot;
734 /* Stuff request onto busy list. */
735 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
738 ahci_write_fis_d2h_ncq(p, slot);
741 err = blockif_read(p->bctx, breq);
743 err = blockif_write(p->bctx, breq);
748 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
750 struct ahci_ioreq *aior;
751 struct blockif_req *breq;
755 * Pull request off free list
757 aior = STAILQ_FIRST(&p->iofhd);
758 assert(aior != NULL);
759 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
765 breq = &aior->io_req;
768 * Mark this command in-flight.
770 p->pending |= 1 << slot;
773 * Stuff request onto busy list
775 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
777 err = blockif_flush(p->bctx, breq);
782 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
785 struct ahci_cmd_hdr *hdr;
786 struct ahci_prdt_entry *prdt;
790 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
793 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
794 for (i = 0; i < hdr->prdtl && len; i++) {
799 dbcsz = (prdt->dbc & DBCMASK) + 1;
800 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
801 sublen = MIN(len, dbcsz);
802 memcpy(to, ptr, sublen);
810 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
812 struct ahci_ioreq *aior;
813 struct blockif_req *breq;
821 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
822 len = (uint16_t)cfis[13] << 8 | cfis[12];
825 } else { /* ATA_SEND_FPDMA_QUEUED */
826 len = (uint16_t)cfis[11] << 8 | cfis[3];
830 read_prdt(p, slot, cfis, buf, sizeof(buf));
834 elba = ((uint64_t)entry[5] << 40) |
835 ((uint64_t)entry[4] << 32) |
836 ((uint64_t)entry[3] << 24) |
837 ((uint64_t)entry[2] << 16) |
838 ((uint64_t)entry[1] << 8) |
840 elen = (uint16_t)entry[7] << 8 | entry[6];
846 ahci_write_fis_d2h_ncq(p, slot);
847 ahci_write_fis_sdb(p, slot, cfis,
848 ATA_S_READY | ATA_S_DSC);
850 ahci_write_fis_d2h(p, slot, cfis,
851 ATA_S_READY | ATA_S_DSC);
853 p->pending &= ~(1 << slot);
854 ahci_check_stopped(p);
863 * Pull request off free list
865 aior = STAILQ_FIRST(&p->iofhd);
866 assert(aior != NULL);
867 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
872 aior->more = (len != done);
874 breq = &aior->io_req;
875 breq->br_offset = elba * blockif_sectsz(p->bctx);
876 breq->br_resid = elen * blockif_sectsz(p->bctx);
879 * Mark this command in-flight.
881 p->pending |= 1 << slot;
884 * Stuff request onto busy list
886 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
889 ahci_write_fis_d2h_ncq(p, slot);
891 err = blockif_delete(p->bctx, breq);
896 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
899 struct ahci_cmd_hdr *hdr;
900 struct ahci_prdt_entry *prdt;
904 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
907 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
908 for (i = 0; i < hdr->prdtl && len; i++) {
913 dbcsz = (prdt->dbc & DBCMASK) + 1;
914 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
915 sublen = MIN(len, dbcsz);
916 memcpy(ptr, from, sublen);
921 hdr->prdbc = size - len;
925 ahci_checksum(uint8_t *buf, int size)
930 for (i = 0; i < size - 1; i++)
932 buf[size - 1] = 0x100 - sum;
936 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
938 struct ahci_cmd_hdr *hdr;
940 uint8_t *buf8 = (uint8_t *)buf;
941 uint16_t *buf16 = (uint16_t *)buf;
943 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
944 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 ||
945 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
946 ahci_write_fis_d2h(p, slot, cfis,
947 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
951 memset(buf, 0, sizeof(buf));
952 if (cfis[4] == 0x00) { /* Log directory */
953 buf16[0x00] = 1; /* Version -- 1 */
954 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */
955 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */
956 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */
957 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis));
958 ahci_checksum(buf8, sizeof(buf));
959 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */
960 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) {
961 buf[0x00] = 1; /* SFQ DSM supported */
962 buf[0x01] = 1; /* SFQ DSM TRIM supported */
965 ahci_write_fis_d2h(p, slot, cfis,
966 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
970 if (cfis[2] == ATA_READ_LOG_EXT)
971 ahci_write_fis_piosetup(p);
972 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
973 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
977 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
979 struct ahci_cmd_hdr *hdr;
981 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
982 if (p->atapi || hdr->prdtl == 0) {
983 ahci_write_fis_d2h(p, slot, cfis,
984 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
986 ahci_write_fis_piosetup(p);
987 write_prdt(p, slot, cfis, (void*)&p->ata_ident, sizeof(struct ata_params));
988 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
993 ata_identify_init(struct ahci_port* p, int atapi)
995 struct ata_params* ata_ident = &p->ata_ident;
998 ata_ident->config = ATA_PROTO_ATAPI | ATA_ATAPI_TYPE_CDROM |
999 ATA_ATAPI_REMOVABLE | ATA_DRQ_FAST;
1000 ata_ident->capabilities1 = ATA_SUPPORT_LBA |
1002 ata_ident->capabilities2 = (1 << 14 | 1);
1003 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1004 ata_ident->obsolete62 = 0x3f;
1005 ata_ident->mwdmamodes = 7;
1006 if (p->xfermode & ATA_WDMA0)
1007 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1008 ata_ident->apiomodes = 3;
1009 ata_ident->mwdmamin = 0x0078;
1010 ata_ident->mwdmarec = 0x0078;
1011 ata_ident->pioblind = 0x0078;
1012 ata_ident->pioiordy = 0x0078;
1013 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
1014 ata_ident->satacapabilities2 = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
1015 ata_ident->satasupport = ATA_SUPPORT_NCQ_STREAM;
1016 ata_ident->version_major = 0x3f0;
1017 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1018 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1019 ata_ident->support.command2 = (1 << 14);
1020 ata_ident->support.extension = (1 << 14);
1021 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1022 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1023 ata_ident->enabled.extension = (1 << 14);
1024 ata_ident->udmamodes = 0x7f;
1025 if (p->xfermode & ATA_UDMA0)
1026 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1027 ata_ident->transport_major = 0x1020;
1028 ata_ident->integrity = 0x00a5;
1031 int sectsz, psectsz, psectoff, candelete, ro;
1033 uint8_t sech, heads;
1035 ro = blockif_is_ro(p->bctx);
1036 candelete = blockif_candelete(p->bctx);
1037 sectsz = blockif_sectsz(p->bctx);
1038 sectors = blockif_size(p->bctx) / sectsz;
1039 blockif_chs(p->bctx, &cyl, &heads, &sech);
1040 blockif_psectsz(p->bctx, &psectsz, &psectoff);
1041 ata_ident->config = ATA_DRQ_FAST;
1042 ata_ident->cylinders = cyl;
1043 ata_ident->heads = heads;
1044 ata_ident->sectors = sech;
1046 ata_ident->sectors_intr = (0x8000 | 128);
1049 ata_ident->capabilities1 = ATA_SUPPORT_DMA |
1050 ATA_SUPPORT_LBA | ATA_SUPPORT_IORDY;
1051 ata_ident->capabilities2 = (1 << 14);
1052 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1053 if (p->mult_sectors)
1054 ata_ident->multi = (ATA_MULTI_VALID | p->mult_sectors);
1055 if (sectors <= 0x0fffffff) {
1056 ata_ident->lba_size_1 = sectors;
1057 ata_ident->lba_size_2 = (sectors >> 16);
1059 ata_ident->lba_size_1 = 0xffff;
1060 ata_ident->lba_size_2 = 0x0fff;
1062 ata_ident->mwdmamodes = 0x7;
1063 if (p->xfermode & ATA_WDMA0)
1064 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1065 ata_ident->apiomodes = 0x3;
1066 ata_ident->mwdmamin = 0x0078;
1067 ata_ident->mwdmarec = 0x0078;
1068 ata_ident->pioblind = 0x0078;
1069 ata_ident->pioiordy = 0x0078;
1070 ata_ident->support3 = 0;
1071 ata_ident->queue = 31;
1072 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
1074 ata_ident->satacapabilities2 = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
1075 (p->ssts & ATA_SS_SPD_MASK) >> 3);
1076 ata_ident->version_major = 0x3f0;
1077 ata_ident->version_minor = 0x28;
1078 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1079 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1080 ata_ident->support.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1081 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
1082 ata_ident->support.extension = (1 << 14);
1083 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1084 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1085 ata_ident->enabled.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1086 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
1087 ata_ident->enabled.extension = (1 << 14);
1088 ata_ident->udmamodes = 0x7f;
1089 if (p->xfermode & ATA_UDMA0)
1090 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1091 ata_ident->lba_size48_1 = sectors;
1092 ata_ident->lba_size48_2 = (sectors >> 16);
1093 ata_ident->lba_size48_3 = (sectors >> 32);
1094 ata_ident->lba_size48_4 = (sectors >> 48);
1096 if (candelete && !ro) {
1097 ata_ident->support3 |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
1098 ata_ident->max_dsm_blocks = 1;
1099 ata_ident->support_dsm = ATA_SUPPORT_DSM_TRIM;
1101 ata_ident->pss = ATA_PSS_VALID_VALUE;
1102 ata_ident->lsalign = 0x4000;
1103 if (psectsz > sectsz) {
1104 ata_ident->pss |= ATA_PSS_MULTLS;
1105 ata_ident->pss |= ffsl(psectsz / sectsz) - 1;
1106 ata_ident->lsalign |= (psectoff / sectsz);
1109 ata_ident->pss |= ATA_PSS_LSSABOVE512;
1110 ata_ident->lss_1 = sectsz / 2;
1111 ata_ident->lss_2 = ((sectsz / 2) >> 16);
1113 ata_ident->support2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1114 ata_ident->enabled2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1115 ata_ident->transport_major = 0x1020;
1116 ata_ident->integrity = 0x00a5;
1118 ahci_checksum((uint8_t*)ata_ident, sizeof(struct ata_params));
1122 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1125 ahci_write_fis_d2h(p, slot, cfis,
1126 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1128 ahci_write_fis_piosetup(p);
1129 write_prdt(p, slot, cfis, (void *)&p->ata_ident, sizeof(struct ata_params));
1130 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1135 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
1144 if (acmd[1] & 1) { /* VPD */
1145 if (acmd[2] == 0) { /* Supported VPD pages */
1153 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1155 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1156 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1157 ahci_write_fis_d2h(p, slot, cfis, tfd);
1169 atapi_string(buf + 8, "BHYVE", 8);
1170 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1171 atapi_string(buf + 32, "001", 4);
1177 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1178 write_prdt(p, slot, cfis, buf, len);
1179 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1183 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1188 sectors = blockif_size(p->bctx) / 2048;
1189 be32enc(buf, sectors - 1);
1190 be32enc(buf + 4, 2048);
1191 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1192 write_prdt(p, slot, cfis, buf, sizeof(buf));
1193 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1197 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1205 len = be16dec(acmd + 7);
1206 format = acmd[9] >> 6;
1212 uint8_t start_track, buf[20], *bp;
1214 msf = (acmd[1] >> 1) & 1;
1215 start_track = acmd[6];
1216 if (start_track > 1 && start_track != 0xaa) {
1218 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1220 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1221 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1222 ahci_write_fis_d2h(p, slot, cfis, tfd);
1228 if (start_track <= 1) {
1248 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1252 lba_to_msf(bp, sectors);
1255 be32enc(bp, sectors);
1259 be16enc(buf, size - 2);
1262 write_prdt(p, slot, cfis, buf, len);
1263 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1264 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1271 memset(buf, 0, sizeof(buf));
1275 if (len > sizeof(buf))
1277 write_prdt(p, slot, cfis, buf, len);
1278 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1279 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1286 uint8_t *bp, buf[50];
1288 msf = (acmd[1] >> 1) & 1;
1324 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1328 lba_to_msf(bp, sectors);
1331 be32enc(bp, sectors);
1354 be16enc(buf, size - 2);
1357 write_prdt(p, slot, cfis, buf, len);
1358 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1359 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1366 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1368 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1369 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1370 ahci_write_fis_d2h(p, slot, cfis, tfd);
1377 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1381 memset(buf, 0, sizeof(buf));
1384 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1385 write_prdt(p, slot, cfis, buf, sizeof(buf));
1386 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1390 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
1392 struct ahci_ioreq *aior;
1393 struct ahci_cmd_hdr *hdr;
1394 struct ahci_prdt_entry *prdt;
1395 struct blockif_req *breq;
1402 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1403 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1405 lba = be32dec(acmd + 2);
1406 if (acmd[0] == READ_10)
1407 len = be16dec(acmd + 7);
1409 len = be32dec(acmd + 6);
1411 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1412 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1418 * Pull request off free list
1420 aior = STAILQ_FIRST(&p->iofhd);
1421 assert(aior != NULL);
1422 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1427 breq = &aior->io_req;
1428 breq->br_offset = lba + done;
1429 ahci_build_iov(p, aior, prdt, hdr->prdtl);
1431 /* Mark this command in-flight. */
1432 p->pending |= 1 << slot;
1434 /* Stuff request onto busy list. */
1435 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1437 err = blockif_read(p->bctx, breq);
1442 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1450 if (len > sizeof(buf))
1452 memset(buf, 0, len);
1453 buf[0] = 0x70 | (1 << 7);
1454 buf[2] = p->sense_key;
1457 write_prdt(p, slot, cfis, buf, len);
1458 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1459 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1463 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1465 uint8_t *acmd = cfis + 0x40;
1468 switch (acmd[4] & 3) {
1472 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1473 tfd = ATA_S_READY | ATA_S_DSC;
1476 /* TODO eject media */
1477 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1478 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1480 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1483 ahci_write_fis_d2h(p, slot, cfis, tfd);
1487 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1495 len = be16dec(acmd + 7);
1497 code = acmd[2] & 0x3f;
1502 case MODEPAGE_RW_ERROR_RECOVERY:
1506 if (len > sizeof(buf))
1509 memset(buf, 0, sizeof(buf));
1510 be16enc(buf, 16 - 2);
1515 write_prdt(p, slot, cfis, buf, len);
1516 tfd = ATA_S_READY | ATA_S_DSC;
1519 case MODEPAGE_CD_CAPABILITIES:
1523 if (len > sizeof(buf))
1526 memset(buf, 0, sizeof(buf));
1527 be16enc(buf, 30 - 2);
1533 be16enc(&buf[18], 2);
1534 be16enc(&buf[20], 512);
1535 write_prdt(p, slot, cfis, buf, len);
1536 tfd = ATA_S_READY | ATA_S_DSC;
1545 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1547 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1552 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1554 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1557 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1558 ahci_write_fis_d2h(p, slot, cfis, tfd);
1562 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1570 /* we don't support asynchronous operation */
1571 if (!(acmd[1] & 1)) {
1572 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1574 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1579 len = be16dec(acmd + 7);
1580 if (len > sizeof(buf))
1583 memset(buf, 0, sizeof(buf));
1584 be16enc(buf, 8 - 2);
1588 write_prdt(p, slot, cfis, buf, len);
1589 tfd = ATA_S_READY | ATA_S_DSC;
1591 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1592 ahci_write_fis_d2h(p, slot, cfis, tfd);
1596 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1606 for (i = 0; i < 16; i++)
1607 DPRINTF("%02x ", acmd[i]);
1613 case TEST_UNIT_READY:
1614 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1615 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1618 atapi_inquiry(p, slot, cfis);
1621 atapi_read_capacity(p, slot, cfis);
1625 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1626 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1629 atapi_read_toc(p, slot, cfis);
1632 atapi_report_luns(p, slot, cfis);
1636 atapi_read(p, slot, cfis, 0);
1639 atapi_request_sense(p, slot, cfis);
1641 case START_STOP_UNIT:
1642 atapi_start_stop_unit(p, slot, cfis);
1645 atapi_mode_sense(p, slot, cfis);
1647 case GET_EVENT_STATUS_NOTIFICATION:
1648 atapi_get_event_status_notification(p, slot, cfis);
1651 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1652 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1654 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1655 ATA_S_READY | ATA_S_ERROR);
1661 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1664 p->tfd |= ATA_S_BUSY;
1666 case ATA_ATA_IDENTIFY:
1667 handle_identify(p, slot, cfis);
1669 case ATA_SETFEATURES:
1672 case ATA_SF_ENAB_SATA_SF:
1674 case ATA_SATA_SF_AN:
1675 p->tfd = ATA_S_DSC | ATA_S_READY;
1678 p->tfd = ATA_S_ERROR | ATA_S_READY;
1679 p->tfd |= (ATA_ERROR_ABORT << 8);
1683 case ATA_SF_ENAB_WCACHE:
1684 case ATA_SF_DIS_WCACHE:
1685 case ATA_SF_ENAB_RCACHE:
1686 case ATA_SF_DIS_RCACHE:
1687 p->tfd = ATA_S_DSC | ATA_S_READY;
1689 case ATA_SF_SETXFER:
1691 switch (cfis[12] & 0xf8) {
1697 p->xfermode = (cfis[12] & 0x7);
1700 p->tfd = ATA_S_DSC | ATA_S_READY;
1704 p->tfd = ATA_S_ERROR | ATA_S_READY;
1705 p->tfd |= (ATA_ERROR_ABORT << 8);
1708 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1712 if (cfis[12] != 0 &&
1713 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1714 p->tfd = ATA_S_ERROR | ATA_S_READY;
1715 p->tfd |= (ATA_ERROR_ABORT << 8);
1717 p->mult_sectors = cfis[12];
1718 p->tfd = ATA_S_DSC | ATA_S_READY;
1720 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1728 case ATA_READ_MUL48:
1729 case ATA_WRITE_MUL48:
1732 case ATA_READ_DMA48:
1733 case ATA_WRITE_DMA48:
1734 case ATA_READ_FPDMA_QUEUED:
1735 case ATA_WRITE_FPDMA_QUEUED:
1736 ahci_handle_rw(p, slot, cfis, 0);
1738 case ATA_FLUSHCACHE:
1739 case ATA_FLUSHCACHE48:
1740 ahci_handle_flush(p, slot, cfis);
1742 case ATA_DATA_SET_MANAGEMENT:
1743 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1744 cfis[13] == 0 && cfis[12] == 1) {
1745 ahci_handle_dsm_trim(p, slot, cfis, 0);
1748 ahci_write_fis_d2h(p, slot, cfis,
1749 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1751 case ATA_SEND_FPDMA_QUEUED:
1752 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1753 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1754 cfis[11] == 0 && cfis[3] == 1) {
1755 ahci_handle_dsm_trim(p, slot, cfis, 0);
1758 ahci_write_fis_d2h(p, slot, cfis,
1759 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1761 case ATA_READ_LOG_EXT:
1762 case ATA_READ_LOG_DMA_EXT:
1763 ahci_handle_read_log(p, slot, cfis);
1765 case ATA_SECURITY_FREEZE_LOCK:
1768 ahci_write_fis_d2h(p, slot, cfis,
1769 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1771 case ATA_CHECK_POWER_MODE:
1772 cfis[12] = 0xff; /* always on */
1773 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1775 case ATA_STANDBY_CMD:
1776 case ATA_STANDBY_IMMEDIATE:
1778 case ATA_IDLE_IMMEDIATE:
1780 case ATA_READ_VERIFY:
1781 case ATA_READ_VERIFY48:
1782 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1784 case ATA_ATAPI_IDENTIFY:
1785 handle_atapi_identify(p, slot, cfis);
1787 case ATA_PACKET_CMD:
1789 ahci_write_fis_d2h(p, slot, cfis,
1790 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1792 handle_packet_cmd(p, slot, cfis);
1795 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1796 ahci_write_fis_d2h(p, slot, cfis,
1797 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1803 ahci_handle_slot(struct ahci_port *p, int slot)
1805 struct ahci_cmd_hdr *hdr;
1807 struct ahci_prdt_entry *prdt;
1809 struct pci_ahci_softc *sc;
1816 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1818 cfl = (hdr->flags & 0x1f) * 4;
1820 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1821 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1823 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1826 for (i = 0; i < cfl; i++) {
1829 DPRINTF("%02x ", cfis[i]);
1833 for (i = 0; i < hdr->prdtl; i++) {
1834 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1839 if (cfis[0] != FIS_TYPE_REGH2D) {
1840 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1844 if (cfis[1] & 0x80) {
1845 ahci_handle_cmd(p, slot, cfis);
1847 if (cfis[15] & (1 << 2))
1849 else if (p->reset) {
1853 p->ci &= ~(1 << slot);
1858 ahci_handle_port(struct ahci_port *p)
1861 if (!(p->cmd & AHCI_P_CMD_ST))
1865 * Search for any new commands to issue ignoring those that
1866 * are already in-flight. Stop if device is busy or in error.
1868 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) {
1869 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0)
1871 if (p->waitforclear)
1873 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) {
1874 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1875 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT;
1876 ahci_handle_slot(p, p->ccs);
1882 * blockif callback routine - this runs in the context of the blockif
1883 * i/o thread, so the mutex needs to be acquired.
1886 ata_ioreq_cb(struct blockif_req *br, int err)
1888 struct ahci_cmd_hdr *hdr;
1889 struct ahci_ioreq *aior;
1890 struct ahci_port *p;
1891 struct pci_ahci_softc *sc;
1896 DPRINTF("%s %d\n", __func__, err);
1899 aior = br->br_param;
1904 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1906 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1907 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1908 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1910 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1911 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1912 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1915 pthread_mutex_lock(&sc->mtx);
1918 * Delete the blockif request from the busy list
1920 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1923 * Move the blockif request back to the free list
1925 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1928 hdr->prdbc = aior->done;
1930 if (!err && aior->more) {
1932 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1934 ahci_handle_rw(p, slot, cfis, aior->done);
1939 tfd = ATA_S_READY | ATA_S_DSC;
1941 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1943 ahci_write_fis_sdb(p, slot, cfis, tfd);
1945 ahci_write_fis_d2h(p, slot, cfis, tfd);
1948 * This command is now complete.
1950 p->pending &= ~(1 << slot);
1952 ahci_check_stopped(p);
1953 ahci_handle_port(p);
1955 pthread_mutex_unlock(&sc->mtx);
1956 DPRINTF("%s exit\n", __func__);
1960 atapi_ioreq_cb(struct blockif_req *br, int err)
1962 struct ahci_cmd_hdr *hdr;
1963 struct ahci_ioreq *aior;
1964 struct ahci_port *p;
1965 struct pci_ahci_softc *sc;
1970 DPRINTF("%s %d\n", __func__, err);
1972 aior = br->br_param;
1977 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1979 pthread_mutex_lock(&sc->mtx);
1982 * Delete the blockif request from the busy list
1984 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1987 * Move the blockif request back to the free list
1989 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1992 hdr->prdbc = aior->done;
1994 if (!err && aior->more) {
1995 atapi_read(p, slot, cfis, aior->done);
2000 tfd = ATA_S_READY | ATA_S_DSC;
2002 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
2004 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
2006 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
2007 ahci_write_fis_d2h(p, slot, cfis, tfd);
2010 * This command is now complete.
2012 p->pending &= ~(1 << slot);
2014 ahci_check_stopped(p);
2015 ahci_handle_port(p);
2017 pthread_mutex_unlock(&sc->mtx);
2018 DPRINTF("%s exit\n", __func__);
2022 pci_ahci_ioreq_init(struct ahci_port *pr)
2024 struct ahci_ioreq *vr;
2027 pr->ioqsz = blockif_queuesz(pr->bctx);
2028 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
2029 STAILQ_INIT(&pr->iofhd);
2032 * Add all i/o request entries to the free queue
2034 for (i = 0; i < pr->ioqsz; i++) {
2038 vr->io_req.br_callback = ata_ioreq_cb;
2040 vr->io_req.br_callback = atapi_ioreq_cb;
2041 vr->io_req.br_param = vr;
2042 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
2045 TAILQ_INIT(&pr->iobhd);
2049 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2051 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2052 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2053 struct ahci_port *p = &sc->port[port];
2055 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
2056 port, offset, value);
2076 p->ie = value & 0xFDC000FF;
2081 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2082 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2083 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2084 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK);
2085 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2086 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2087 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2088 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value;
2090 if (!(value & AHCI_P_CMD_ST)) {
2095 p->cmd |= AHCI_P_CMD_CR;
2096 clb = (uint64_t)p->clbu << 32 | p->clb;
2097 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
2098 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
2101 if (value & AHCI_P_CMD_FRE) {
2104 p->cmd |= AHCI_P_CMD_FR;
2105 fb = (uint64_t)p->fbu << 32 | p->fb;
2106 /* we don't support FBSCP, so rfis size is 256Bytes */
2107 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
2109 p->cmd &= ~AHCI_P_CMD_FR;
2112 if (value & AHCI_P_CMD_CLO) {
2113 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ);
2114 p->cmd &= ~AHCI_P_CMD_CLO;
2117 if (value & AHCI_P_CMD_ICC_MASK) {
2118 p->cmd &= ~AHCI_P_CMD_ICC_MASK;
2121 ahci_handle_port(p);
2127 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
2131 if (!(p->cmd & AHCI_P_CMD_ST)) {
2132 if (value & ATA_SC_DET_RESET)
2144 ahci_handle_port(p);
2154 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2156 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
2164 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
2167 if (value & AHCI_GHC_HR) {
2171 if (value & AHCI_GHC_IE)
2172 sc->ghc |= AHCI_GHC_IE;
2174 sc->ghc &= ~AHCI_GHC_IE;
2175 ahci_generate_intr(sc, 0xffffffff);
2179 ahci_generate_intr(sc, value);
2187 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
2188 int baridx, uint64_t offset, int size, uint64_t value)
2190 struct pci_ahci_softc *sc = pi->pi_arg;
2192 assert(baridx == 5);
2193 assert((offset % 4) == 0 && size == 4);
2195 pthread_mutex_lock(&sc->mtx);
2197 if (offset < AHCI_OFFSET)
2198 pci_ahci_host_write(sc, offset, value);
2199 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2200 pci_ahci_port_write(sc, offset, value);
2202 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
2204 pthread_mutex_unlock(&sc->mtx);
2208 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2224 uint32_t *p = &sc->cap;
2225 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2233 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
2240 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2243 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2244 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2264 uint32_t *p= &sc->port[port].clb;
2265 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2274 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
2275 port, offset, value);
2281 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2282 uint64_t regoff, int size)
2284 struct pci_ahci_softc *sc = pi->pi_arg;
2288 assert(baridx == 5);
2289 assert(size == 1 || size == 2 || size == 4);
2290 assert((regoff & (size - 1)) == 0);
2292 pthread_mutex_lock(&sc->mtx);
2294 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */
2295 if (offset < AHCI_OFFSET)
2296 value = pci_ahci_host_read(sc, offset);
2297 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2298 value = pci_ahci_port_read(sc, offset);
2301 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n",
2304 value >>= 8 * (regoff & 0x3);
2306 pthread_mutex_unlock(&sc->mtx);
2312 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2314 char bident[sizeof("XX:XX:XX")];
2315 struct blockif_ctxt *bctxt;
2316 struct pci_ahci_softc *sc;
2321 char *bopt, *uopt, *xopts, *config;
2329 dbg = fopen("/tmp/log", "w+");
2332 sc = calloc(1, sizeof(struct pci_ahci_softc));
2335 pthread_mutex_init(&sc->mtx, NULL);
2340 for (p = 0; p < MAX_PORTS && opts != NULL; p++, opts = next) {
2341 struct ata_params *ata_ident = &sc->port[p].ata_ident;
2342 memset(ata_ident, 0, sizeof(struct ata_params));
2344 /* Identify and cut off type of present port. */
2345 if (strncmp(opts, "hd:", 3) == 0) {
2348 } else if (strncmp(opts, "cd:", 3) == 0) {
2353 /* Find and cut off the next port options. */
2354 next = strstr(opts, ",hd:");
2355 next2 = strstr(opts, ",cd:");
2356 if (next == NULL || (next2 != NULL && next2 < next))
2366 uopt = strdup(opts);
2368 fp = open_memstream(&bopt, &block_len);
2372 for (xopts = strtok(uopt, ",");
2374 xopts = strtok(NULL, ",")) {
2376 /* First option assume as block filename. */
2379 * Create an identifier for the backing file.
2380 * Use parts of the md5 sum of the filename
2382 char ident[AHCI_PORT_IDENT];
2384 MD5Update(&mdctx, opts, strlen(opts));
2385 MD5Final(digest, &mdctx);
2386 snprintf(ident, AHCI_PORT_IDENT,
2387 "BHYVE-%02X%02X-%02X%02X-%02X%02X",
2388 digest[0], digest[1], digest[2], digest[3], digest[4],
2390 ata_string((uint8_t*)&ata_ident->serial, ident, 20);
2391 ata_string((uint8_t*)&ata_ident->revision, "001", 8);
2393 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DVD ROM", 40);
2396 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DISK", 40);
2400 if ((config = strchr(xopts, '=')) != NULL) {
2402 if (!strcmp("nmrr", xopts)) {
2403 ata_ident->media_rotation_rate = atoi(config);
2405 else if (!strcmp("ser", xopts)) {
2406 ata_string((uint8_t*)(&ata_ident->serial), config, 20);
2408 else if (!strcmp("rev", xopts)) {
2409 ata_string((uint8_t*)(&ata_ident->revision), config, 8);
2411 else if (!strcmp("model", xopts)) {
2412 ata_string((uint8_t*)(&ata_ident->model), config, 40);
2415 /* Pass all other options to blockif_open. */
2417 fprintf(fp, "%s%s", comma ? "," : "", xopts);
2422 /* Pass all other options to blockif_open. */
2423 fprintf(fp, "%s%s", comma ? "," : "", xopts);
2431 DPRINTF("%s\n", bopt);
2434 * Attempt to open the backing image. Use the PCI slot/func
2435 * and the port number for the identifier string.
2437 snprintf(bident, sizeof(bident), "%d:%d:%d", pi->pi_slot,
2439 bctxt = blockif_open(bopt, bident);
2442 if (bctxt == NULL) {
2447 sc->port[p].bctx = bctxt;
2448 sc->port[p].pr_sc = sc;
2449 sc->port[p].port = p;
2450 sc->port[p].atapi = atapi;
2452 ata_identify_init(&sc->port[p], atapi);
2455 * Allocate blockif request structures and add them
2458 pci_ahci_ioreq_init(&sc->port[p]);
2461 if (sc->port[p].ioqsz < slots)
2462 slots = sc->port[p].ioqsz;
2466 /* Intel ICH8 AHCI */
2468 if (sc->ports < DEF_PORTS)
2469 sc->ports = DEF_PORTS;
2470 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2471 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2472 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2473 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2474 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2477 sc->cap2 = AHCI_CAP2_APST;
2480 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2481 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2482 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2483 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2484 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2485 p = MIN(sc->ports, 16);
2486 p = flsl(p) - ((p & (p - 1)) ? 0 : 1);
2487 pci_emul_add_msicap(pi, 1 << p);
2488 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2489 AHCI_OFFSET + sc->ports * AHCI_STEP);
2491 pci_lintr_request(pi);
2495 for (p = 0; p < sc->ports; p++) {
2496 if (sc->port[p].bctx != NULL)
2497 blockif_close(sc->port[p].bctx);
2506 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2509 return (pci_ahci_init(ctx, pi, opts, 0));
2513 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2516 return (pci_ahci_init(ctx, pi, opts, 1));
2520 * Use separate emulation names to distinguish drive and atapi devices
2522 struct pci_devemu pci_de_ahci = {
2524 .pe_init = pci_ahci_hd_init,
2525 .pe_barwrite = pci_ahci_write,
2526 .pe_barread = pci_ahci_read
2528 PCI_EMUL_SET(pci_de_ahci);
2530 struct pci_devemu pci_de_ahci_hd = {
2531 .pe_emu = "ahci-hd",
2532 .pe_init = pci_ahci_hd_init,
2533 .pe_barwrite = pci_ahci_write,
2534 .pe_barread = pci_ahci_read
2536 PCI_EMUL_SET(pci_de_ahci_hd);
2538 struct pci_devemu pci_de_ahci_cd = {
2539 .pe_emu = "ahci-cd",
2540 .pe_init = pci_ahci_atapi_init,
2541 .pe_barwrite = pci_ahci_write,
2542 .pe_barread = pci_ahci_read
2544 PCI_EMUL_SET(pci_de_ahci_cd);