2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 #include <sys/param.h>
32 #include <sys/linker_set.h>
35 #include <sys/ioctl.h>
38 #include <sys/endian.h>
50 #include <pthread_np.h>
64 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
65 #define MAX_PORTS 32 /* AHCI supports 32 ports */
67 #define PxSIG_ATA 0x00000101 /* ATA drive */
68 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
71 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
72 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
73 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
74 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
75 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
76 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
77 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
78 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
84 #define TEST_UNIT_READY 0x00
85 #define REQUEST_SENSE 0x03
87 #define START_STOP_UNIT 0x1B
88 #define PREVENT_ALLOW 0x1E
89 #define READ_CAPACITY 0x25
91 #define POSITION_TO_ELEMENT 0x2B
93 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
94 #define MODE_SENSE_10 0x5A
95 #define REPORT_LUNS 0xA0
100 * SCSI mode page codes
102 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
103 #define MODEPAGE_CD_CAPABILITIES 0x2A
108 #define ATA_SF_ENAB_SATA_SF 0x10
109 #define ATA_SATA_SF_AN 0x05
110 #define ATA_SF_DIS_SATA_SF 0x90
117 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
119 #define DPRINTF(format, arg...)
121 #define WPRINTF(format, arg...) printf(format, ##arg)
123 #define AHCI_PORT_IDENT 20 + 1
126 struct blockif_req io_req;
127 struct ahci_port *io_pr;
128 STAILQ_ENTRY(ahci_ioreq) io_flist;
129 TAILQ_ENTRY(ahci_ioreq) io_blist;
139 struct blockif_ctxt *bctx;
140 struct pci_ahci_softc *pr_sc;
141 struct ata_params ata_ident;
150 uint8_t err_cfis[20];
177 struct ahci_ioreq *ioreq;
179 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
180 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
183 struct ahci_cmd_hdr {
188 uint32_t reserved[4];
191 struct ahci_prdt_entry {
194 #define DBCMASK 0x3fffff
198 struct pci_ahci_softc {
199 struct pci_devinst *asc_pi;
214 struct ahci_port port[MAX_PORTS];
216 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
218 static void ahci_handle_port(struct ahci_port *p);
220 static inline void lba_to_msf(uint8_t *buf, int lba)
223 buf[0] = (lba / 75) / 60;
224 buf[1] = (lba / 75) % 60;
229 * Generate HBA interrupts on global IS register write.
232 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask)
234 struct pci_devinst *pi = sc->asc_pi;
239 /* Update global IS from PxIS/PxIE. */
240 for (i = 0; i < sc->ports; i++) {
245 DPRINTF("%s(%08x) %08x", __func__, mask, sc->is);
247 /* If there is nothing enabled -- clear legacy interrupt and exit. */
248 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) {
250 pci_lintr_deassert(pi);
256 /* If there is anything and no MSI -- assert legacy interrupt. */
257 nmsg = pci_msi_maxmsgnum(pi);
261 pci_lintr_assert(pi);
266 /* Assert respective MSIs for ports that were touched. */
267 for (i = 0; i < nmsg; i++) {
268 if (sc->ports <= nmsg || i < nmsg - 1)
271 mmask = 0xffffffff << i;
272 if (sc->is & mask && mmask & mask)
273 pci_generate_msi(pi, i);
278 * Generate HBA interrupt on specific port event.
281 ahci_port_intr(struct ahci_port *p)
283 struct pci_ahci_softc *sc = p->pr_sc;
284 struct pci_devinst *pi = sc->asc_pi;
287 DPRINTF("%s(%d) %08x/%08x %08x", __func__,
288 p->port, p->is, p->ie, sc->is);
290 /* If there is nothing enabled -- we are done. */
291 if ((p->is & p->ie) == 0)
294 /* In case of non-shared MSI always generate interrupt. */
295 nmsg = pci_msi_maxmsgnum(pi);
296 if (sc->ports <= nmsg || p->port < nmsg - 1) {
297 sc->is |= (1 << p->port);
298 if ((sc->ghc & AHCI_GHC_IE) == 0)
300 pci_generate_msi(pi, p->port);
304 /* If IS for this port is already set -- do nothing. */
305 if (sc->is & (1 << p->port))
308 sc->is |= (1 << p->port);
310 /* If interrupts are enabled -- generate one. */
311 if ((sc->ghc & AHCI_GHC_IE) == 0)
314 pci_generate_msi(pi, nmsg - 1);
315 } else if (!sc->lintr) {
317 pci_lintr_assert(pi);
322 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
324 int offset, len, irq;
326 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
330 case FIS_TYPE_REGD2H:
333 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0;
335 case FIS_TYPE_SETDEVBITS:
338 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0;
340 case FIS_TYPE_PIOSETUP:
343 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
346 WPRINTF("unsupported fis type %d", ft);
349 if (fis[2] & ATA_S_ERROR) {
351 irq |= AHCI_P_IX_TFE;
353 memcpy(p->rfis + offset, fis, len);
363 ahci_write_fis_piosetup(struct ahci_port *p)
367 memset(fis, 0, sizeof(fis));
368 fis[0] = FIS_TYPE_PIOSETUP;
369 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
373 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
378 error = (tfd >> 8) & 0xff;
380 memset(fis, 0, sizeof(fis));
381 fis[0] = FIS_TYPE_SETDEVBITS;
385 if (fis[2] & ATA_S_ERROR) {
386 p->err_cfis[0] = slot;
387 p->err_cfis[2] = tfd;
388 p->err_cfis[3] = error;
389 memcpy(&p->err_cfis[4], cfis + 4, 16);
391 *(uint32_t *)(fis + 4) = (1 << slot);
392 p->sact &= ~(1 << slot);
396 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
400 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
405 error = (tfd >> 8) & 0xff;
406 memset(fis, 0, sizeof(fis));
407 fis[0] = FIS_TYPE_REGD2H;
421 if (fis[2] & ATA_S_ERROR) {
422 p->err_cfis[0] = 0x80;
423 p->err_cfis[2] = tfd & 0xff;
424 p->err_cfis[3] = error;
425 memcpy(&p->err_cfis[4], cfis + 4, 16);
427 p->ci &= ~(1 << slot);
429 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
433 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot)
437 p->tfd = ATA_S_READY | ATA_S_DSC;
438 memset(fis, 0, sizeof(fis));
439 fis[0] = FIS_TYPE_REGD2H;
440 fis[1] = 0; /* No interrupt */
441 fis[2] = p->tfd; /* Status */
442 fis[3] = 0; /* No error */
443 p->ci &= ~(1 << slot);
444 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
448 ahci_write_reset_fis_d2h(struct ahci_port *p)
452 memset(fis, 0, sizeof(fis));
453 fis[0] = FIS_TYPE_REGD2H;
461 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
465 ahci_check_stopped(struct ahci_port *p)
468 * If we are no longer processing the command list and nothing
469 * is in-flight, clear the running bit, the current command
470 * slot, the command issue and active bits.
472 if (!(p->cmd & AHCI_P_CMD_ST)) {
473 if (p->pending == 0) {
475 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
484 ahci_port_stop(struct ahci_port *p)
486 struct ahci_ioreq *aior;
491 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
493 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
495 * Try to cancel the outstanding blockif request.
497 error = blockif_cancel(p->bctx, &aior->io_req);
503 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
504 cfis[2] == ATA_READ_FPDMA_QUEUED ||
505 cfis[2] == ATA_SEND_FPDMA_QUEUED)
506 p->sact &= ~(1 << slot); /* NCQ */
508 p->ci &= ~(1 << slot);
511 * This command is now done.
513 p->pending &= ~(1 << slot);
516 * Delete the blockif request from the busy list
518 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
521 * Move the blockif request back to the free list
523 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
526 ahci_check_stopped(p);
530 ahci_port_reset(struct ahci_port *pr)
534 pr->xfermode = ATA_UDMA6;
535 pr->mult_sectors = 128;
538 pr->ssts = ATA_SS_DET_NO_DEVICE;
539 pr->sig = 0xFFFFFFFF;
543 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
544 if (pr->sctl & ATA_SC_SPD_MASK)
545 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
547 pr->ssts |= ATA_SS_SPD_GEN3;
548 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
551 pr->tfd |= ATA_S_READY;
553 pr->sig = PxSIG_ATAPI;
554 ahci_write_reset_fis_d2h(pr);
558 ahci_reset(struct pci_ahci_softc *sc)
562 sc->ghc = AHCI_GHC_AE;
566 pci_lintr_deassert(sc->asc_pi);
570 for (i = 0; i < sc->ports; i++) {
573 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD);
574 if (sc->port[i].bctx)
575 sc->port[i].cmd |= AHCI_P_CMD_CPS;
576 sc->port[i].sctl = 0;
577 ahci_port_reset(&sc->port[i]);
582 ata_string(uint8_t *dest, const char *src, int len)
586 for (i = 0; i < len; i++) {
588 dest[i ^ 1] = *src++;
595 atapi_string(uint8_t *dest, const char *src, int len)
599 for (i = 0; i < len; i++) {
608 * Build up the iovec based on the PRDT, 'done' and 'len'.
611 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior,
612 struct ahci_prdt_entry *prdt, uint16_t prdtl)
614 struct blockif_req *breq = &aior->io_req;
615 uint32_t dbcsz, extra, left, skip, todo;
618 assert(aior->len >= aior->done);
620 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */
622 left = aior->len - aior->done;
624 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0;
626 dbcsz = (prdt->dbc & DBCMASK) + 1;
627 /* Skip already done part of the PRDT */
635 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc),
636 prdt->dba + skip, dbcsz);
637 breq->br_iov[j].iov_len = dbcsz;
644 /* If we got limited by IOV length, round I/O down to sector size. */
645 if (j == BLOCKIF_IOV_MAX) {
646 extra = todo % blockif_sectsz(p->bctx);
650 if (breq->br_iov[j - 1].iov_len > extra) {
651 breq->br_iov[j - 1].iov_len -= extra;
654 extra -= breq->br_iov[j - 1].iov_len;
660 breq->br_resid = todo;
662 aior->more = (aior->done < aior->len && i < prdtl);
666 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
668 struct ahci_ioreq *aior;
669 struct blockif_req *breq;
670 struct ahci_prdt_entry *prdt;
671 struct ahci_cmd_hdr *hdr;
674 int err, first, ncq, readop;
676 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
677 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
682 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
683 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
684 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
685 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
688 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
689 cfis[2] == ATA_READ_FPDMA_QUEUED) {
690 lba = ((uint64_t)cfis[10] << 40) |
691 ((uint64_t)cfis[9] << 32) |
692 ((uint64_t)cfis[8] << 24) |
693 ((uint64_t)cfis[6] << 16) |
694 ((uint64_t)cfis[5] << 8) |
696 len = cfis[11] << 8 | cfis[3];
700 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
701 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
702 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
703 lba = ((uint64_t)cfis[10] << 40) |
704 ((uint64_t)cfis[9] << 32) |
705 ((uint64_t)cfis[8] << 24) |
706 ((uint64_t)cfis[6] << 16) |
707 ((uint64_t)cfis[5] << 8) |
709 len = cfis[13] << 8 | cfis[12];
713 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
714 (cfis[5] << 8) | cfis[4];
719 lba *= blockif_sectsz(p->bctx);
720 len *= blockif_sectsz(p->bctx);
722 /* Pull request off free list */
723 aior = STAILQ_FIRST(&p->iofhd);
724 assert(aior != NULL);
725 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
731 aior->readop = readop;
732 breq = &aior->io_req;
733 breq->br_offset = lba + done;
734 ahci_build_iov(p, aior, prdt, hdr->prdtl);
736 /* Mark this command in-flight. */
737 p->pending |= 1 << slot;
739 /* Stuff request onto busy list. */
740 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
743 ahci_write_fis_d2h_ncq(p, slot);
746 err = blockif_read(p->bctx, breq);
748 err = blockif_write(p->bctx, breq);
753 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
755 struct ahci_ioreq *aior;
756 struct blockif_req *breq;
760 * Pull request off free list
762 aior = STAILQ_FIRST(&p->iofhd);
763 assert(aior != NULL);
764 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
770 breq = &aior->io_req;
773 * Mark this command in-flight.
775 p->pending |= 1 << slot;
778 * Stuff request onto busy list
780 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
782 err = blockif_flush(p->bctx, breq);
787 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf,
790 struct ahci_cmd_hdr *hdr;
791 struct ahci_prdt_entry *prdt;
796 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
799 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
800 for (i = 0; i < hdr->prdtl && len; i++) {
805 dbcsz = (prdt->dbc & DBCMASK) + 1;
806 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
807 sublen = MIN(len, dbcsz);
808 memcpy(to, ptr, sublen);
816 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
818 struct ahci_ioreq *aior;
819 struct blockif_req *breq;
827 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
828 len = (uint16_t)cfis[13] << 8 | cfis[12];
831 } else { /* ATA_SEND_FPDMA_QUEUED */
832 len = (uint16_t)cfis[11] << 8 | cfis[3];
836 read_prdt(p, slot, cfis, buf, sizeof(buf));
840 elba = ((uint64_t)entry[5] << 40) |
841 ((uint64_t)entry[4] << 32) |
842 ((uint64_t)entry[3] << 24) |
843 ((uint64_t)entry[2] << 16) |
844 ((uint64_t)entry[1] << 8) |
846 elen = (uint16_t)entry[7] << 8 | entry[6];
852 ahci_write_fis_d2h_ncq(p, slot);
853 ahci_write_fis_sdb(p, slot, cfis,
854 ATA_S_READY | ATA_S_DSC);
856 ahci_write_fis_d2h(p, slot, cfis,
857 ATA_S_READY | ATA_S_DSC);
859 p->pending &= ~(1 << slot);
860 ahci_check_stopped(p);
869 * Pull request off free list
871 aior = STAILQ_FIRST(&p->iofhd);
872 assert(aior != NULL);
873 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
878 aior->more = (len != done);
880 breq = &aior->io_req;
881 breq->br_offset = elba * blockif_sectsz(p->bctx);
882 breq->br_resid = elen * blockif_sectsz(p->bctx);
885 * Mark this command in-flight.
887 p->pending |= 1 << slot;
890 * Stuff request onto busy list
892 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
895 ahci_write_fis_d2h_ncq(p, slot);
897 err = blockif_delete(p->bctx, breq);
902 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf,
905 struct ahci_cmd_hdr *hdr;
906 struct ahci_prdt_entry *prdt;
911 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
914 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
915 for (i = 0; i < hdr->prdtl && len; i++) {
920 dbcsz = (prdt->dbc & DBCMASK) + 1;
921 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
922 sublen = MIN(len, dbcsz);
923 memcpy(ptr, from, sublen);
928 hdr->prdbc = size - len;
932 ahci_checksum(uint8_t *buf, int size)
937 for (i = 0; i < size - 1; i++)
939 buf[size - 1] = 0x100 - sum;
943 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
945 struct ahci_cmd_hdr *hdr;
947 uint8_t *buf8 = (uint8_t *)buf;
948 uint16_t *buf16 = (uint16_t *)buf;
950 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
951 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 ||
952 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
953 ahci_write_fis_d2h(p, slot, cfis,
954 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
958 memset(buf, 0, sizeof(buf));
959 if (cfis[4] == 0x00) { /* Log directory */
960 buf16[0x00] = 1; /* Version -- 1 */
961 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */
962 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */
963 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */
964 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis));
965 ahci_checksum(buf8, sizeof(buf));
966 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */
967 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) {
968 buf[0x00] = 1; /* SFQ DSM supported */
969 buf[0x01] = 1; /* SFQ DSM TRIM supported */
972 ahci_write_fis_d2h(p, slot, cfis,
973 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
977 if (cfis[2] == ATA_READ_LOG_EXT)
978 ahci_write_fis_piosetup(p);
979 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
980 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
984 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
986 struct ahci_cmd_hdr *hdr;
988 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
989 if (p->atapi || hdr->prdtl == 0) {
990 ahci_write_fis_d2h(p, slot, cfis,
991 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
993 ahci_write_fis_piosetup(p);
994 write_prdt(p, slot, cfis, (void*)&p->ata_ident, sizeof(struct ata_params));
995 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1000 ata_identify_init(struct ahci_port* p, int atapi)
1002 struct ata_params* ata_ident = &p->ata_ident;
1005 ata_ident->config = ATA_PROTO_ATAPI | ATA_ATAPI_TYPE_CDROM |
1006 ATA_ATAPI_REMOVABLE | ATA_DRQ_FAST;
1007 ata_ident->capabilities1 = ATA_SUPPORT_LBA |
1009 ata_ident->capabilities2 = (1 << 14 | 1);
1010 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1011 ata_ident->obsolete62 = 0x3f;
1012 ata_ident->mwdmamodes = 7;
1013 if (p->xfermode & ATA_WDMA0)
1014 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1015 ata_ident->apiomodes = 3;
1016 ata_ident->mwdmamin = 0x0078;
1017 ata_ident->mwdmarec = 0x0078;
1018 ata_ident->pioblind = 0x0078;
1019 ata_ident->pioiordy = 0x0078;
1020 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
1021 ata_ident->satacapabilities2 = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
1022 ata_ident->satasupport = ATA_SUPPORT_NCQ_STREAM;
1023 ata_ident->version_major = 0x3f0;
1024 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1025 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1026 ata_ident->support.command2 = (1 << 14);
1027 ata_ident->support.extension = (1 << 14);
1028 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1029 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1030 ata_ident->enabled.extension = (1 << 14);
1031 ata_ident->udmamodes = 0x7f;
1032 if (p->xfermode & ATA_UDMA0)
1033 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1034 ata_ident->transport_major = 0x1020;
1035 ata_ident->integrity = 0x00a5;
1038 int sectsz, psectsz, psectoff, candelete, ro;
1040 uint8_t sech, heads;
1042 ro = blockif_is_ro(p->bctx);
1043 candelete = blockif_candelete(p->bctx);
1044 sectsz = blockif_sectsz(p->bctx);
1045 sectors = blockif_size(p->bctx) / sectsz;
1046 blockif_chs(p->bctx, &cyl, &heads, &sech);
1047 blockif_psectsz(p->bctx, &psectsz, &psectoff);
1048 ata_ident->config = ATA_DRQ_FAST;
1049 ata_ident->cylinders = cyl;
1050 ata_ident->heads = heads;
1051 ata_ident->sectors = sech;
1053 ata_ident->sectors_intr = (0x8000 | 128);
1056 ata_ident->capabilities1 = ATA_SUPPORT_DMA |
1057 ATA_SUPPORT_LBA | ATA_SUPPORT_IORDY;
1058 ata_ident->capabilities2 = (1 << 14);
1059 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1060 if (p->mult_sectors)
1061 ata_ident->multi = (ATA_MULTI_VALID | p->mult_sectors);
1062 if (sectors <= 0x0fffffff) {
1063 ata_ident->lba_size_1 = sectors;
1064 ata_ident->lba_size_2 = (sectors >> 16);
1066 ata_ident->lba_size_1 = 0xffff;
1067 ata_ident->lba_size_2 = 0x0fff;
1069 ata_ident->mwdmamodes = 0x7;
1070 if (p->xfermode & ATA_WDMA0)
1071 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1072 ata_ident->apiomodes = 0x3;
1073 ata_ident->mwdmamin = 0x0078;
1074 ata_ident->mwdmarec = 0x0078;
1075 ata_ident->pioblind = 0x0078;
1076 ata_ident->pioiordy = 0x0078;
1077 ata_ident->support3 = 0;
1078 ata_ident->queue = 31;
1079 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
1081 ata_ident->satacapabilities2 = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
1082 (p->ssts & ATA_SS_SPD_MASK) >> 3);
1083 ata_ident->version_major = 0x3f0;
1084 ata_ident->version_minor = 0x28;
1085 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1086 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1087 ata_ident->support.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1088 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
1089 ata_ident->support.extension = (1 << 14);
1090 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1091 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1092 ata_ident->enabled.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1093 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
1094 ata_ident->enabled.extension = (1 << 14);
1095 ata_ident->udmamodes = 0x7f;
1096 if (p->xfermode & ATA_UDMA0)
1097 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1098 ata_ident->lba_size48_1 = sectors;
1099 ata_ident->lba_size48_2 = (sectors >> 16);
1100 ata_ident->lba_size48_3 = (sectors >> 32);
1101 ata_ident->lba_size48_4 = (sectors >> 48);
1103 if (candelete && !ro) {
1104 ata_ident->support3 |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
1105 ata_ident->max_dsm_blocks = 1;
1106 ata_ident->support_dsm = ATA_SUPPORT_DSM_TRIM;
1108 ata_ident->pss = ATA_PSS_VALID_VALUE;
1109 ata_ident->lsalign = 0x4000;
1110 if (psectsz > sectsz) {
1111 ata_ident->pss |= ATA_PSS_MULTLS;
1112 ata_ident->pss |= ffsl(psectsz / sectsz) - 1;
1113 ata_ident->lsalign |= (psectoff / sectsz);
1116 ata_ident->pss |= ATA_PSS_LSSABOVE512;
1117 ata_ident->lss_1 = sectsz / 2;
1118 ata_ident->lss_2 = ((sectsz / 2) >> 16);
1120 ata_ident->support2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1121 ata_ident->enabled2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1122 ata_ident->transport_major = 0x1020;
1123 ata_ident->integrity = 0x00a5;
1125 ahci_checksum((uint8_t*)ata_ident, sizeof(struct ata_params));
1129 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1132 ahci_write_fis_d2h(p, slot, cfis,
1133 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1135 ahci_write_fis_piosetup(p);
1136 write_prdt(p, slot, cfis, (void *)&p->ata_ident, sizeof(struct ata_params));
1137 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1142 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
1151 if (acmd[1] & 1) { /* VPD */
1152 if (acmd[2] == 0) { /* Supported VPD pages */
1160 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1162 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1163 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1164 ahci_write_fis_d2h(p, slot, cfis, tfd);
1176 atapi_string(buf + 8, "BHYVE", 8);
1177 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1178 atapi_string(buf + 32, "001", 4);
1184 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1185 write_prdt(p, slot, cfis, buf, len);
1186 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1190 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1195 sectors = blockif_size(p->bctx) / 2048;
1196 be32enc(buf, sectors - 1);
1197 be32enc(buf + 4, 2048);
1198 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1199 write_prdt(p, slot, cfis, buf, sizeof(buf));
1200 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1204 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1212 len = be16dec(acmd + 7);
1213 format = acmd[9] >> 6;
1220 uint8_t start_track, buf[20], *bp;
1222 msf = (acmd[1] >> 1) & 1;
1223 start_track = acmd[6];
1224 if (start_track > 1 && start_track != 0xaa) {
1226 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1228 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1229 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1230 ahci_write_fis_d2h(p, slot, cfis, tfd);
1236 if (start_track <= 1) {
1256 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1260 lba_to_msf(bp, sectors);
1263 be32enc(bp, sectors);
1267 be16enc(buf, size - 2);
1270 write_prdt(p, slot, cfis, buf, len);
1271 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1272 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1279 memset(buf, 0, sizeof(buf));
1283 if (len > sizeof(buf))
1285 write_prdt(p, slot, cfis, buf, len);
1286 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1287 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1295 uint8_t *bp, buf[50];
1297 msf = (acmd[1] >> 1) & 1;
1333 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1337 lba_to_msf(bp, sectors);
1340 be32enc(bp, sectors);
1363 be16enc(buf, size - 2);
1366 write_prdt(p, slot, cfis, buf, len);
1367 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1368 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1375 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1377 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1378 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1379 ahci_write_fis_d2h(p, slot, cfis, tfd);
1386 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1390 memset(buf, 0, sizeof(buf));
1393 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1394 write_prdt(p, slot, cfis, buf, sizeof(buf));
1395 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1399 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
1401 struct ahci_ioreq *aior;
1402 struct ahci_cmd_hdr *hdr;
1403 struct ahci_prdt_entry *prdt;
1404 struct blockif_req *breq;
1411 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1412 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1414 lba = be32dec(acmd + 2);
1415 if (acmd[0] == READ_10)
1416 len = be16dec(acmd + 7);
1418 len = be32dec(acmd + 6);
1420 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1421 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1427 * Pull request off free list
1429 aior = STAILQ_FIRST(&p->iofhd);
1430 assert(aior != NULL);
1431 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1437 breq = &aior->io_req;
1438 breq->br_offset = lba + done;
1439 ahci_build_iov(p, aior, prdt, hdr->prdtl);
1441 /* Mark this command in-flight. */
1442 p->pending |= 1 << slot;
1444 /* Stuff request onto busy list. */
1445 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1447 err = blockif_read(p->bctx, breq);
1452 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1460 if (len > sizeof(buf))
1462 memset(buf, 0, len);
1463 buf[0] = 0x70 | (1 << 7);
1464 buf[2] = p->sense_key;
1467 write_prdt(p, slot, cfis, buf, len);
1468 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1469 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1473 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1475 uint8_t *acmd = cfis + 0x40;
1478 switch (acmd[4] & 3) {
1482 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1483 tfd = ATA_S_READY | ATA_S_DSC;
1486 /* TODO eject media */
1487 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1488 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1490 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1493 ahci_write_fis_d2h(p, slot, cfis, tfd);
1497 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1505 len = be16dec(acmd + 7);
1507 code = acmd[2] & 0x3f;
1512 case MODEPAGE_RW_ERROR_RECOVERY:
1516 if (len > sizeof(buf))
1519 memset(buf, 0, sizeof(buf));
1520 be16enc(buf, 16 - 2);
1525 write_prdt(p, slot, cfis, buf, len);
1526 tfd = ATA_S_READY | ATA_S_DSC;
1529 case MODEPAGE_CD_CAPABILITIES:
1533 if (len > sizeof(buf))
1536 memset(buf, 0, sizeof(buf));
1537 be16enc(buf, 30 - 2);
1543 be16enc(&buf[18], 2);
1544 be16enc(&buf[20], 512);
1545 write_prdt(p, slot, cfis, buf, len);
1546 tfd = ATA_S_READY | ATA_S_DSC;
1555 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1557 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1562 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1564 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1567 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1568 ahci_write_fis_d2h(p, slot, cfis, tfd);
1572 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1580 /* we don't support asynchronous operation */
1581 if (!(acmd[1] & 1)) {
1582 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1584 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1589 len = be16dec(acmd + 7);
1590 if (len > sizeof(buf))
1593 memset(buf, 0, sizeof(buf));
1594 be16enc(buf, 8 - 2);
1598 write_prdt(p, slot, cfis, buf, len);
1599 tfd = ATA_S_READY | ATA_S_DSC;
1601 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1602 ahci_write_fis_d2h(p, slot, cfis, tfd);
1606 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1616 for (i = 0; i < 16; i++)
1617 DPRINTF("%02x ", acmd[i]);
1623 case TEST_UNIT_READY:
1624 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1625 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1628 atapi_inquiry(p, slot, cfis);
1631 atapi_read_capacity(p, slot, cfis);
1635 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1636 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1639 atapi_read_toc(p, slot, cfis);
1642 atapi_report_luns(p, slot, cfis);
1646 atapi_read(p, slot, cfis, 0);
1649 atapi_request_sense(p, slot, cfis);
1651 case START_STOP_UNIT:
1652 atapi_start_stop_unit(p, slot, cfis);
1655 atapi_mode_sense(p, slot, cfis);
1657 case GET_EVENT_STATUS_NOTIFICATION:
1658 atapi_get_event_status_notification(p, slot, cfis);
1661 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1662 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1664 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1665 ATA_S_READY | ATA_S_ERROR);
1671 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1674 p->tfd |= ATA_S_BUSY;
1676 case ATA_ATA_IDENTIFY:
1677 handle_identify(p, slot, cfis);
1679 case ATA_SETFEATURES:
1682 case ATA_SF_ENAB_SATA_SF:
1684 case ATA_SATA_SF_AN:
1685 p->tfd = ATA_S_DSC | ATA_S_READY;
1688 p->tfd = ATA_S_ERROR | ATA_S_READY;
1689 p->tfd |= (ATA_ERROR_ABORT << 8);
1693 case ATA_SF_ENAB_WCACHE:
1694 case ATA_SF_DIS_WCACHE:
1695 case ATA_SF_ENAB_RCACHE:
1696 case ATA_SF_DIS_RCACHE:
1697 p->tfd = ATA_S_DSC | ATA_S_READY;
1699 case ATA_SF_SETXFER:
1701 switch (cfis[12] & 0xf8) {
1707 p->xfermode = (cfis[12] & 0x7);
1710 p->tfd = ATA_S_DSC | ATA_S_READY;
1714 p->tfd = ATA_S_ERROR | ATA_S_READY;
1715 p->tfd |= (ATA_ERROR_ABORT << 8);
1718 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1722 if (cfis[12] != 0 &&
1723 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1724 p->tfd = ATA_S_ERROR | ATA_S_READY;
1725 p->tfd |= (ATA_ERROR_ABORT << 8);
1727 p->mult_sectors = cfis[12];
1728 p->tfd = ATA_S_DSC | ATA_S_READY;
1730 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1738 case ATA_READ_MUL48:
1739 case ATA_WRITE_MUL48:
1742 case ATA_READ_DMA48:
1743 case ATA_WRITE_DMA48:
1744 case ATA_READ_FPDMA_QUEUED:
1745 case ATA_WRITE_FPDMA_QUEUED:
1746 ahci_handle_rw(p, slot, cfis, 0);
1748 case ATA_FLUSHCACHE:
1749 case ATA_FLUSHCACHE48:
1750 ahci_handle_flush(p, slot, cfis);
1752 case ATA_DATA_SET_MANAGEMENT:
1753 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1754 cfis[13] == 0 && cfis[12] == 1) {
1755 ahci_handle_dsm_trim(p, slot, cfis, 0);
1758 ahci_write_fis_d2h(p, slot, cfis,
1759 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1761 case ATA_SEND_FPDMA_QUEUED:
1762 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1763 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1764 cfis[11] == 0 && cfis[3] == 1) {
1765 ahci_handle_dsm_trim(p, slot, cfis, 0);
1768 ahci_write_fis_d2h(p, slot, cfis,
1769 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1771 case ATA_READ_LOG_EXT:
1772 case ATA_READ_LOG_DMA_EXT:
1773 ahci_handle_read_log(p, slot, cfis);
1775 case ATA_SECURITY_FREEZE_LOCK:
1778 ahci_write_fis_d2h(p, slot, cfis,
1779 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1781 case ATA_CHECK_POWER_MODE:
1782 cfis[12] = 0xff; /* always on */
1783 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1785 case ATA_STANDBY_CMD:
1786 case ATA_STANDBY_IMMEDIATE:
1788 case ATA_IDLE_IMMEDIATE:
1790 case ATA_READ_VERIFY:
1791 case ATA_READ_VERIFY48:
1792 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1794 case ATA_ATAPI_IDENTIFY:
1795 handle_atapi_identify(p, slot, cfis);
1797 case ATA_PACKET_CMD:
1799 ahci_write_fis_d2h(p, slot, cfis,
1800 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1802 handle_packet_cmd(p, slot, cfis);
1805 WPRINTF("Unsupported cmd:%02x", cfis[2]);
1806 ahci_write_fis_d2h(p, slot, cfis,
1807 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1813 ahci_handle_slot(struct ahci_port *p, int slot)
1815 struct ahci_cmd_hdr *hdr;
1817 struct ahci_prdt_entry *prdt;
1819 struct pci_ahci_softc *sc;
1826 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1828 cfl = (hdr->flags & 0x1f) * 4;
1830 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1831 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1833 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1836 for (i = 0; i < cfl; i++) {
1839 DPRINTF("%02x ", cfis[i]);
1843 for (i = 0; i < hdr->prdtl; i++) {
1844 DPRINTF("%d@%08"PRIx64"", prdt->dbc & 0x3fffff, prdt->dba);
1849 if (cfis[0] != FIS_TYPE_REGH2D) {
1850 WPRINTF("Not a H2D FIS:%02x", cfis[0]);
1854 if (cfis[1] & 0x80) {
1855 ahci_handle_cmd(p, slot, cfis);
1857 if (cfis[15] & (1 << 2))
1859 else if (p->reset) {
1863 p->ci &= ~(1 << slot);
1868 ahci_handle_port(struct ahci_port *p)
1871 if (!(p->cmd & AHCI_P_CMD_ST))
1875 * Search for any new commands to issue ignoring those that
1876 * are already in-flight. Stop if device is busy or in error.
1878 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) {
1879 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0)
1881 if (p->waitforclear)
1883 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) {
1884 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1885 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT;
1886 ahci_handle_slot(p, p->ccs);
1892 * blockif callback routine - this runs in the context of the blockif
1893 * i/o thread, so the mutex needs to be acquired.
1896 ata_ioreq_cb(struct blockif_req *br, int err)
1898 struct ahci_cmd_hdr *hdr;
1899 struct ahci_ioreq *aior;
1900 struct ahci_port *p;
1901 struct pci_ahci_softc *sc;
1906 DPRINTF("%s %d", __func__, err);
1909 aior = br->br_param;
1914 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1916 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1917 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1918 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1920 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1921 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1922 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1925 pthread_mutex_lock(&sc->mtx);
1928 * Delete the blockif request from the busy list
1930 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1933 * Move the blockif request back to the free list
1935 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1938 hdr->prdbc = aior->done;
1940 if (!err && aior->more) {
1942 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1944 ahci_handle_rw(p, slot, cfis, aior->done);
1949 tfd = ATA_S_READY | ATA_S_DSC;
1951 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1953 ahci_write_fis_sdb(p, slot, cfis, tfd);
1955 ahci_write_fis_d2h(p, slot, cfis, tfd);
1958 * This command is now complete.
1960 p->pending &= ~(1 << slot);
1962 ahci_check_stopped(p);
1963 ahci_handle_port(p);
1965 pthread_mutex_unlock(&sc->mtx);
1966 DPRINTF("%s exit", __func__);
1970 atapi_ioreq_cb(struct blockif_req *br, int err)
1972 struct ahci_cmd_hdr *hdr;
1973 struct ahci_ioreq *aior;
1974 struct ahci_port *p;
1975 struct pci_ahci_softc *sc;
1980 DPRINTF("%s %d", __func__, err);
1982 aior = br->br_param;
1987 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1989 pthread_mutex_lock(&sc->mtx);
1992 * Delete the blockif request from the busy list
1994 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1997 * Move the blockif request back to the free list
1999 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
2002 hdr->prdbc = aior->done;
2004 if (!err && aior->more) {
2005 atapi_read(p, slot, cfis, aior->done);
2010 tfd = ATA_S_READY | ATA_S_DSC;
2012 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
2014 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
2016 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
2017 ahci_write_fis_d2h(p, slot, cfis, tfd);
2020 * This command is now complete.
2022 p->pending &= ~(1 << slot);
2024 ahci_check_stopped(p);
2025 ahci_handle_port(p);
2027 pthread_mutex_unlock(&sc->mtx);
2028 DPRINTF("%s exit", __func__);
2032 pci_ahci_ioreq_init(struct ahci_port *pr)
2034 struct ahci_ioreq *vr;
2037 pr->ioqsz = blockif_queuesz(pr->bctx);
2038 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
2039 STAILQ_INIT(&pr->iofhd);
2042 * Add all i/o request entries to the free queue
2044 for (i = 0; i < pr->ioqsz; i++) {
2048 vr->io_req.br_callback = ata_ioreq_cb;
2050 vr->io_req.br_callback = atapi_ioreq_cb;
2051 vr->io_req.br_param = vr;
2052 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
2055 TAILQ_INIT(&pr->iobhd);
2059 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2061 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2062 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2063 struct ahci_port *p = &sc->port[port];
2065 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2066 port, offset, value);
2086 p->ie = value & 0xFDC000FF;
2091 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2092 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2093 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2094 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK);
2095 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2096 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2097 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2098 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value;
2100 if (!(value & AHCI_P_CMD_ST)) {
2105 p->cmd |= AHCI_P_CMD_CR;
2106 clb = (uint64_t)p->clbu << 32 | p->clb;
2107 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
2108 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
2111 if (value & AHCI_P_CMD_FRE) {
2114 p->cmd |= AHCI_P_CMD_FR;
2115 fb = (uint64_t)p->fbu << 32 | p->fb;
2116 /* we don't support FBSCP, so rfis size is 256Bytes */
2117 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
2119 p->cmd &= ~AHCI_P_CMD_FR;
2122 if (value & AHCI_P_CMD_CLO) {
2123 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ);
2124 p->cmd &= ~AHCI_P_CMD_CLO;
2127 if (value & AHCI_P_CMD_ICC_MASK) {
2128 p->cmd &= ~AHCI_P_CMD_ICC_MASK;
2131 ahci_handle_port(p);
2137 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"", offset);
2141 if (!(p->cmd & AHCI_P_CMD_ST)) {
2142 if (value & ATA_SC_DET_RESET)
2154 ahci_handle_port(p);
2164 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2166 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2174 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"", offset);
2177 if (value & AHCI_GHC_HR) {
2181 if (value & AHCI_GHC_IE)
2182 sc->ghc |= AHCI_GHC_IE;
2184 sc->ghc &= ~AHCI_GHC_IE;
2185 ahci_generate_intr(sc, 0xffffffff);
2189 ahci_generate_intr(sc, value);
2197 pci_ahci_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
2200 struct pci_ahci_softc *sc = pi->pi_arg;
2202 assert(baridx == 5);
2203 assert((offset % 4) == 0 && size == 4);
2205 pthread_mutex_lock(&sc->mtx);
2207 if (offset < AHCI_OFFSET)
2208 pci_ahci_host_write(sc, offset, value);
2209 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP)
2210 pci_ahci_port_write(sc, offset, value);
2212 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"", offset);
2214 pthread_mutex_unlock(&sc->mtx);
2218 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2234 uint32_t *p = &sc->cap;
2235 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2243 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x",
2250 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2253 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2254 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2274 uint32_t *p= &sc->port[port].clb;
2275 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2284 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x",
2285 port, offset, value);
2291 pci_ahci_read(struct pci_devinst *pi, int baridx, uint64_t regoff, int size)
2293 struct pci_ahci_softc *sc = pi->pi_arg;
2297 assert(baridx == 5);
2298 assert(size == 1 || size == 2 || size == 4);
2299 assert((regoff & (size - 1)) == 0);
2301 pthread_mutex_lock(&sc->mtx);
2303 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */
2304 if (offset < AHCI_OFFSET)
2305 value = pci_ahci_host_read(sc, offset);
2306 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP)
2307 value = pci_ahci_port_read(sc, offset);
2310 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"",
2313 value >>= 8 * (regoff & 0x3);
2315 pthread_mutex_unlock(&sc->mtx);
2321 * Each AHCI controller has a "port" node which contains nodes for
2322 * each port named after the decimal number of the port (no leading
2323 * zeroes). Port nodes contain a "type" ("hd" or "cd"), as well as
2324 * options for blockif. For example:
2331 * .path="/path/to/image"
2334 pci_ahci_legacy_config_port(nvlist_t *nvl, int port, const char *type,
2337 char node_name[sizeof("XX")];
2340 snprintf(node_name, sizeof(node_name), "%d", port);
2341 port_nvl = create_relative_config_node(nvl, node_name);
2342 set_config_value_node(port_nvl, "type", type);
2343 return (blockif_legacy_config(port_nvl, opts));
2347 pci_ahci_legacy_config(nvlist_t *nvl, const char *opts)
2349 nvlist_t *ports_nvl;
2351 char *next, *next2, *str, *tofree;
2357 ports_nvl = create_relative_config_node(nvl, "port");
2359 tofree = str = strdup(opts);
2360 for (p = 0; p < MAX_PORTS && str != NULL; p++, str = next) {
2361 /* Identify and cut off type of present port. */
2362 if (strncmp(str, "hd:", 3) == 0) {
2365 } else if (strncmp(str, "cd:", 3) == 0) {
2371 /* Find and cut off the next port options. */
2372 next = strstr(str, ",hd:");
2373 next2 = strstr(str, ",cd:");
2374 if (next == NULL || (next2 != NULL && next2 < next))
2385 EPRINTLN("Missing or invalid type for port %d: \"%s\"",
2390 if (pci_ahci_legacy_config_port(ports_nvl, p, type, str) != 0)
2400 pci_ahci_cd_legacy_config(nvlist_t *nvl, const char *opts)
2402 nvlist_t *ports_nvl;
2404 ports_nvl = create_relative_config_node(nvl, "port");
2405 return (pci_ahci_legacy_config_port(ports_nvl, 0, "cd", opts));
2409 pci_ahci_hd_legacy_config(nvlist_t *nvl, const char *opts)
2411 nvlist_t *ports_nvl;
2413 ports_nvl = create_relative_config_node(nvl, "port");
2414 return (pci_ahci_legacy_config_port(ports_nvl, 0, "hd", opts));
2418 pci_ahci_init(struct pci_devinst *pi, nvlist_t *nvl)
2420 char bident[sizeof("XXX:XXX:XXX")];
2421 char node_name[sizeof("XX")];
2422 struct blockif_ctxt *bctxt;
2423 struct pci_ahci_softc *sc;
2424 int atapi, ret, slots, p;
2427 const char *path, *type, *value;
2428 nvlist_t *ports_nvl, *port_nvl;
2433 dbg = fopen("/tmp/log", "w+");
2436 sc = calloc(1, sizeof(struct pci_ahci_softc));
2439 pthread_mutex_init(&sc->mtx, NULL);
2444 ports_nvl = find_relative_config_node(nvl, "port");
2445 for (p = 0; ports_nvl != NULL && p < MAX_PORTS; p++) {
2446 struct ata_params *ata_ident = &sc->port[p].ata_ident;
2447 char ident[AHCI_PORT_IDENT];
2449 snprintf(node_name, sizeof(node_name), "%d", p);
2450 port_nvl = find_relative_config_node(ports_nvl, node_name);
2451 if (port_nvl == NULL)
2454 type = get_config_value_node(port_nvl, "type");
2458 if (strcmp(type, "hd") == 0)
2464 * Attempt to open the backing image. Use the PCI slot/func
2465 * and the port number for the identifier string.
2467 snprintf(bident, sizeof(bident), "%u:%u:%u", pi->pi_slot,
2470 bctxt = blockif_open(port_nvl, bident);
2471 if (bctxt == NULL) {
2477 ret = blockif_add_boot_device(pi, bctxt);
2483 sc->port[p].bctx = bctxt;
2484 sc->port[p].pr_sc = sc;
2485 sc->port[p].port = p;
2486 sc->port[p].atapi = atapi;
2489 * Create an identifier for the backing file.
2490 * Use parts of the md5 sum of the filename
2492 path = get_config_value_node(port_nvl, "path");
2494 MD5Update(&mdctx, path, strlen(path));
2495 MD5Final(digest, &mdctx);
2496 snprintf(ident, AHCI_PORT_IDENT,
2497 "BHYVE-%02X%02X-%02X%02X-%02X%02X",
2498 digest[0], digest[1], digest[2], digest[3], digest[4],
2501 memset(ata_ident, 0, sizeof(struct ata_params));
2502 ata_string((uint8_t*)&ata_ident->serial, ident, 20);
2503 ata_string((uint8_t*)&ata_ident->revision, "001", 8);
2505 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DVD ROM", 40);
2507 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DISK", 40);
2508 value = get_config_value_node(port_nvl, "nmrr");
2510 ata_ident->media_rotation_rate = atoi(value);
2511 value = get_config_value_node(port_nvl, "ser");
2513 ata_string((uint8_t*)(&ata_ident->serial), value, 20);
2514 value = get_config_value_node(port_nvl, "rev");
2516 ata_string((uint8_t*)(&ata_ident->revision), value, 8);
2517 value = get_config_value_node(port_nvl, "model");
2519 ata_string((uint8_t*)(&ata_ident->model), value, 40);
2520 ata_identify_init(&sc->port[p], atapi);
2523 * Allocate blockif request structures and add them
2526 pci_ahci_ioreq_init(&sc->port[p]);
2529 if (sc->port[p].ioqsz < slots)
2530 slots = sc->port[p].ioqsz;
2534 /* Intel ICH8 AHCI */
2536 if (sc->ports < DEF_PORTS)
2537 sc->ports = DEF_PORTS;
2538 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2539 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2540 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2541 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2542 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2545 sc->cap2 = AHCI_CAP2_APST;
2548 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2549 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2550 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2551 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2552 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2553 p = MIN(sc->ports, 16);
2554 p = flsl(p) - ((p & (p - 1)) ? 0 : 1);
2555 pci_emul_add_msicap(pi, 1 << p);
2556 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2557 AHCI_OFFSET + sc->ports * AHCI_STEP);
2559 pci_lintr_request(pi);
2563 for (p = 0; p < sc->ports; p++) {
2564 if (sc->port[p].bctx != NULL)
2565 blockif_close(sc->port[p].bctx);
2573 #ifdef BHYVE_SNAPSHOT
2575 pci_ahci_snapshot(struct vm_snapshot_meta *meta)
2579 struct pci_devinst *pi;
2580 struct pci_ahci_softc *sc;
2581 struct ahci_port *port;
2583 pi = meta->dev_data;
2586 /* TODO: add mtx lock/unlock */
2588 SNAPSHOT_VAR_OR_LEAVE(sc->ports, meta, ret, done);
2589 SNAPSHOT_VAR_OR_LEAVE(sc->cap, meta, ret, done);
2590 SNAPSHOT_VAR_OR_LEAVE(sc->ghc, meta, ret, done);
2591 SNAPSHOT_VAR_OR_LEAVE(sc->is, meta, ret, done);
2592 SNAPSHOT_VAR_OR_LEAVE(sc->pi, meta, ret, done);
2593 SNAPSHOT_VAR_OR_LEAVE(sc->vs, meta, ret, done);
2594 SNAPSHOT_VAR_OR_LEAVE(sc->ccc_ctl, meta, ret, done);
2595 SNAPSHOT_VAR_OR_LEAVE(sc->ccc_pts, meta, ret, done);
2596 SNAPSHOT_VAR_OR_LEAVE(sc->em_loc, meta, ret, done);
2597 SNAPSHOT_VAR_OR_LEAVE(sc->em_ctl, meta, ret, done);
2598 SNAPSHOT_VAR_OR_LEAVE(sc->cap2, meta, ret, done);
2599 SNAPSHOT_VAR_OR_LEAVE(sc->bohc, meta, ret, done);
2600 SNAPSHOT_VAR_OR_LEAVE(sc->lintr, meta, ret, done);
2602 for (i = 0; i < MAX_PORTS; i++) {
2603 port = &sc->port[i];
2605 if (meta->op == VM_SNAPSHOT_SAVE)
2608 SNAPSHOT_VAR_OR_LEAVE(bctx, meta, ret, done);
2609 SNAPSHOT_VAR_OR_LEAVE(port->port, meta, ret, done);
2611 /* Mostly for restore; save is ensured by the lines above. */
2612 if (((bctx == NULL) && (port->bctx != NULL)) ||
2613 ((bctx != NULL) && (port->bctx == NULL))) {
2614 fprintf(stderr, "%s: ports not matching\r\n", __func__);
2619 if (port->bctx == NULL)
2622 if (port->port != i) {
2623 fprintf(stderr, "%s: ports not matching: "
2624 "actual: %d expected: %d\r\n",
2625 __func__, port->port, i);
2630 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, port->cmd_lst,
2631 AHCI_CL_SIZE * AHCI_MAX_SLOTS, false, meta, ret, done);
2632 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, port->rfis, 256,
2633 false, meta, ret, done);
2635 SNAPSHOT_VAR_OR_LEAVE(port->ata_ident, meta, ret, done);
2636 SNAPSHOT_VAR_OR_LEAVE(port->atapi, meta, ret, done);
2637 SNAPSHOT_VAR_OR_LEAVE(port->reset, meta, ret, done);
2638 SNAPSHOT_VAR_OR_LEAVE(port->waitforclear, meta, ret, done);
2639 SNAPSHOT_VAR_OR_LEAVE(port->mult_sectors, meta, ret, done);
2640 SNAPSHOT_VAR_OR_LEAVE(port->xfermode, meta, ret, done);
2641 SNAPSHOT_VAR_OR_LEAVE(port->err_cfis, meta, ret, done);
2642 SNAPSHOT_VAR_OR_LEAVE(port->sense_key, meta, ret, done);
2643 SNAPSHOT_VAR_OR_LEAVE(port->asc, meta, ret, done);
2644 SNAPSHOT_VAR_OR_LEAVE(port->ccs, meta, ret, done);
2645 SNAPSHOT_VAR_OR_LEAVE(port->pending, meta, ret, done);
2647 SNAPSHOT_VAR_OR_LEAVE(port->clb, meta, ret, done);
2648 SNAPSHOT_VAR_OR_LEAVE(port->clbu, meta, ret, done);
2649 SNAPSHOT_VAR_OR_LEAVE(port->fb, meta, ret, done);
2650 SNAPSHOT_VAR_OR_LEAVE(port->fbu, meta, ret, done);
2651 SNAPSHOT_VAR_OR_LEAVE(port->ie, meta, ret, done);
2652 SNAPSHOT_VAR_OR_LEAVE(port->cmd, meta, ret, done);
2653 SNAPSHOT_VAR_OR_LEAVE(port->unused0, meta, ret, done);
2654 SNAPSHOT_VAR_OR_LEAVE(port->tfd, meta, ret, done);
2655 SNAPSHOT_VAR_OR_LEAVE(port->sig, meta, ret, done);
2656 SNAPSHOT_VAR_OR_LEAVE(port->ssts, meta, ret, done);
2657 SNAPSHOT_VAR_OR_LEAVE(port->sctl, meta, ret, done);
2658 SNAPSHOT_VAR_OR_LEAVE(port->serr, meta, ret, done);
2659 SNAPSHOT_VAR_OR_LEAVE(port->sact, meta, ret, done);
2660 SNAPSHOT_VAR_OR_LEAVE(port->ci, meta, ret, done);
2661 SNAPSHOT_VAR_OR_LEAVE(port->sntf, meta, ret, done);
2662 SNAPSHOT_VAR_OR_LEAVE(port->fbs, meta, ret, done);
2663 SNAPSHOT_VAR_OR_LEAVE(port->ioqsz, meta, ret, done);
2665 assert(TAILQ_EMPTY(&port->iobhd));
2673 pci_ahci_pause(struct pci_devinst *pi)
2675 struct pci_ahci_softc *sc;
2676 struct blockif_ctxt *bctxt;
2681 for (i = 0; i < MAX_PORTS; i++) {
2682 bctxt = sc->port[i].bctx;
2686 blockif_pause(bctxt);
2693 pci_ahci_resume(struct pci_devinst *pi)
2695 struct pci_ahci_softc *sc;
2696 struct blockif_ctxt *bctxt;
2701 for (i = 0; i < MAX_PORTS; i++) {
2702 bctxt = sc->port[i].bctx;
2706 blockif_resume(bctxt);
2711 #endif /* BHYVE_SNAPSHOT */
2714 * Use separate emulation names to distinguish drive and atapi devices
2716 static const struct pci_devemu pci_de_ahci = {
2718 .pe_init = pci_ahci_init,
2719 .pe_legacy_config = pci_ahci_legacy_config,
2720 .pe_barwrite = pci_ahci_write,
2721 .pe_barread = pci_ahci_read,
2722 #ifdef BHYVE_SNAPSHOT
2723 .pe_snapshot = pci_ahci_snapshot,
2724 .pe_pause = pci_ahci_pause,
2725 .pe_resume = pci_ahci_resume,
2728 PCI_EMUL_SET(pci_de_ahci);
2730 static const struct pci_devemu pci_de_ahci_hd = {
2731 .pe_emu = "ahci-hd",
2732 .pe_legacy_config = pci_ahci_hd_legacy_config,
2735 PCI_EMUL_SET(pci_de_ahci_hd);
2737 static const struct pci_devemu pci_de_ahci_cd = {
2738 .pe_emu = "ahci-cd",
2739 .pe_legacy_config = pci_ahci_cd_legacy_config,
2742 PCI_EMUL_SET(pci_de_ahci_cd);