2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/linker_set.h>
39 #include <sys/ioctl.h>
42 #include <sys/endian.h>
54 #include <pthread_np.h>
68 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
69 #define MAX_PORTS 32 /* AHCI supports 32 ports */
71 #define PxSIG_ATA 0x00000101 /* ATA drive */
72 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
75 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
76 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
77 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
78 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
79 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
80 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
81 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
82 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
88 #define TEST_UNIT_READY 0x00
89 #define REQUEST_SENSE 0x03
91 #define START_STOP_UNIT 0x1B
92 #define PREVENT_ALLOW 0x1E
93 #define READ_CAPACITY 0x25
95 #define POSITION_TO_ELEMENT 0x2B
97 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
98 #define MODE_SENSE_10 0x5A
99 #define REPORT_LUNS 0xA0
104 * SCSI mode page codes
106 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
107 #define MODEPAGE_CD_CAPABILITIES 0x2A
112 #define ATA_SF_ENAB_SATA_SF 0x10
113 #define ATA_SATA_SF_AN 0x05
114 #define ATA_SF_DIS_SATA_SF 0x90
121 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
123 #define DPRINTF(format, arg...)
125 #define WPRINTF(format, arg...) printf(format, ##arg)
127 #define AHCI_PORT_IDENT 20 + 1
130 struct blockif_req io_req;
131 struct ahci_port *io_pr;
132 STAILQ_ENTRY(ahci_ioreq) io_flist;
133 TAILQ_ENTRY(ahci_ioreq) io_blist;
143 struct blockif_ctxt *bctx;
144 struct pci_ahci_softc *pr_sc;
145 struct ata_params ata_ident;
154 uint8_t err_cfis[20];
181 struct ahci_ioreq *ioreq;
183 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
184 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
187 struct ahci_cmd_hdr {
192 uint32_t reserved[4];
195 struct ahci_prdt_entry {
198 #define DBCMASK 0x3fffff
202 struct pci_ahci_softc {
203 struct pci_devinst *asc_pi;
218 struct ahci_port port[MAX_PORTS];
220 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
222 static void ahci_handle_port(struct ahci_port *p);
224 static inline void lba_to_msf(uint8_t *buf, int lba)
227 buf[0] = (lba / 75) / 60;
228 buf[1] = (lba / 75) % 60;
233 * Generate HBA interrupts on global IS register write.
236 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask)
238 struct pci_devinst *pi = sc->asc_pi;
243 /* Update global IS from PxIS/PxIE. */
244 for (i = 0; i < sc->ports; i++) {
249 DPRINTF("%s(%08x) %08x", __func__, mask, sc->is);
251 /* If there is nothing enabled -- clear legacy interrupt and exit. */
252 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) {
254 pci_lintr_deassert(pi);
260 /* If there is anything and no MSI -- assert legacy interrupt. */
261 nmsg = pci_msi_maxmsgnum(pi);
265 pci_lintr_assert(pi);
270 /* Assert respective MSIs for ports that were touched. */
271 for (i = 0; i < nmsg; i++) {
272 if (sc->ports <= nmsg || i < nmsg - 1)
275 mmask = 0xffffffff << i;
276 if (sc->is & mask && mmask & mask)
277 pci_generate_msi(pi, i);
282 * Generate HBA interrupt on specific port event.
285 ahci_port_intr(struct ahci_port *p)
287 struct pci_ahci_softc *sc = p->pr_sc;
288 struct pci_devinst *pi = sc->asc_pi;
291 DPRINTF("%s(%d) %08x/%08x %08x", __func__,
292 p->port, p->is, p->ie, sc->is);
294 /* If there is nothing enabled -- we are done. */
295 if ((p->is & p->ie) == 0)
298 /* In case of non-shared MSI always generate interrupt. */
299 nmsg = pci_msi_maxmsgnum(pi);
300 if (sc->ports <= nmsg || p->port < nmsg - 1) {
301 sc->is |= (1 << p->port);
302 if ((sc->ghc & AHCI_GHC_IE) == 0)
304 pci_generate_msi(pi, p->port);
308 /* If IS for this port is already set -- do nothing. */
309 if (sc->is & (1 << p->port))
312 sc->is |= (1 << p->port);
314 /* If interrupts are enabled -- generate one. */
315 if ((sc->ghc & AHCI_GHC_IE) == 0)
318 pci_generate_msi(pi, nmsg - 1);
319 } else if (!sc->lintr) {
321 pci_lintr_assert(pi);
326 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
328 int offset, len, irq;
330 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
334 case FIS_TYPE_REGD2H:
337 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0;
339 case FIS_TYPE_SETDEVBITS:
342 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0;
344 case FIS_TYPE_PIOSETUP:
347 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
350 WPRINTF("unsupported fis type %d", ft);
353 if (fis[2] & ATA_S_ERROR) {
355 irq |= AHCI_P_IX_TFE;
357 memcpy(p->rfis + offset, fis, len);
367 ahci_write_fis_piosetup(struct ahci_port *p)
371 memset(fis, 0, sizeof(fis));
372 fis[0] = FIS_TYPE_PIOSETUP;
373 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
377 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
382 error = (tfd >> 8) & 0xff;
384 memset(fis, 0, sizeof(fis));
385 fis[0] = FIS_TYPE_SETDEVBITS;
389 if (fis[2] & ATA_S_ERROR) {
390 p->err_cfis[0] = slot;
391 p->err_cfis[2] = tfd;
392 p->err_cfis[3] = error;
393 memcpy(&p->err_cfis[4], cfis + 4, 16);
395 *(uint32_t *)(fis + 4) = (1 << slot);
396 p->sact &= ~(1 << slot);
400 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
404 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
409 error = (tfd >> 8) & 0xff;
410 memset(fis, 0, sizeof(fis));
411 fis[0] = FIS_TYPE_REGD2H;
425 if (fis[2] & ATA_S_ERROR) {
426 p->err_cfis[0] = 0x80;
427 p->err_cfis[2] = tfd & 0xff;
428 p->err_cfis[3] = error;
429 memcpy(&p->err_cfis[4], cfis + 4, 16);
431 p->ci &= ~(1 << slot);
433 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
437 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot)
441 p->tfd = ATA_S_READY | ATA_S_DSC;
442 memset(fis, 0, sizeof(fis));
443 fis[0] = FIS_TYPE_REGD2H;
444 fis[1] = 0; /* No interrupt */
445 fis[2] = p->tfd; /* Status */
446 fis[3] = 0; /* No error */
447 p->ci &= ~(1 << slot);
448 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
452 ahci_write_reset_fis_d2h(struct ahci_port *p)
456 memset(fis, 0, sizeof(fis));
457 fis[0] = FIS_TYPE_REGD2H;
465 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
469 ahci_check_stopped(struct ahci_port *p)
472 * If we are no longer processing the command list and nothing
473 * is in-flight, clear the running bit, the current command
474 * slot, the command issue and active bits.
476 if (!(p->cmd & AHCI_P_CMD_ST)) {
477 if (p->pending == 0) {
479 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
488 ahci_port_stop(struct ahci_port *p)
490 struct ahci_ioreq *aior;
495 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
497 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
499 * Try to cancel the outstanding blockif request.
501 error = blockif_cancel(p->bctx, &aior->io_req);
507 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
508 cfis[2] == ATA_READ_FPDMA_QUEUED ||
509 cfis[2] == ATA_SEND_FPDMA_QUEUED)
510 p->sact &= ~(1 << slot); /* NCQ */
512 p->ci &= ~(1 << slot);
515 * This command is now done.
517 p->pending &= ~(1 << slot);
520 * Delete the blockif request from the busy list
522 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
525 * Move the blockif request back to the free list
527 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
530 ahci_check_stopped(p);
534 ahci_port_reset(struct ahci_port *pr)
538 pr->xfermode = ATA_UDMA6;
539 pr->mult_sectors = 128;
542 pr->ssts = ATA_SS_DET_NO_DEVICE;
543 pr->sig = 0xFFFFFFFF;
547 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
548 if (pr->sctl & ATA_SC_SPD_MASK)
549 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
551 pr->ssts |= ATA_SS_SPD_GEN3;
552 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
555 pr->tfd |= ATA_S_READY;
557 pr->sig = PxSIG_ATAPI;
558 ahci_write_reset_fis_d2h(pr);
562 ahci_reset(struct pci_ahci_softc *sc)
566 sc->ghc = AHCI_GHC_AE;
570 pci_lintr_deassert(sc->asc_pi);
574 for (i = 0; i < sc->ports; i++) {
577 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD);
578 if (sc->port[i].bctx)
579 sc->port[i].cmd |= AHCI_P_CMD_CPS;
580 sc->port[i].sctl = 0;
581 ahci_port_reset(&sc->port[i]);
586 ata_string(uint8_t *dest, const char *src, int len)
590 for (i = 0; i < len; i++) {
592 dest[i ^ 1] = *src++;
599 atapi_string(uint8_t *dest, const char *src, int len)
603 for (i = 0; i < len; i++) {
612 * Build up the iovec based on the PRDT, 'done' and 'len'.
615 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior,
616 struct ahci_prdt_entry *prdt, uint16_t prdtl)
618 struct blockif_req *breq = &aior->io_req;
619 uint32_t dbcsz, extra, left, skip, todo;
622 assert(aior->len >= aior->done);
624 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */
626 left = aior->len - aior->done;
628 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0;
630 dbcsz = (prdt->dbc & DBCMASK) + 1;
631 /* Skip already done part of the PRDT */
639 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc),
640 prdt->dba + skip, dbcsz);
641 breq->br_iov[j].iov_len = dbcsz;
648 /* If we got limited by IOV length, round I/O down to sector size. */
649 if (j == BLOCKIF_IOV_MAX) {
650 extra = todo % blockif_sectsz(p->bctx);
654 if (breq->br_iov[j - 1].iov_len > extra) {
655 breq->br_iov[j - 1].iov_len -= extra;
658 extra -= breq->br_iov[j - 1].iov_len;
664 breq->br_resid = todo;
666 aior->more = (aior->done < aior->len && i < prdtl);
670 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
672 struct ahci_ioreq *aior;
673 struct blockif_req *breq;
674 struct ahci_prdt_entry *prdt;
675 struct ahci_cmd_hdr *hdr;
678 int err, first, ncq, readop;
680 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
681 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
686 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
687 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
688 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
689 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
692 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
693 cfis[2] == ATA_READ_FPDMA_QUEUED) {
694 lba = ((uint64_t)cfis[10] << 40) |
695 ((uint64_t)cfis[9] << 32) |
696 ((uint64_t)cfis[8] << 24) |
697 ((uint64_t)cfis[6] << 16) |
698 ((uint64_t)cfis[5] << 8) |
700 len = cfis[11] << 8 | cfis[3];
704 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
705 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
706 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
707 lba = ((uint64_t)cfis[10] << 40) |
708 ((uint64_t)cfis[9] << 32) |
709 ((uint64_t)cfis[8] << 24) |
710 ((uint64_t)cfis[6] << 16) |
711 ((uint64_t)cfis[5] << 8) |
713 len = cfis[13] << 8 | cfis[12];
717 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
718 (cfis[5] << 8) | cfis[4];
723 lba *= blockif_sectsz(p->bctx);
724 len *= blockif_sectsz(p->bctx);
726 /* Pull request off free list */
727 aior = STAILQ_FIRST(&p->iofhd);
728 assert(aior != NULL);
729 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
735 aior->readop = readop;
736 breq = &aior->io_req;
737 breq->br_offset = lba + done;
738 ahci_build_iov(p, aior, prdt, hdr->prdtl);
740 /* Mark this command in-flight. */
741 p->pending |= 1 << slot;
743 /* Stuff request onto busy list. */
744 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
747 ahci_write_fis_d2h_ncq(p, slot);
750 err = blockif_read(p->bctx, breq);
752 err = blockif_write(p->bctx, breq);
757 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
759 struct ahci_ioreq *aior;
760 struct blockif_req *breq;
764 * Pull request off free list
766 aior = STAILQ_FIRST(&p->iofhd);
767 assert(aior != NULL);
768 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
774 breq = &aior->io_req;
777 * Mark this command in-flight.
779 p->pending |= 1 << slot;
782 * Stuff request onto busy list
784 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
786 err = blockif_flush(p->bctx, breq);
791 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf,
794 struct ahci_cmd_hdr *hdr;
795 struct ahci_prdt_entry *prdt;
800 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
803 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
804 for (i = 0; i < hdr->prdtl && len; i++) {
809 dbcsz = (prdt->dbc & DBCMASK) + 1;
810 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
811 sublen = MIN(len, dbcsz);
812 memcpy(to, ptr, sublen);
820 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
822 struct ahci_ioreq *aior;
823 struct blockif_req *breq;
831 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
832 len = (uint16_t)cfis[13] << 8 | cfis[12];
835 } else { /* ATA_SEND_FPDMA_QUEUED */
836 len = (uint16_t)cfis[11] << 8 | cfis[3];
840 read_prdt(p, slot, cfis, buf, sizeof(buf));
844 elba = ((uint64_t)entry[5] << 40) |
845 ((uint64_t)entry[4] << 32) |
846 ((uint64_t)entry[3] << 24) |
847 ((uint64_t)entry[2] << 16) |
848 ((uint64_t)entry[1] << 8) |
850 elen = (uint16_t)entry[7] << 8 | entry[6];
856 ahci_write_fis_d2h_ncq(p, slot);
857 ahci_write_fis_sdb(p, slot, cfis,
858 ATA_S_READY | ATA_S_DSC);
860 ahci_write_fis_d2h(p, slot, cfis,
861 ATA_S_READY | ATA_S_DSC);
863 p->pending &= ~(1 << slot);
864 ahci_check_stopped(p);
873 * Pull request off free list
875 aior = STAILQ_FIRST(&p->iofhd);
876 assert(aior != NULL);
877 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
882 aior->more = (len != done);
884 breq = &aior->io_req;
885 breq->br_offset = elba * blockif_sectsz(p->bctx);
886 breq->br_resid = elen * blockif_sectsz(p->bctx);
889 * Mark this command in-flight.
891 p->pending |= 1 << slot;
894 * Stuff request onto busy list
896 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
899 ahci_write_fis_d2h_ncq(p, slot);
901 err = blockif_delete(p->bctx, breq);
906 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf,
909 struct ahci_cmd_hdr *hdr;
910 struct ahci_prdt_entry *prdt;
915 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
918 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
919 for (i = 0; i < hdr->prdtl && len; i++) {
924 dbcsz = (prdt->dbc & DBCMASK) + 1;
925 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
926 sublen = MIN(len, dbcsz);
927 memcpy(ptr, from, sublen);
932 hdr->prdbc = size - len;
936 ahci_checksum(uint8_t *buf, int size)
941 for (i = 0; i < size - 1; i++)
943 buf[size - 1] = 0x100 - sum;
947 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
949 struct ahci_cmd_hdr *hdr;
951 uint8_t *buf8 = (uint8_t *)buf;
952 uint16_t *buf16 = (uint16_t *)buf;
954 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
955 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 ||
956 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
957 ahci_write_fis_d2h(p, slot, cfis,
958 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
962 memset(buf, 0, sizeof(buf));
963 if (cfis[4] == 0x00) { /* Log directory */
964 buf16[0x00] = 1; /* Version -- 1 */
965 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */
966 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */
967 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */
968 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis));
969 ahci_checksum(buf8, sizeof(buf));
970 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */
971 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) {
972 buf[0x00] = 1; /* SFQ DSM supported */
973 buf[0x01] = 1; /* SFQ DSM TRIM supported */
976 ahci_write_fis_d2h(p, slot, cfis,
977 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
981 if (cfis[2] == ATA_READ_LOG_EXT)
982 ahci_write_fis_piosetup(p);
983 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
984 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
988 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
990 struct ahci_cmd_hdr *hdr;
992 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
993 if (p->atapi || hdr->prdtl == 0) {
994 ahci_write_fis_d2h(p, slot, cfis,
995 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
997 ahci_write_fis_piosetup(p);
998 write_prdt(p, slot, cfis, (void*)&p->ata_ident, sizeof(struct ata_params));
999 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1004 ata_identify_init(struct ahci_port* p, int atapi)
1006 struct ata_params* ata_ident = &p->ata_ident;
1009 ata_ident->config = ATA_PROTO_ATAPI | ATA_ATAPI_TYPE_CDROM |
1010 ATA_ATAPI_REMOVABLE | ATA_DRQ_FAST;
1011 ata_ident->capabilities1 = ATA_SUPPORT_LBA |
1013 ata_ident->capabilities2 = (1 << 14 | 1);
1014 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1015 ata_ident->obsolete62 = 0x3f;
1016 ata_ident->mwdmamodes = 7;
1017 if (p->xfermode & ATA_WDMA0)
1018 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1019 ata_ident->apiomodes = 3;
1020 ata_ident->mwdmamin = 0x0078;
1021 ata_ident->mwdmarec = 0x0078;
1022 ata_ident->pioblind = 0x0078;
1023 ata_ident->pioiordy = 0x0078;
1024 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
1025 ata_ident->satacapabilities2 = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
1026 ata_ident->satasupport = ATA_SUPPORT_NCQ_STREAM;
1027 ata_ident->version_major = 0x3f0;
1028 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1029 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1030 ata_ident->support.command2 = (1 << 14);
1031 ata_ident->support.extension = (1 << 14);
1032 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1033 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1034 ata_ident->enabled.extension = (1 << 14);
1035 ata_ident->udmamodes = 0x7f;
1036 if (p->xfermode & ATA_UDMA0)
1037 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1038 ata_ident->transport_major = 0x1020;
1039 ata_ident->integrity = 0x00a5;
1042 int sectsz, psectsz, psectoff, candelete, ro;
1044 uint8_t sech, heads;
1046 ro = blockif_is_ro(p->bctx);
1047 candelete = blockif_candelete(p->bctx);
1048 sectsz = blockif_sectsz(p->bctx);
1049 sectors = blockif_size(p->bctx) / sectsz;
1050 blockif_chs(p->bctx, &cyl, &heads, &sech);
1051 blockif_psectsz(p->bctx, &psectsz, &psectoff);
1052 ata_ident->config = ATA_DRQ_FAST;
1053 ata_ident->cylinders = cyl;
1054 ata_ident->heads = heads;
1055 ata_ident->sectors = sech;
1057 ata_ident->sectors_intr = (0x8000 | 128);
1060 ata_ident->capabilities1 = ATA_SUPPORT_DMA |
1061 ATA_SUPPORT_LBA | ATA_SUPPORT_IORDY;
1062 ata_ident->capabilities2 = (1 << 14);
1063 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1064 if (p->mult_sectors)
1065 ata_ident->multi = (ATA_MULTI_VALID | p->mult_sectors);
1066 if (sectors <= 0x0fffffff) {
1067 ata_ident->lba_size_1 = sectors;
1068 ata_ident->lba_size_2 = (sectors >> 16);
1070 ata_ident->lba_size_1 = 0xffff;
1071 ata_ident->lba_size_2 = 0x0fff;
1073 ata_ident->mwdmamodes = 0x7;
1074 if (p->xfermode & ATA_WDMA0)
1075 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1076 ata_ident->apiomodes = 0x3;
1077 ata_ident->mwdmamin = 0x0078;
1078 ata_ident->mwdmarec = 0x0078;
1079 ata_ident->pioblind = 0x0078;
1080 ata_ident->pioiordy = 0x0078;
1081 ata_ident->support3 = 0;
1082 ata_ident->queue = 31;
1083 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
1085 ata_ident->satacapabilities2 = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
1086 (p->ssts & ATA_SS_SPD_MASK) >> 3);
1087 ata_ident->version_major = 0x3f0;
1088 ata_ident->version_minor = 0x28;
1089 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1090 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1091 ata_ident->support.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1092 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
1093 ata_ident->support.extension = (1 << 14);
1094 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1095 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1096 ata_ident->enabled.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1097 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
1098 ata_ident->enabled.extension = (1 << 14);
1099 ata_ident->udmamodes = 0x7f;
1100 if (p->xfermode & ATA_UDMA0)
1101 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1102 ata_ident->lba_size48_1 = sectors;
1103 ata_ident->lba_size48_2 = (sectors >> 16);
1104 ata_ident->lba_size48_3 = (sectors >> 32);
1105 ata_ident->lba_size48_4 = (sectors >> 48);
1107 if (candelete && !ro) {
1108 ata_ident->support3 |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
1109 ata_ident->max_dsm_blocks = 1;
1110 ata_ident->support_dsm = ATA_SUPPORT_DSM_TRIM;
1112 ata_ident->pss = ATA_PSS_VALID_VALUE;
1113 ata_ident->lsalign = 0x4000;
1114 if (psectsz > sectsz) {
1115 ata_ident->pss |= ATA_PSS_MULTLS;
1116 ata_ident->pss |= ffsl(psectsz / sectsz) - 1;
1117 ata_ident->lsalign |= (psectoff / sectsz);
1120 ata_ident->pss |= ATA_PSS_LSSABOVE512;
1121 ata_ident->lss_1 = sectsz / 2;
1122 ata_ident->lss_2 = ((sectsz / 2) >> 16);
1124 ata_ident->support2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1125 ata_ident->enabled2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1126 ata_ident->transport_major = 0x1020;
1127 ata_ident->integrity = 0x00a5;
1129 ahci_checksum((uint8_t*)ata_ident, sizeof(struct ata_params));
1133 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1136 ahci_write_fis_d2h(p, slot, cfis,
1137 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1139 ahci_write_fis_piosetup(p);
1140 write_prdt(p, slot, cfis, (void *)&p->ata_ident, sizeof(struct ata_params));
1141 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1146 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
1155 if (acmd[1] & 1) { /* VPD */
1156 if (acmd[2] == 0) { /* Supported VPD pages */
1164 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1166 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1167 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1168 ahci_write_fis_d2h(p, slot, cfis, tfd);
1180 atapi_string(buf + 8, "BHYVE", 8);
1181 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1182 atapi_string(buf + 32, "001", 4);
1188 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1189 write_prdt(p, slot, cfis, buf, len);
1190 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1194 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1199 sectors = blockif_size(p->bctx) / 2048;
1200 be32enc(buf, sectors - 1);
1201 be32enc(buf + 4, 2048);
1202 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1203 write_prdt(p, slot, cfis, buf, sizeof(buf));
1204 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1208 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1216 len = be16dec(acmd + 7);
1217 format = acmd[9] >> 6;
1224 uint8_t start_track, buf[20], *bp;
1226 msf = (acmd[1] >> 1) & 1;
1227 start_track = acmd[6];
1228 if (start_track > 1 && start_track != 0xaa) {
1230 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1232 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1233 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1234 ahci_write_fis_d2h(p, slot, cfis, tfd);
1240 if (start_track <= 1) {
1260 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1264 lba_to_msf(bp, sectors);
1267 be32enc(bp, sectors);
1271 be16enc(buf, size - 2);
1274 write_prdt(p, slot, cfis, buf, len);
1275 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1276 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1283 memset(buf, 0, sizeof(buf));
1287 if (len > sizeof(buf))
1289 write_prdt(p, slot, cfis, buf, len);
1290 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1291 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1299 uint8_t *bp, buf[50];
1301 msf = (acmd[1] >> 1) & 1;
1337 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1341 lba_to_msf(bp, sectors);
1344 be32enc(bp, sectors);
1367 be16enc(buf, size - 2);
1370 write_prdt(p, slot, cfis, buf, len);
1371 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1372 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1379 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1381 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1382 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1383 ahci_write_fis_d2h(p, slot, cfis, tfd);
1390 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1394 memset(buf, 0, sizeof(buf));
1397 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1398 write_prdt(p, slot, cfis, buf, sizeof(buf));
1399 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1403 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
1405 struct ahci_ioreq *aior;
1406 struct ahci_cmd_hdr *hdr;
1407 struct ahci_prdt_entry *prdt;
1408 struct blockif_req *breq;
1415 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1416 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1418 lba = be32dec(acmd + 2);
1419 if (acmd[0] == READ_10)
1420 len = be16dec(acmd + 7);
1422 len = be32dec(acmd + 6);
1424 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1425 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1431 * Pull request off free list
1433 aior = STAILQ_FIRST(&p->iofhd);
1434 assert(aior != NULL);
1435 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1441 breq = &aior->io_req;
1442 breq->br_offset = lba + done;
1443 ahci_build_iov(p, aior, prdt, hdr->prdtl);
1445 /* Mark this command in-flight. */
1446 p->pending |= 1 << slot;
1448 /* Stuff request onto busy list. */
1449 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1451 err = blockif_read(p->bctx, breq);
1456 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1464 if (len > sizeof(buf))
1466 memset(buf, 0, len);
1467 buf[0] = 0x70 | (1 << 7);
1468 buf[2] = p->sense_key;
1471 write_prdt(p, slot, cfis, buf, len);
1472 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1473 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1477 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1479 uint8_t *acmd = cfis + 0x40;
1482 switch (acmd[4] & 3) {
1486 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1487 tfd = ATA_S_READY | ATA_S_DSC;
1490 /* TODO eject media */
1491 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1492 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1494 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1497 ahci_write_fis_d2h(p, slot, cfis, tfd);
1501 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1509 len = be16dec(acmd + 7);
1511 code = acmd[2] & 0x3f;
1516 case MODEPAGE_RW_ERROR_RECOVERY:
1520 if (len > sizeof(buf))
1523 memset(buf, 0, sizeof(buf));
1524 be16enc(buf, 16 - 2);
1529 write_prdt(p, slot, cfis, buf, len);
1530 tfd = ATA_S_READY | ATA_S_DSC;
1533 case MODEPAGE_CD_CAPABILITIES:
1537 if (len > sizeof(buf))
1540 memset(buf, 0, sizeof(buf));
1541 be16enc(buf, 30 - 2);
1547 be16enc(&buf[18], 2);
1548 be16enc(&buf[20], 512);
1549 write_prdt(p, slot, cfis, buf, len);
1550 tfd = ATA_S_READY | ATA_S_DSC;
1559 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1561 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1566 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1568 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1571 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1572 ahci_write_fis_d2h(p, slot, cfis, tfd);
1576 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1584 /* we don't support asynchronous operation */
1585 if (!(acmd[1] & 1)) {
1586 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1588 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1593 len = be16dec(acmd + 7);
1594 if (len > sizeof(buf))
1597 memset(buf, 0, sizeof(buf));
1598 be16enc(buf, 8 - 2);
1602 write_prdt(p, slot, cfis, buf, len);
1603 tfd = ATA_S_READY | ATA_S_DSC;
1605 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1606 ahci_write_fis_d2h(p, slot, cfis, tfd);
1610 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1620 for (i = 0; i < 16; i++)
1621 DPRINTF("%02x ", acmd[i]);
1627 case TEST_UNIT_READY:
1628 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1629 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1632 atapi_inquiry(p, slot, cfis);
1635 atapi_read_capacity(p, slot, cfis);
1639 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1640 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1643 atapi_read_toc(p, slot, cfis);
1646 atapi_report_luns(p, slot, cfis);
1650 atapi_read(p, slot, cfis, 0);
1653 atapi_request_sense(p, slot, cfis);
1655 case START_STOP_UNIT:
1656 atapi_start_stop_unit(p, slot, cfis);
1659 atapi_mode_sense(p, slot, cfis);
1661 case GET_EVENT_STATUS_NOTIFICATION:
1662 atapi_get_event_status_notification(p, slot, cfis);
1665 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1666 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1668 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1669 ATA_S_READY | ATA_S_ERROR);
1675 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1678 p->tfd |= ATA_S_BUSY;
1680 case ATA_ATA_IDENTIFY:
1681 handle_identify(p, slot, cfis);
1683 case ATA_SETFEATURES:
1686 case ATA_SF_ENAB_SATA_SF:
1688 case ATA_SATA_SF_AN:
1689 p->tfd = ATA_S_DSC | ATA_S_READY;
1692 p->tfd = ATA_S_ERROR | ATA_S_READY;
1693 p->tfd |= (ATA_ERROR_ABORT << 8);
1697 case ATA_SF_ENAB_WCACHE:
1698 case ATA_SF_DIS_WCACHE:
1699 case ATA_SF_ENAB_RCACHE:
1700 case ATA_SF_DIS_RCACHE:
1701 p->tfd = ATA_S_DSC | ATA_S_READY;
1703 case ATA_SF_SETXFER:
1705 switch (cfis[12] & 0xf8) {
1711 p->xfermode = (cfis[12] & 0x7);
1714 p->tfd = ATA_S_DSC | ATA_S_READY;
1718 p->tfd = ATA_S_ERROR | ATA_S_READY;
1719 p->tfd |= (ATA_ERROR_ABORT << 8);
1722 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1726 if (cfis[12] != 0 &&
1727 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1728 p->tfd = ATA_S_ERROR | ATA_S_READY;
1729 p->tfd |= (ATA_ERROR_ABORT << 8);
1731 p->mult_sectors = cfis[12];
1732 p->tfd = ATA_S_DSC | ATA_S_READY;
1734 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1742 case ATA_READ_MUL48:
1743 case ATA_WRITE_MUL48:
1746 case ATA_READ_DMA48:
1747 case ATA_WRITE_DMA48:
1748 case ATA_READ_FPDMA_QUEUED:
1749 case ATA_WRITE_FPDMA_QUEUED:
1750 ahci_handle_rw(p, slot, cfis, 0);
1752 case ATA_FLUSHCACHE:
1753 case ATA_FLUSHCACHE48:
1754 ahci_handle_flush(p, slot, cfis);
1756 case ATA_DATA_SET_MANAGEMENT:
1757 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1758 cfis[13] == 0 && cfis[12] == 1) {
1759 ahci_handle_dsm_trim(p, slot, cfis, 0);
1762 ahci_write_fis_d2h(p, slot, cfis,
1763 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1765 case ATA_SEND_FPDMA_QUEUED:
1766 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1767 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1768 cfis[11] == 0 && cfis[3] == 1) {
1769 ahci_handle_dsm_trim(p, slot, cfis, 0);
1772 ahci_write_fis_d2h(p, slot, cfis,
1773 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1775 case ATA_READ_LOG_EXT:
1776 case ATA_READ_LOG_DMA_EXT:
1777 ahci_handle_read_log(p, slot, cfis);
1779 case ATA_SECURITY_FREEZE_LOCK:
1782 ahci_write_fis_d2h(p, slot, cfis,
1783 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1785 case ATA_CHECK_POWER_MODE:
1786 cfis[12] = 0xff; /* always on */
1787 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1789 case ATA_STANDBY_CMD:
1790 case ATA_STANDBY_IMMEDIATE:
1792 case ATA_IDLE_IMMEDIATE:
1794 case ATA_READ_VERIFY:
1795 case ATA_READ_VERIFY48:
1796 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1798 case ATA_ATAPI_IDENTIFY:
1799 handle_atapi_identify(p, slot, cfis);
1801 case ATA_PACKET_CMD:
1803 ahci_write_fis_d2h(p, slot, cfis,
1804 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1806 handle_packet_cmd(p, slot, cfis);
1809 WPRINTF("Unsupported cmd:%02x", cfis[2]);
1810 ahci_write_fis_d2h(p, slot, cfis,
1811 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1817 ahci_handle_slot(struct ahci_port *p, int slot)
1819 struct ahci_cmd_hdr *hdr;
1821 struct ahci_prdt_entry *prdt;
1823 struct pci_ahci_softc *sc;
1830 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1832 cfl = (hdr->flags & 0x1f) * 4;
1834 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1835 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1837 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1840 for (i = 0; i < cfl; i++) {
1843 DPRINTF("%02x ", cfis[i]);
1847 for (i = 0; i < hdr->prdtl; i++) {
1848 DPRINTF("%d@%08"PRIx64"", prdt->dbc & 0x3fffff, prdt->dba);
1853 if (cfis[0] != FIS_TYPE_REGH2D) {
1854 WPRINTF("Not a H2D FIS:%02x", cfis[0]);
1858 if (cfis[1] & 0x80) {
1859 ahci_handle_cmd(p, slot, cfis);
1861 if (cfis[15] & (1 << 2))
1863 else if (p->reset) {
1867 p->ci &= ~(1 << slot);
1872 ahci_handle_port(struct ahci_port *p)
1875 if (!(p->cmd & AHCI_P_CMD_ST))
1879 * Search for any new commands to issue ignoring those that
1880 * are already in-flight. Stop if device is busy or in error.
1882 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) {
1883 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0)
1885 if (p->waitforclear)
1887 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) {
1888 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1889 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT;
1890 ahci_handle_slot(p, p->ccs);
1896 * blockif callback routine - this runs in the context of the blockif
1897 * i/o thread, so the mutex needs to be acquired.
1900 ata_ioreq_cb(struct blockif_req *br, int err)
1902 struct ahci_cmd_hdr *hdr;
1903 struct ahci_ioreq *aior;
1904 struct ahci_port *p;
1905 struct pci_ahci_softc *sc;
1910 DPRINTF("%s %d", __func__, err);
1913 aior = br->br_param;
1918 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1920 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1921 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1922 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1924 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1925 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1926 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1929 pthread_mutex_lock(&sc->mtx);
1932 * Delete the blockif request from the busy list
1934 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1937 * Move the blockif request back to the free list
1939 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1942 hdr->prdbc = aior->done;
1944 if (!err && aior->more) {
1946 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1948 ahci_handle_rw(p, slot, cfis, aior->done);
1953 tfd = ATA_S_READY | ATA_S_DSC;
1955 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1957 ahci_write_fis_sdb(p, slot, cfis, tfd);
1959 ahci_write_fis_d2h(p, slot, cfis, tfd);
1962 * This command is now complete.
1964 p->pending &= ~(1 << slot);
1966 ahci_check_stopped(p);
1967 ahci_handle_port(p);
1969 pthread_mutex_unlock(&sc->mtx);
1970 DPRINTF("%s exit", __func__);
1974 atapi_ioreq_cb(struct blockif_req *br, int err)
1976 struct ahci_cmd_hdr *hdr;
1977 struct ahci_ioreq *aior;
1978 struct ahci_port *p;
1979 struct pci_ahci_softc *sc;
1984 DPRINTF("%s %d", __func__, err);
1986 aior = br->br_param;
1991 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1993 pthread_mutex_lock(&sc->mtx);
1996 * Delete the blockif request from the busy list
1998 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
2001 * Move the blockif request back to the free list
2003 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
2006 hdr->prdbc = aior->done;
2008 if (!err && aior->more) {
2009 atapi_read(p, slot, cfis, aior->done);
2014 tfd = ATA_S_READY | ATA_S_DSC;
2016 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
2018 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
2020 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
2021 ahci_write_fis_d2h(p, slot, cfis, tfd);
2024 * This command is now complete.
2026 p->pending &= ~(1 << slot);
2028 ahci_check_stopped(p);
2029 ahci_handle_port(p);
2031 pthread_mutex_unlock(&sc->mtx);
2032 DPRINTF("%s exit", __func__);
2036 pci_ahci_ioreq_init(struct ahci_port *pr)
2038 struct ahci_ioreq *vr;
2041 pr->ioqsz = blockif_queuesz(pr->bctx);
2042 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
2043 STAILQ_INIT(&pr->iofhd);
2046 * Add all i/o request entries to the free queue
2048 for (i = 0; i < pr->ioqsz; i++) {
2052 vr->io_req.br_callback = ata_ioreq_cb;
2054 vr->io_req.br_callback = atapi_ioreq_cb;
2055 vr->io_req.br_param = vr;
2056 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
2059 TAILQ_INIT(&pr->iobhd);
2063 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2065 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2066 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2067 struct ahci_port *p = &sc->port[port];
2069 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2070 port, offset, value);
2090 p->ie = value & 0xFDC000FF;
2095 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2096 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2097 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2098 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK);
2099 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2100 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2101 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2102 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value;
2104 if (!(value & AHCI_P_CMD_ST)) {
2109 p->cmd |= AHCI_P_CMD_CR;
2110 clb = (uint64_t)p->clbu << 32 | p->clb;
2111 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
2112 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
2115 if (value & AHCI_P_CMD_FRE) {
2118 p->cmd |= AHCI_P_CMD_FR;
2119 fb = (uint64_t)p->fbu << 32 | p->fb;
2120 /* we don't support FBSCP, so rfis size is 256Bytes */
2121 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
2123 p->cmd &= ~AHCI_P_CMD_FR;
2126 if (value & AHCI_P_CMD_CLO) {
2127 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ);
2128 p->cmd &= ~AHCI_P_CMD_CLO;
2131 if (value & AHCI_P_CMD_ICC_MASK) {
2132 p->cmd &= ~AHCI_P_CMD_ICC_MASK;
2135 ahci_handle_port(p);
2141 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"", offset);
2145 if (!(p->cmd & AHCI_P_CMD_ST)) {
2146 if (value & ATA_SC_DET_RESET)
2158 ahci_handle_port(p);
2168 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2170 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2178 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"", offset);
2181 if (value & AHCI_GHC_HR) {
2185 if (value & AHCI_GHC_IE)
2186 sc->ghc |= AHCI_GHC_IE;
2188 sc->ghc &= ~AHCI_GHC_IE;
2189 ahci_generate_intr(sc, 0xffffffff);
2193 ahci_generate_intr(sc, value);
2201 pci_ahci_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
2204 struct pci_ahci_softc *sc = pi->pi_arg;
2206 assert(baridx == 5);
2207 assert((offset % 4) == 0 && size == 4);
2209 pthread_mutex_lock(&sc->mtx);
2211 if (offset < AHCI_OFFSET)
2212 pci_ahci_host_write(sc, offset, value);
2213 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP)
2214 pci_ahci_port_write(sc, offset, value);
2216 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"", offset);
2218 pthread_mutex_unlock(&sc->mtx);
2222 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2238 uint32_t *p = &sc->cap;
2239 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2247 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x",
2254 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2257 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2258 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2278 uint32_t *p= &sc->port[port].clb;
2279 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2288 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x",
2289 port, offset, value);
2295 pci_ahci_read(struct pci_devinst *pi, int baridx, uint64_t regoff, int size)
2297 struct pci_ahci_softc *sc = pi->pi_arg;
2301 assert(baridx == 5);
2302 assert(size == 1 || size == 2 || size == 4);
2303 assert((regoff & (size - 1)) == 0);
2305 pthread_mutex_lock(&sc->mtx);
2307 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */
2308 if (offset < AHCI_OFFSET)
2309 value = pci_ahci_host_read(sc, offset);
2310 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP)
2311 value = pci_ahci_port_read(sc, offset);
2314 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"",
2317 value >>= 8 * (regoff & 0x3);
2319 pthread_mutex_unlock(&sc->mtx);
2325 * Each AHCI controller has a "port" node which contains nodes for
2326 * each port named after the decimal number of the port (no leading
2327 * zeroes). Port nodes contain a "type" ("hd" or "cd"), as well as
2328 * options for blockif. For example:
2335 * .path="/path/to/image"
2338 pci_ahci_legacy_config_port(nvlist_t *nvl, int port, const char *type,
2341 char node_name[sizeof("XX")];
2344 snprintf(node_name, sizeof(node_name), "%d", port);
2345 port_nvl = create_relative_config_node(nvl, node_name);
2346 set_config_value_node(port_nvl, "type", type);
2347 return (blockif_legacy_config(port_nvl, opts));
2351 pci_ahci_legacy_config(nvlist_t *nvl, const char *opts)
2353 nvlist_t *ports_nvl;
2355 char *next, *next2, *str, *tofree;
2361 ports_nvl = create_relative_config_node(nvl, "port");
2363 tofree = str = strdup(opts);
2364 for (p = 0; p < MAX_PORTS && str != NULL; p++, str = next) {
2365 /* Identify and cut off type of present port. */
2366 if (strncmp(str, "hd:", 3) == 0) {
2369 } else if (strncmp(str, "cd:", 3) == 0) {
2375 /* Find and cut off the next port options. */
2376 next = strstr(str, ",hd:");
2377 next2 = strstr(str, ",cd:");
2378 if (next == NULL || (next2 != NULL && next2 < next))
2389 EPRINTLN("Missing or invalid type for port %d: \"%s\"",
2394 if (pci_ahci_legacy_config_port(ports_nvl, p, type, str) != 0)
2404 pci_ahci_cd_legacy_config(nvlist_t *nvl, const char *opts)
2406 nvlist_t *ports_nvl;
2408 ports_nvl = create_relative_config_node(nvl, "port");
2409 return (pci_ahci_legacy_config_port(ports_nvl, 0, "cd", opts));
2413 pci_ahci_hd_legacy_config(nvlist_t *nvl, const char *opts)
2415 nvlist_t *ports_nvl;
2417 ports_nvl = create_relative_config_node(nvl, "port");
2418 return (pci_ahci_legacy_config_port(ports_nvl, 0, "hd", opts));
2422 pci_ahci_init(struct pci_devinst *pi, nvlist_t *nvl)
2424 char bident[sizeof("XXX:XXX:XXX")];
2425 char node_name[sizeof("XX")];
2426 struct blockif_ctxt *bctxt;
2427 struct pci_ahci_softc *sc;
2428 int atapi, ret, slots, p;
2431 const char *path, *type, *value;
2432 nvlist_t *ports_nvl, *port_nvl;
2437 dbg = fopen("/tmp/log", "w+");
2440 sc = calloc(1, sizeof(struct pci_ahci_softc));
2443 pthread_mutex_init(&sc->mtx, NULL);
2448 ports_nvl = find_relative_config_node(nvl, "port");
2449 for (p = 0; ports_nvl != NULL && p < MAX_PORTS; p++) {
2450 struct ata_params *ata_ident = &sc->port[p].ata_ident;
2451 char ident[AHCI_PORT_IDENT];
2453 snprintf(node_name, sizeof(node_name), "%d", p);
2454 port_nvl = find_relative_config_node(ports_nvl, node_name);
2455 if (port_nvl == NULL)
2458 type = get_config_value_node(port_nvl, "type");
2462 if (strcmp(type, "hd") == 0)
2468 * Attempt to open the backing image. Use the PCI slot/func
2469 * and the port number for the identifier string.
2471 snprintf(bident, sizeof(bident), "%u:%u:%u", pi->pi_slot,
2474 bctxt = blockif_open(port_nvl, bident);
2475 if (bctxt == NULL) {
2480 sc->port[p].bctx = bctxt;
2481 sc->port[p].pr_sc = sc;
2482 sc->port[p].port = p;
2483 sc->port[p].atapi = atapi;
2486 * Create an identifier for the backing file.
2487 * Use parts of the md5 sum of the filename
2489 path = get_config_value_node(port_nvl, "path");
2491 MD5Update(&mdctx, path, strlen(path));
2492 MD5Final(digest, &mdctx);
2493 snprintf(ident, AHCI_PORT_IDENT,
2494 "BHYVE-%02X%02X-%02X%02X-%02X%02X",
2495 digest[0], digest[1], digest[2], digest[3], digest[4],
2498 memset(ata_ident, 0, sizeof(struct ata_params));
2499 ata_string((uint8_t*)&ata_ident->serial, ident, 20);
2500 ata_string((uint8_t*)&ata_ident->revision, "001", 8);
2502 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DVD ROM", 40);
2504 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DISK", 40);
2505 value = get_config_value_node(port_nvl, "nmrr");
2507 ata_ident->media_rotation_rate = atoi(value);
2508 value = get_config_value_node(port_nvl, "ser");
2510 ata_string((uint8_t*)(&ata_ident->serial), value, 20);
2511 value = get_config_value_node(port_nvl, "rev");
2513 ata_string((uint8_t*)(&ata_ident->revision), value, 8);
2514 value = get_config_value_node(port_nvl, "model");
2516 ata_string((uint8_t*)(&ata_ident->model), value, 40);
2517 ata_identify_init(&sc->port[p], atapi);
2520 * Allocate blockif request structures and add them
2523 pci_ahci_ioreq_init(&sc->port[p]);
2526 if (sc->port[p].ioqsz < slots)
2527 slots = sc->port[p].ioqsz;
2531 /* Intel ICH8 AHCI */
2533 if (sc->ports < DEF_PORTS)
2534 sc->ports = DEF_PORTS;
2535 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2536 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2537 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2538 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2539 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2542 sc->cap2 = AHCI_CAP2_APST;
2545 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2546 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2547 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2548 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2549 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2550 p = MIN(sc->ports, 16);
2551 p = flsl(p) - ((p & (p - 1)) ? 0 : 1);
2552 pci_emul_add_msicap(pi, 1 << p);
2553 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2554 AHCI_OFFSET + sc->ports * AHCI_STEP);
2556 pci_lintr_request(pi);
2560 for (p = 0; p < sc->ports; p++) {
2561 if (sc->port[p].bctx != NULL)
2562 blockif_close(sc->port[p].bctx);
2570 #ifdef BHYVE_SNAPSHOT
2572 pci_ahci_snapshot(struct vm_snapshot_meta *meta)
2576 struct pci_devinst *pi;
2577 struct pci_ahci_softc *sc;
2578 struct ahci_port *port;
2580 pi = meta->dev_data;
2583 /* TODO: add mtx lock/unlock */
2585 SNAPSHOT_VAR_OR_LEAVE(sc->ports, meta, ret, done);
2586 SNAPSHOT_VAR_OR_LEAVE(sc->cap, meta, ret, done);
2587 SNAPSHOT_VAR_OR_LEAVE(sc->ghc, meta, ret, done);
2588 SNAPSHOT_VAR_OR_LEAVE(sc->is, meta, ret, done);
2589 SNAPSHOT_VAR_OR_LEAVE(sc->pi, meta, ret, done);
2590 SNAPSHOT_VAR_OR_LEAVE(sc->vs, meta, ret, done);
2591 SNAPSHOT_VAR_OR_LEAVE(sc->ccc_ctl, meta, ret, done);
2592 SNAPSHOT_VAR_OR_LEAVE(sc->ccc_pts, meta, ret, done);
2593 SNAPSHOT_VAR_OR_LEAVE(sc->em_loc, meta, ret, done);
2594 SNAPSHOT_VAR_OR_LEAVE(sc->em_ctl, meta, ret, done);
2595 SNAPSHOT_VAR_OR_LEAVE(sc->cap2, meta, ret, done);
2596 SNAPSHOT_VAR_OR_LEAVE(sc->bohc, meta, ret, done);
2597 SNAPSHOT_VAR_OR_LEAVE(sc->lintr, meta, ret, done);
2599 for (i = 0; i < MAX_PORTS; i++) {
2600 port = &sc->port[i];
2602 if (meta->op == VM_SNAPSHOT_SAVE)
2605 SNAPSHOT_VAR_OR_LEAVE(bctx, meta, ret, done);
2606 SNAPSHOT_VAR_OR_LEAVE(port->port, meta, ret, done);
2608 /* Mostly for restore; save is ensured by the lines above. */
2609 if (((bctx == NULL) && (port->bctx != NULL)) ||
2610 ((bctx != NULL) && (port->bctx == NULL))) {
2611 fprintf(stderr, "%s: ports not matching\r\n", __func__);
2616 if (port->bctx == NULL)
2619 if (port->port != i) {
2620 fprintf(stderr, "%s: ports not matching: "
2621 "actual: %d expected: %d\r\n",
2622 __func__, port->port, i);
2627 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, port->cmd_lst,
2628 AHCI_CL_SIZE * AHCI_MAX_SLOTS, false, meta, ret, done);
2629 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, port->rfis, 256,
2630 false, meta, ret, done);
2632 SNAPSHOT_VAR_OR_LEAVE(port->ata_ident, meta, ret, done);
2633 SNAPSHOT_VAR_OR_LEAVE(port->atapi, meta, ret, done);
2634 SNAPSHOT_VAR_OR_LEAVE(port->reset, meta, ret, done);
2635 SNAPSHOT_VAR_OR_LEAVE(port->waitforclear, meta, ret, done);
2636 SNAPSHOT_VAR_OR_LEAVE(port->mult_sectors, meta, ret, done);
2637 SNAPSHOT_VAR_OR_LEAVE(port->xfermode, meta, ret, done);
2638 SNAPSHOT_VAR_OR_LEAVE(port->err_cfis, meta, ret, done);
2639 SNAPSHOT_VAR_OR_LEAVE(port->sense_key, meta, ret, done);
2640 SNAPSHOT_VAR_OR_LEAVE(port->asc, meta, ret, done);
2641 SNAPSHOT_VAR_OR_LEAVE(port->ccs, meta, ret, done);
2642 SNAPSHOT_VAR_OR_LEAVE(port->pending, meta, ret, done);
2644 SNAPSHOT_VAR_OR_LEAVE(port->clb, meta, ret, done);
2645 SNAPSHOT_VAR_OR_LEAVE(port->clbu, meta, ret, done);
2646 SNAPSHOT_VAR_OR_LEAVE(port->fb, meta, ret, done);
2647 SNAPSHOT_VAR_OR_LEAVE(port->fbu, meta, ret, done);
2648 SNAPSHOT_VAR_OR_LEAVE(port->ie, meta, ret, done);
2649 SNAPSHOT_VAR_OR_LEAVE(port->cmd, meta, ret, done);
2650 SNAPSHOT_VAR_OR_LEAVE(port->unused0, meta, ret, done);
2651 SNAPSHOT_VAR_OR_LEAVE(port->tfd, meta, ret, done);
2652 SNAPSHOT_VAR_OR_LEAVE(port->sig, meta, ret, done);
2653 SNAPSHOT_VAR_OR_LEAVE(port->ssts, meta, ret, done);
2654 SNAPSHOT_VAR_OR_LEAVE(port->sctl, meta, ret, done);
2655 SNAPSHOT_VAR_OR_LEAVE(port->serr, meta, ret, done);
2656 SNAPSHOT_VAR_OR_LEAVE(port->sact, meta, ret, done);
2657 SNAPSHOT_VAR_OR_LEAVE(port->ci, meta, ret, done);
2658 SNAPSHOT_VAR_OR_LEAVE(port->sntf, meta, ret, done);
2659 SNAPSHOT_VAR_OR_LEAVE(port->fbs, meta, ret, done);
2660 SNAPSHOT_VAR_OR_LEAVE(port->ioqsz, meta, ret, done);
2662 assert(TAILQ_EMPTY(&port->iobhd));
2670 pci_ahci_pause(struct pci_devinst *pi)
2672 struct pci_ahci_softc *sc;
2673 struct blockif_ctxt *bctxt;
2678 for (i = 0; i < MAX_PORTS; i++) {
2679 bctxt = sc->port[i].bctx;
2683 blockif_pause(bctxt);
2690 pci_ahci_resume(struct pci_devinst *pi)
2692 struct pci_ahci_softc *sc;
2693 struct blockif_ctxt *bctxt;
2698 for (i = 0; i < MAX_PORTS; i++) {
2699 bctxt = sc->port[i].bctx;
2703 blockif_resume(bctxt);
2708 #endif /* BHYVE_SNAPSHOT */
2711 * Use separate emulation names to distinguish drive and atapi devices
2713 static const struct pci_devemu pci_de_ahci = {
2715 .pe_init = pci_ahci_init,
2716 .pe_legacy_config = pci_ahci_legacy_config,
2717 .pe_barwrite = pci_ahci_write,
2718 .pe_barread = pci_ahci_read,
2719 #ifdef BHYVE_SNAPSHOT
2720 .pe_snapshot = pci_ahci_snapshot,
2721 .pe_pause = pci_ahci_pause,
2722 .pe_resume = pci_ahci_resume,
2725 PCI_EMUL_SET(pci_de_ahci);
2727 static const struct pci_devemu pci_de_ahci_hd = {
2728 .pe_emu = "ahci-hd",
2729 .pe_legacy_config = pci_ahci_hd_legacy_config,
2732 PCI_EMUL_SET(pci_de_ahci_hd);
2734 static const struct pci_devemu pci_de_ahci_cd = {
2735 .pe_emu = "ahci-cd",
2736 .pe_legacy_config = pci_ahci_cd_legacy_config,
2739 PCI_EMUL_SET(pci_de_ahci_cd);