2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
58 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
60 #define PxSIG_ATA 0x00000101 /* ATA drive */
61 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
64 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
65 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
66 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
67 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
68 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
69 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
70 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
71 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
77 #define TEST_UNIT_READY 0x00
78 #define REQUEST_SENSE 0x03
80 #define START_STOP_UNIT 0x1B
81 #define PREVENT_ALLOW 0x1E
82 #define READ_CAPACITY 0x25
84 #define POSITION_TO_ELEMENT 0x2B
86 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
87 #define MODE_SENSE_10 0x5A
92 * SCSI mode page codes
94 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
95 #define MODEPAGE_CD_CAPABILITIES 0x2A
100 #define ATA_SF_ENAB_SATA_SF 0x10
101 #define ATA_SATA_SF_AN 0x05
102 #define ATA_SF_DIS_SATA_SF 0x90
109 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
111 #define DPRINTF(format, arg...)
113 #define WPRINTF(format, arg...) printf(format, ##arg)
116 struct blockif_req io_req;
117 struct ahci_port *io_pr;
118 STAILQ_ENTRY(ahci_ioreq) io_list;
127 struct blockif_ctxt *bctx;
128 struct pci_ahci_softc *pr_sc;
160 struct ahci_ioreq *ioreq;
162 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
165 struct ahci_cmd_hdr {
170 uint32_t reserved[4];
173 struct ahci_prdt_entry {
176 #define DBCMASK 0x3fffff
180 struct pci_ahci_softc {
181 struct pci_devinst *asc_pi;
196 struct ahci_port port[MAX_PORTS];
198 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
200 static inline void lba_to_msf(uint8_t *buf, int lba)
203 buf[0] = (lba / 75) / 60;
204 buf[1] = (lba / 75) % 60;
209 * generate HBA intr depending on whether or not ports within
210 * the controller have an interrupt pending.
213 ahci_generate_intr(struct pci_ahci_softc *sc)
215 struct pci_devinst *pi;
220 for (i = 0; i < sc->ports; i++) {
221 struct ahci_port *pr;
227 DPRINTF("%s %x\n", __func__, sc->is);
229 if (sc->is && (sc->ghc & AHCI_GHC_IE)) {
230 if (pci_msi_enabled(pi)) {
232 * Generate an MSI interrupt on every edge
234 pci_generate_msi(pi, 0);
235 } else if (!sc->lintr) {
237 * Only generate a pin-based interrupt if one wasn't
241 pci_lintr_assert(pi);
243 } else if (sc->lintr) {
245 * No interrupts: deassert pin-based signal if it had
248 pci_lintr_deassert(pi);
254 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
256 int offset, len, irq;
258 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
262 case FIS_TYPE_REGD2H:
267 case FIS_TYPE_SETDEVBITS:
272 case FIS_TYPE_PIOSETUP:
278 WPRINTF("unsupported fis type %d\n", ft);
281 memcpy(p->rfis + offset, fis, len);
284 ahci_generate_intr(p->pr_sc);
289 ahci_write_fis_piosetup(struct ahci_port *p)
293 memset(fis, 0, sizeof(fis));
294 fis[0] = FIS_TYPE_PIOSETUP;
295 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
299 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd)
304 error = (tfd >> 8) & 0xff;
305 memset(fis, 0, sizeof(fis));
308 *(uint32_t *)(fis + 4) = (1 << slot);
309 if (fis[2] & ATA_S_ERROR)
310 p->is |= AHCI_P_IX_TFE;
312 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
316 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
321 error = (tfd >> 8) & 0xff;
322 memset(fis, 0, sizeof(fis));
323 fis[0] = FIS_TYPE_REGD2H;
337 if (fis[2] & ATA_S_ERROR)
338 p->is |= AHCI_P_IX_TFE;
340 p->ci &= ~(1 << slot);
341 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
345 ahci_write_reset_fis_d2h(struct ahci_port *p)
349 memset(fis, 0, sizeof(fis));
350 fis[0] = FIS_TYPE_REGD2H;
358 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
362 ahci_port_reset(struct ahci_port *pr)
367 pr->xfermode = ATA_UDMA6;
368 pr->mult_sectors = 128;
371 pr->ssts = ATA_SS_DET_NO_DEVICE;
372 pr->sig = 0xFFFFFFFF;
376 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 |
378 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
381 pr->tfd |= ATA_S_READY;
383 pr->sig = PxSIG_ATAPI;
384 ahci_write_reset_fis_d2h(pr);
388 ahci_reset(struct pci_ahci_softc *sc)
392 sc->ghc = AHCI_GHC_AE;
396 pci_lintr_deassert(sc->asc_pi);
400 for (i = 0; i < sc->ports; i++) {
403 ahci_port_reset(&sc->port[i]);
408 ata_string(uint8_t *dest, const char *src, int len)
412 for (i = 0; i < len; i++) {
414 dest[i ^ 1] = *src++;
421 atapi_string(uint8_t *dest, const char *src, int len)
425 for (i = 0; i < len; i++) {
434 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
437 struct ahci_ioreq *aior;
438 struct blockif_req *breq;
439 struct pci_ahci_softc *sc;
440 struct ahci_prdt_entry *prdt;
441 struct ahci_cmd_hdr *hdr;
444 int i, err, iovcnt, ncq, readop;
447 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
448 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
453 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
454 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
457 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
458 cfis[2] == ATA_READ_FPDMA_QUEUED) {
459 lba = ((uint64_t)cfis[10] << 40) |
460 ((uint64_t)cfis[9] << 32) |
461 ((uint64_t)cfis[8] << 24) |
462 ((uint64_t)cfis[6] << 16) |
463 ((uint64_t)cfis[5] << 8) |
465 len = cfis[11] << 8 | cfis[3];
469 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
470 lba = ((uint64_t)cfis[10] << 40) |
471 ((uint64_t)cfis[9] << 32) |
472 ((uint64_t)cfis[8] << 24) |
473 ((uint64_t)cfis[6] << 16) |
474 ((uint64_t)cfis[5] << 8) |
476 len = cfis[13] << 8 | cfis[12];
480 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
481 (cfis[5] << 8) | cfis[4];
486 lba *= blockif_sectsz(p->bctx);
487 len *= blockif_sectsz(p->bctx);
490 * Pull request off free list
492 aior = STAILQ_FIRST(&p->iofhd);
493 assert(aior != NULL);
494 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
499 breq = &aior->io_req;
500 breq->br_offset = lba + done;
501 iovcnt = hdr->prdtl - seek;
502 if (iovcnt > BLOCKIF_IOV_MAX) {
503 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
504 iovcnt = BLOCKIF_IOV_MAX;
506 * Mark this command in-flight.
508 p->pending |= 1 << slot;
511 breq->br_iovcnt = iovcnt;
514 * Build up the iovec based on the prdt
516 for (i = 0; i < iovcnt; i++) {
519 dbcsz = (prdt->dbc & DBCMASK) + 1;
520 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
522 breq->br_iov[i].iov_len = dbcsz;
527 err = blockif_read(p->bctx, breq);
529 err = blockif_write(p->bctx, breq);
533 p->ci &= ~(1 << slot);
537 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
539 struct ahci_ioreq *aior;
540 struct blockif_req *breq;
544 * Pull request off free list
546 aior = STAILQ_FIRST(&p->iofhd);
547 assert(aior != NULL);
548 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
554 breq = &aior->io_req;
556 err = blockif_flush(p->bctx, breq);
561 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
564 struct ahci_cmd_hdr *hdr;
565 struct ahci_prdt_entry *prdt;
569 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
572 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
573 for (i = 0; i < hdr->prdtl && len; i++) {
578 dbcsz = (prdt->dbc & DBCMASK) + 1;
579 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
580 sublen = len < dbcsz ? len : dbcsz;
581 memcpy(ptr, from, sublen);
586 hdr->prdbc = size - len;
590 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
592 struct ahci_cmd_hdr *hdr;
594 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
595 if (p->atapi || hdr->prdtl == 0) {
596 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
597 p->is |= AHCI_P_IX_TFE;
602 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
603 memset(buf, 0, sizeof(buf));
605 /* TODO emulate different serial? */
606 ata_string((uint8_t *)(buf+10), "123456", 20);
607 ata_string((uint8_t *)(buf+23), "001", 8);
608 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
609 buf[47] = (0x8000 | 128);
611 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
613 buf[53] = (1 << 1 | 1 << 2);
615 buf[59] = (0x100 | p->mult_sectors);
617 buf[61] = (sectors >> 16);
619 if (p->xfermode & ATA_WDMA0)
620 buf[63] |= (1 << ((p->xfermode & 7) + 8));
627 buf[76] = (1 << 8 | 1 << 2);
630 buf[82] = (1 << 5 | 1 << 14);
631 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
633 buf[85] = (1 << 5 | 1 << 14);
634 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
637 if (p->xfermode & ATA_UDMA0)
638 buf[88] |= (1 << ((p->xfermode & 7) + 8));
639 buf[93] = (1 | 1 <<14);
641 buf[101] = (sectors >> 16);
642 buf[102] = (sectors >> 32);
643 buf[103] = (sectors >> 48);
644 ahci_write_fis_piosetup(p);
645 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
646 p->tfd = ATA_S_DSC | ATA_S_READY;
647 p->is |= AHCI_P_IX_DP;
649 p->ci &= ~(1 << slot);
650 ahci_generate_intr(p->pr_sc);
654 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
657 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
658 p->is |= AHCI_P_IX_TFE;
662 memset(buf, 0, sizeof(buf));
663 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
664 /* TODO emulate different serial? */
665 ata_string((uint8_t *)(buf+10), "123456", 20);
666 ata_string((uint8_t *)(buf+23), "001", 8);
667 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
668 buf[49] = (1 << 9 | 1 << 8);
669 buf[50] = (1 << 14 | 1);
670 buf[53] = (1 << 2 | 1 << 1);
678 buf[76] = (1 << 2 | 1 << 1);
680 buf[80] = (0x1f << 4);
686 buf[88] = (1 << 14 | 0x7f);
687 ahci_write_fis_piosetup(p);
688 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
689 p->tfd = ATA_S_DSC | ATA_S_READY;
690 p->is |= AHCI_P_IX_DHR;
692 p->ci &= ~(1 << slot);
693 ahci_generate_intr(p->pr_sc);
697 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
713 atapi_string(buf + 8, "BHYVE", 8);
714 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
715 atapi_string(buf + 32, "001", 4);
720 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
721 write_prdt(p, slot, cfis, buf, len);
722 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
726 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
731 sectors = blockif_size(p->bctx) / 2048;
732 be32enc(buf, sectors - 1);
733 be32enc(buf + 4, 2048);
734 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
735 write_prdt(p, slot, cfis, buf, sizeof(buf));
736 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
740 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
748 len = be16dec(acmd + 7);
749 format = acmd[9] >> 6;
755 uint8_t start_track, buf[20], *bp;
757 msf = (acmd[1] >> 1) & 1;
758 start_track = acmd[6];
759 if (start_track > 1 && start_track != 0xaa) {
761 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
763 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
764 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
765 ahci_write_fis_d2h(p, slot, cfis, tfd);
771 if (start_track <= 1) {
791 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
795 lba_to_msf(bp, sectors);
798 be32enc(bp, sectors);
802 be16enc(buf, size - 2);
805 write_prdt(p, slot, cfis, buf, len);
806 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
807 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
814 memset(buf, 0, sizeof(buf));
818 if (len > sizeof(buf))
820 write_prdt(p, slot, cfis, buf, len);
821 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
822 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
829 uint8_t start_track, *bp, buf[50];
831 msf = (acmd[1] >> 1) & 1;
832 start_track = acmd[6];
868 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
872 lba_to_msf(bp, sectors);
875 be32enc(bp, sectors);
898 be16enc(buf, size - 2);
901 write_prdt(p, slot, cfis, buf, len);
902 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
903 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
910 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
912 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
913 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
914 ahci_write_fis_d2h(p, slot, cfis, tfd);
921 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
922 uint32_t done, int seek)
924 struct ahci_ioreq *aior;
925 struct ahci_cmd_hdr *hdr;
926 struct ahci_prdt_entry *prdt;
927 struct blockif_req *breq;
928 struct pci_ahci_softc *sc;
936 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
937 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
940 lba = be32dec(acmd + 2);
941 if (acmd[0] == READ_10)
942 len = be16dec(acmd + 7);
944 len = be32dec(acmd + 6);
946 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
947 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
953 * Pull request off free list
955 aior = STAILQ_FIRST(&p->iofhd);
956 assert(aior != NULL);
957 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
962 breq = &aior->io_req;
963 breq->br_offset = lba + done;
964 iovcnt = hdr->prdtl - seek;
965 if (iovcnt > BLOCKIF_IOV_MAX) {
966 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
967 iovcnt = BLOCKIF_IOV_MAX;
970 breq->br_iovcnt = iovcnt;
973 * Build up the iovec based on the prdt
975 for (i = 0; i < iovcnt; i++) {
978 dbcsz = (prdt->dbc & DBCMASK) + 1;
979 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
981 breq->br_iov[i].iov_len = dbcsz;
985 err = blockif_read(p->bctx, breq);
990 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
998 if (len > sizeof(buf))
1000 memset(buf, 0, len);
1001 buf[0] = 0x70 | (1 << 7);
1002 buf[2] = p->sense_key;
1005 write_prdt(p, slot, cfis, buf, len);
1006 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1007 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1011 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1013 uint8_t *acmd = cfis + 0x40;
1016 switch (acmd[4] & 3) {
1020 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1021 tfd = ATA_S_READY | ATA_S_DSC;
1024 /* TODO eject media */
1025 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1026 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1028 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1031 ahci_write_fis_d2h(p, slot, cfis, tfd);
1035 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1043 len = be16dec(acmd + 7);
1045 code = acmd[2] & 0x3f;
1050 case MODEPAGE_RW_ERROR_RECOVERY:
1054 if (len > sizeof(buf))
1057 memset(buf, 0, sizeof(buf));
1058 be16enc(buf, 16 - 2);
1063 write_prdt(p, slot, cfis, buf, len);
1064 tfd = ATA_S_READY | ATA_S_DSC;
1067 case MODEPAGE_CD_CAPABILITIES:
1071 if (len > sizeof(buf))
1074 memset(buf, 0, sizeof(buf));
1075 be16enc(buf, 30 - 2);
1081 be16enc(&buf[18], 2);
1082 be16enc(&buf[20], 512);
1083 write_prdt(p, slot, cfis, buf, len);
1084 tfd = ATA_S_READY | ATA_S_DSC;
1093 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1095 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1100 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1102 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1105 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1106 ahci_write_fis_d2h(p, slot, cfis, tfd);
1110 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1118 /* we don't support asynchronous operation */
1119 if (!(acmd[1] & 1)) {
1120 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1122 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1127 len = be16dec(acmd + 7);
1128 if (len > sizeof(buf))
1131 memset(buf, 0, sizeof(buf));
1132 be16enc(buf, 8 - 2);
1136 write_prdt(p, slot, cfis, buf, len);
1137 tfd = ATA_S_READY | ATA_S_DSC;
1139 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1140 ahci_write_fis_d2h(p, slot, cfis, tfd);
1144 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1154 for (i = 0; i < 16; i++)
1155 DPRINTF("%02x ", acmd[i]);
1161 case TEST_UNIT_READY:
1162 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1163 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1166 atapi_inquiry(p, slot, cfis);
1169 atapi_read_capacity(p, slot, cfis);
1173 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1174 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1177 atapi_read_toc(p, slot, cfis);
1181 atapi_read(p, slot, cfis, 0, 0);
1184 atapi_request_sense(p, slot, cfis);
1186 case START_STOP_UNIT:
1187 atapi_start_stop_unit(p, slot, cfis);
1190 atapi_mode_sense(p, slot, cfis);
1192 case GET_EVENT_STATUS_NOTIFICATION:
1193 atapi_get_event_status_notification(p, slot, cfis);
1196 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1197 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1199 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1200 ATA_S_READY | ATA_S_ERROR);
1206 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1210 case ATA_ATA_IDENTIFY:
1211 handle_identify(p, slot, cfis);
1213 case ATA_SETFEATURES:
1216 case ATA_SF_ENAB_SATA_SF:
1218 case ATA_SATA_SF_AN:
1219 p->tfd = ATA_S_DSC | ATA_S_READY;
1222 p->tfd = ATA_S_ERROR | ATA_S_READY;
1223 p->tfd |= (ATA_ERROR_ABORT << 8);
1227 case ATA_SF_ENAB_WCACHE:
1228 case ATA_SF_DIS_WCACHE:
1229 case ATA_SF_ENAB_RCACHE:
1230 case ATA_SF_DIS_RCACHE:
1231 p->tfd = ATA_S_DSC | ATA_S_READY;
1233 case ATA_SF_SETXFER:
1235 switch (cfis[12] & 0xf8) {
1241 p->xfermode = (cfis[12] & 0x7);
1244 p->tfd = ATA_S_DSC | ATA_S_READY;
1248 p->tfd = ATA_S_ERROR | ATA_S_READY;
1249 p->tfd |= (ATA_ERROR_ABORT << 8);
1252 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1256 if (cfis[12] != 0 &&
1257 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1258 p->tfd = ATA_S_ERROR | ATA_S_READY;
1259 p->tfd |= (ATA_ERROR_ABORT << 8);
1261 p->mult_sectors = cfis[12];
1262 p->tfd = ATA_S_DSC | ATA_S_READY;
1264 p->is |= AHCI_P_IX_DP;
1265 p->ci &= ~(1 << slot);
1266 ahci_generate_intr(p->pr_sc);
1270 case ATA_READ_DMA48:
1271 case ATA_WRITE_DMA48:
1272 case ATA_READ_FPDMA_QUEUED:
1273 case ATA_WRITE_FPDMA_QUEUED:
1274 ahci_handle_dma(p, slot, cfis, 0, 0);
1276 case ATA_FLUSHCACHE:
1277 case ATA_FLUSHCACHE48:
1278 ahci_handle_flush(p, slot, cfis);
1280 case ATA_STANDBY_CMD:
1283 case ATA_STANDBY_IMMEDIATE:
1284 case ATA_IDLE_IMMEDIATE:
1286 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1288 case ATA_ATAPI_IDENTIFY:
1289 handle_atapi_identify(p, slot, cfis);
1291 case ATA_PACKET_CMD:
1293 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1294 p->is |= AHCI_P_IX_TFE;
1295 p->ci &= ~(1 << slot);
1296 ahci_generate_intr(p->pr_sc);
1298 handle_packet_cmd(p, slot, cfis);
1301 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1302 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1303 p->is |= AHCI_P_IX_TFE;
1304 p->ci &= ~(1 << slot);
1305 ahci_generate_intr(p->pr_sc);
1311 ahci_handle_slot(struct ahci_port *p, int slot)
1313 struct ahci_cmd_hdr *hdr;
1314 struct ahci_prdt_entry *prdt;
1315 struct pci_ahci_softc *sc;
1320 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1321 cfl = (hdr->flags & 0x1f) * 4;
1322 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1323 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1324 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1328 for (i = 0; i < cfl; i++) {
1331 DPRINTF("%02x ", cfis[i]);
1335 for (i = 0; i < hdr->prdtl; i++) {
1336 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1341 if (cfis[0] != FIS_TYPE_REGH2D) {
1342 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1346 if (cfis[1] & 0x80) {
1347 ahci_handle_cmd(p, slot, cfis);
1349 if (cfis[15] & (1 << 2))
1351 else if (p->reset) {
1355 p->ci &= ~(1 << slot);
1360 ahci_handle_port(struct ahci_port *p)
1364 if (!(p->cmd & AHCI_P_CMD_ST))
1368 * Search for any new commands to issue ignoring those that
1369 * are already in-flight.
1371 for (i = 0; (i < 32) && p->ci; i++) {
1372 if ((p->ci & (1 << i)) && !(p->pending & (1 << i)))
1373 ahci_handle_slot(p, i);
1378 * blockif callback routine - this runs in the context of the blockif
1379 * i/o thread, so the mutex needs to be acquired.
1382 ata_ioreq_cb(struct blockif_req *br, int err)
1384 struct ahci_cmd_hdr *hdr;
1385 struct ahci_ioreq *aior;
1386 struct ahci_port *p;
1387 struct pci_ahci_softc *sc;
1390 int pending, slot, ncq;
1392 DPRINTF("%s %d\n", __func__, err);
1395 aior = br->br_param;
1399 pending = aior->prdtl;
1401 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1403 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1404 cfis[2] == ATA_READ_FPDMA_QUEUED)
1407 pthread_mutex_lock(&sc->mtx);
1410 * Move the blockif request back to the free list
1412 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1414 if (pending && !err) {
1415 ahci_handle_dma(p, slot, cfis, aior->done,
1416 hdr->prdtl - pending);
1420 if (!err && aior->done == aior->len) {
1421 tfd = ATA_S_READY | ATA_S_DSC;
1425 hdr->prdbc = aior->len;
1427 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1430 p->serr |= (1 << slot);
1434 * This command is now complete.
1436 p->pending &= ~(1 << slot);
1439 p->sact &= ~(1 << slot);
1440 ahci_write_fis_sdb(p, slot, tfd);
1442 ahci_write_fis_d2h(p, slot, cfis, tfd);
1445 pthread_mutex_unlock(&sc->mtx);
1446 DPRINTF("%s exit\n", __func__);
1450 atapi_ioreq_cb(struct blockif_req *br, int err)
1452 struct ahci_cmd_hdr *hdr;
1453 struct ahci_ioreq *aior;
1454 struct ahci_port *p;
1455 struct pci_ahci_softc *sc;
1460 DPRINTF("%s %d\n", __func__, err);
1462 aior = br->br_param;
1466 pending = aior->prdtl;
1468 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1470 pthread_mutex_lock(&sc->mtx);
1473 * Move the blockif request back to the free list
1475 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1477 if (pending && !err) {
1478 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1482 if (!err && aior->done == aior->len) {
1483 tfd = ATA_S_READY | ATA_S_DSC;
1484 hdr->prdbc = aior->len;
1486 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1488 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1492 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1493 ahci_write_fis_d2h(p, slot, cfis, tfd);
1496 pthread_mutex_unlock(&sc->mtx);
1497 DPRINTF("%s exit\n", __func__);
1501 pci_ahci_ioreq_init(struct ahci_port *pr)
1503 struct ahci_ioreq *vr;
1506 pr->ioqsz = blockif_queuesz(pr->bctx);
1507 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1508 STAILQ_INIT(&pr->iofhd);
1511 * Add all i/o request entries to the free queue
1513 for (i = 0; i < pr->ioqsz; i++) {
1517 vr->io_req.br_callback = ata_ioreq_cb;
1519 vr->io_req.br_callback = atapi_ioreq_cb;
1520 vr->io_req.br_param = vr;
1521 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_list);
1526 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1528 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1529 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1530 struct ahci_port *p = &sc->port[port];
1532 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1533 port, offset, value);
1552 p->ie = value & 0xFDC000FF;
1553 ahci_generate_intr(sc);
1559 if (!(value & AHCI_P_CMD_ST)) {
1560 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
1566 p->cmd |= AHCI_P_CMD_CR;
1567 clb = (uint64_t)p->clbu << 32 | p->clb;
1568 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1569 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1572 if (value & AHCI_P_CMD_FRE) {
1575 p->cmd |= AHCI_P_CMD_FR;
1576 fb = (uint64_t)p->fbu << 32 | p->fb;
1577 /* we don't support FBSCP, so rfis size is 256Bytes */
1578 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1580 p->cmd &= ~AHCI_P_CMD_FR;
1583 if (value & AHCI_P_CMD_CLO) {
1585 p->cmd &= ~AHCI_P_CMD_CLO;
1588 ahci_handle_port(p);
1594 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1597 if (!(p->cmd & AHCI_P_CMD_ST)) {
1598 if (value & ATA_SC_DET_RESET)
1611 ahci_handle_port(p);
1621 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1623 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1631 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1634 if (value & AHCI_GHC_HR)
1636 else if (value & AHCI_GHC_IE) {
1637 sc->ghc |= AHCI_GHC_IE;
1638 ahci_generate_intr(sc);
1643 ahci_generate_intr(sc);
1651 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1652 int baridx, uint64_t offset, int size, uint64_t value)
1654 struct pci_ahci_softc *sc = pi->pi_arg;
1656 assert(baridx == 5);
1659 pthread_mutex_lock(&sc->mtx);
1661 if (offset < AHCI_OFFSET)
1662 pci_ahci_host_write(sc, offset, value);
1663 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1664 pci_ahci_port_write(sc, offset, value);
1666 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1668 pthread_mutex_unlock(&sc->mtx);
1672 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1688 uint32_t *p = &sc->cap;
1689 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1697 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1704 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1707 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1708 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1728 uint32_t *p= &sc->port[port].clb;
1729 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1738 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1739 port, offset, value);
1745 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1746 uint64_t offset, int size)
1748 struct pci_ahci_softc *sc = pi->pi_arg;
1751 assert(baridx == 5);
1754 pthread_mutex_lock(&sc->mtx);
1756 if (offset < AHCI_OFFSET)
1757 value = pci_ahci_host_read(sc, offset);
1758 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1759 value = pci_ahci_port_read(sc, offset);
1762 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
1765 pthread_mutex_unlock(&sc->mtx);
1771 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
1773 char bident[sizeof("XX:X:X")];
1774 struct blockif_ctxt *bctxt;
1775 struct pci_ahci_softc *sc;
1781 fprintf(stderr, "pci_ahci: backing device required\n");
1786 dbg = fopen("/tmp/log", "w+");
1789 sc = calloc(1, sizeof(struct pci_ahci_softc));
1792 sc->ports = MAX_PORTS;
1795 * Only use port 0 for a backing device. All other ports will be
1798 sc->port[0].atapi = atapi;
1801 * Attempt to open the backing image. Use the PCI
1802 * slot/func for the identifier string.
1804 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
1805 bctxt = blockif_open(opts, bident);
1806 if (bctxt == NULL) {
1810 sc->port[0].bctx = bctxt;
1811 sc->port[0].pr_sc = sc;
1814 * Allocate blockif request structures and add them
1817 pci_ahci_ioreq_init(&sc->port[0]);
1819 pthread_mutex_init(&sc->mtx, NULL);
1821 /* Intel ICH8 AHCI */
1822 slots = sc->port[0].ioqsz;
1826 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
1827 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
1828 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
1829 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
1830 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
1832 /* Only port 0 implemented */
1835 sc->cap2 = AHCI_CAP2_APST;
1838 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
1839 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
1840 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
1841 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
1842 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
1843 pci_emul_add_msicap(pi, 1);
1844 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
1845 AHCI_OFFSET + sc->ports * AHCI_STEP);
1847 pci_lintr_request(pi);
1851 blockif_close(sc->port[0].bctx);
1859 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1862 return (pci_ahci_init(ctx, pi, opts, 0));
1866 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1869 return (pci_ahci_init(ctx, pi, opts, 1));
1873 * Use separate emulation names to distinguish drive and atapi devices
1875 struct pci_devemu pci_de_ahci_hd = {
1876 .pe_emu = "ahci-hd",
1877 .pe_init = pci_ahci_hd_init,
1878 .pe_barwrite = pci_ahci_write,
1879 .pe_barread = pci_ahci_read
1881 PCI_EMUL_SET(pci_de_ahci_hd);
1883 struct pci_devemu pci_de_ahci_cd = {
1884 .pe_emu = "ahci-cd",
1885 .pe_init = pci_ahci_atapi_init,
1886 .pe_barwrite = pci_ahci_write,
1887 .pe_barread = pci_ahci_read
1889 PCI_EMUL_SET(pci_de_ahci_cd);