2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/linker_set.h>
39 #include <sys/ioctl.h>
42 #include <sys/endian.h>
44 #include <machine/vmm_snapshot.h>
56 #include <pthread_np.h>
65 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
66 #define MAX_PORTS 32 /* AHCI supports 32 ports */
68 #define PxSIG_ATA 0x00000101 /* ATA drive */
69 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
72 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
73 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
74 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
75 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
76 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
77 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
78 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
79 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
85 #define TEST_UNIT_READY 0x00
86 #define REQUEST_SENSE 0x03
88 #define START_STOP_UNIT 0x1B
89 #define PREVENT_ALLOW 0x1E
90 #define READ_CAPACITY 0x25
92 #define POSITION_TO_ELEMENT 0x2B
94 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
95 #define MODE_SENSE_10 0x5A
96 #define REPORT_LUNS 0xA0
101 * SCSI mode page codes
103 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
104 #define MODEPAGE_CD_CAPABILITIES 0x2A
109 #define ATA_SF_ENAB_SATA_SF 0x10
110 #define ATA_SATA_SF_AN 0x05
111 #define ATA_SF_DIS_SATA_SF 0x90
118 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
120 #define DPRINTF(format, arg...)
122 #define WPRINTF(format, arg...) printf(format, ##arg)
124 #define AHCI_PORT_IDENT 20 + 1
127 struct blockif_req io_req;
128 struct ahci_port *io_pr;
129 STAILQ_ENTRY(ahci_ioreq) io_flist;
130 TAILQ_ENTRY(ahci_ioreq) io_blist;
140 struct blockif_ctxt *bctx;
141 struct pci_ahci_softc *pr_sc;
142 struct ata_params ata_ident;
151 uint8_t err_cfis[20];
178 struct ahci_ioreq *ioreq;
180 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
181 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
184 struct ahci_cmd_hdr {
189 uint32_t reserved[4];
192 struct ahci_prdt_entry {
195 #define DBCMASK 0x3fffff
199 struct pci_ahci_softc {
200 struct pci_devinst *asc_pi;
215 struct ahci_port port[MAX_PORTS];
217 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
219 static void ahci_handle_port(struct ahci_port *p);
221 static inline void lba_to_msf(uint8_t *buf, int lba)
224 buf[0] = (lba / 75) / 60;
225 buf[1] = (lba / 75) % 60;
230 * Generate HBA interrupts on global IS register write.
233 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask)
235 struct pci_devinst *pi = sc->asc_pi;
240 /* Update global IS from PxIS/PxIE. */
241 for (i = 0; i < sc->ports; i++) {
246 DPRINTF("%s(%08x) %08x", __func__, mask, sc->is);
248 /* If there is nothing enabled -- clear legacy interrupt and exit. */
249 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) {
251 pci_lintr_deassert(pi);
257 /* If there is anything and no MSI -- assert legacy interrupt. */
258 nmsg = pci_msi_maxmsgnum(pi);
262 pci_lintr_assert(pi);
267 /* Assert respective MSIs for ports that were touched. */
268 for (i = 0; i < nmsg; i++) {
269 if (sc->ports <= nmsg || i < nmsg - 1)
272 mmask = 0xffffffff << i;
273 if (sc->is & mask && mmask & mask)
274 pci_generate_msi(pi, i);
279 * Generate HBA interrupt on specific port event.
282 ahci_port_intr(struct ahci_port *p)
284 struct pci_ahci_softc *sc = p->pr_sc;
285 struct pci_devinst *pi = sc->asc_pi;
288 DPRINTF("%s(%d) %08x/%08x %08x", __func__,
289 p->port, p->is, p->ie, sc->is);
291 /* If there is nothing enabled -- we are done. */
292 if ((p->is & p->ie) == 0)
295 /* In case of non-shared MSI always generate interrupt. */
296 nmsg = pci_msi_maxmsgnum(pi);
297 if (sc->ports <= nmsg || p->port < nmsg - 1) {
298 sc->is |= (1 << p->port);
299 if ((sc->ghc & AHCI_GHC_IE) == 0)
301 pci_generate_msi(pi, p->port);
305 /* If IS for this port is already set -- do nothing. */
306 if (sc->is & (1 << p->port))
309 sc->is |= (1 << p->port);
311 /* If interrupts are enabled -- generate one. */
312 if ((sc->ghc & AHCI_GHC_IE) == 0)
315 pci_generate_msi(pi, nmsg - 1);
316 } else if (!sc->lintr) {
318 pci_lintr_assert(pi);
323 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
325 int offset, len, irq;
327 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
331 case FIS_TYPE_REGD2H:
334 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0;
336 case FIS_TYPE_SETDEVBITS:
339 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0;
341 case FIS_TYPE_PIOSETUP:
344 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
347 WPRINTF("unsupported fis type %d", ft);
350 if (fis[2] & ATA_S_ERROR) {
352 irq |= AHCI_P_IX_TFE;
354 memcpy(p->rfis + offset, fis, len);
364 ahci_write_fis_piosetup(struct ahci_port *p)
368 memset(fis, 0, sizeof(fis));
369 fis[0] = FIS_TYPE_PIOSETUP;
370 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
374 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
379 error = (tfd >> 8) & 0xff;
381 memset(fis, 0, sizeof(fis));
382 fis[0] = FIS_TYPE_SETDEVBITS;
386 if (fis[2] & ATA_S_ERROR) {
387 p->err_cfis[0] = slot;
388 p->err_cfis[2] = tfd;
389 p->err_cfis[3] = error;
390 memcpy(&p->err_cfis[4], cfis + 4, 16);
392 *(uint32_t *)(fis + 4) = (1 << slot);
393 p->sact &= ~(1 << slot);
397 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
401 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
406 error = (tfd >> 8) & 0xff;
407 memset(fis, 0, sizeof(fis));
408 fis[0] = FIS_TYPE_REGD2H;
422 if (fis[2] & ATA_S_ERROR) {
423 p->err_cfis[0] = 0x80;
424 p->err_cfis[2] = tfd & 0xff;
425 p->err_cfis[3] = error;
426 memcpy(&p->err_cfis[4], cfis + 4, 16);
428 p->ci &= ~(1 << slot);
430 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
434 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot)
438 p->tfd = ATA_S_READY | ATA_S_DSC;
439 memset(fis, 0, sizeof(fis));
440 fis[0] = FIS_TYPE_REGD2H;
441 fis[1] = 0; /* No interrupt */
442 fis[2] = p->tfd; /* Status */
443 fis[3] = 0; /* No error */
444 p->ci &= ~(1 << slot);
445 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
449 ahci_write_reset_fis_d2h(struct ahci_port *p)
453 memset(fis, 0, sizeof(fis));
454 fis[0] = FIS_TYPE_REGD2H;
462 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
466 ahci_check_stopped(struct ahci_port *p)
469 * If we are no longer processing the command list and nothing
470 * is in-flight, clear the running bit, the current command
471 * slot, the command issue and active bits.
473 if (!(p->cmd & AHCI_P_CMD_ST)) {
474 if (p->pending == 0) {
476 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
485 ahci_port_stop(struct ahci_port *p)
487 struct ahci_ioreq *aior;
492 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
494 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
496 * Try to cancel the outstanding blockif request.
498 error = blockif_cancel(p->bctx, &aior->io_req);
504 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
505 cfis[2] == ATA_READ_FPDMA_QUEUED ||
506 cfis[2] == ATA_SEND_FPDMA_QUEUED)
507 p->sact &= ~(1 << slot); /* NCQ */
509 p->ci &= ~(1 << slot);
512 * This command is now done.
514 p->pending &= ~(1 << slot);
517 * Delete the blockif request from the busy list
519 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
522 * Move the blockif request back to the free list
524 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
527 ahci_check_stopped(p);
531 ahci_port_reset(struct ahci_port *pr)
535 pr->xfermode = ATA_UDMA6;
536 pr->mult_sectors = 128;
539 pr->ssts = ATA_SS_DET_NO_DEVICE;
540 pr->sig = 0xFFFFFFFF;
544 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
545 if (pr->sctl & ATA_SC_SPD_MASK)
546 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
548 pr->ssts |= ATA_SS_SPD_GEN3;
549 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
552 pr->tfd |= ATA_S_READY;
554 pr->sig = PxSIG_ATAPI;
555 ahci_write_reset_fis_d2h(pr);
559 ahci_reset(struct pci_ahci_softc *sc)
563 sc->ghc = AHCI_GHC_AE;
567 pci_lintr_deassert(sc->asc_pi);
571 for (i = 0; i < sc->ports; i++) {
574 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD);
575 if (sc->port[i].bctx)
576 sc->port[i].cmd |= AHCI_P_CMD_CPS;
577 sc->port[i].sctl = 0;
578 ahci_port_reset(&sc->port[i]);
583 ata_string(uint8_t *dest, const char *src, int len)
587 for (i = 0; i < len; i++) {
589 dest[i ^ 1] = *src++;
596 atapi_string(uint8_t *dest, const char *src, int len)
600 for (i = 0; i < len; i++) {
609 * Build up the iovec based on the PRDT, 'done' and 'len'.
612 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior,
613 struct ahci_prdt_entry *prdt, uint16_t prdtl)
615 struct blockif_req *breq = &aior->io_req;
616 int i, j, skip, todo, left, extra;
619 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */
621 left = aior->len - aior->done;
623 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0;
625 dbcsz = (prdt->dbc & DBCMASK) + 1;
626 /* Skip already done part of the PRDT */
634 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc),
635 prdt->dba + skip, dbcsz);
636 breq->br_iov[j].iov_len = dbcsz;
643 /* If we got limited by IOV length, round I/O down to sector size. */
644 if (j == BLOCKIF_IOV_MAX) {
645 extra = todo % blockif_sectsz(p->bctx);
649 if (breq->br_iov[j - 1].iov_len > extra) {
650 breq->br_iov[j - 1].iov_len -= extra;
653 extra -= breq->br_iov[j - 1].iov_len;
659 breq->br_resid = todo;
661 aior->more = (aior->done < aior->len && i < prdtl);
665 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
667 struct ahci_ioreq *aior;
668 struct blockif_req *breq;
669 struct ahci_prdt_entry *prdt;
670 struct ahci_cmd_hdr *hdr;
673 int err, first, ncq, readop;
675 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
676 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
681 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
682 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
683 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
684 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
687 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
688 cfis[2] == ATA_READ_FPDMA_QUEUED) {
689 lba = ((uint64_t)cfis[10] << 40) |
690 ((uint64_t)cfis[9] << 32) |
691 ((uint64_t)cfis[8] << 24) |
692 ((uint64_t)cfis[6] << 16) |
693 ((uint64_t)cfis[5] << 8) |
695 len = cfis[11] << 8 | cfis[3];
699 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
700 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
701 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
702 lba = ((uint64_t)cfis[10] << 40) |
703 ((uint64_t)cfis[9] << 32) |
704 ((uint64_t)cfis[8] << 24) |
705 ((uint64_t)cfis[6] << 16) |
706 ((uint64_t)cfis[5] << 8) |
708 len = cfis[13] << 8 | cfis[12];
712 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
713 (cfis[5] << 8) | cfis[4];
718 lba *= blockif_sectsz(p->bctx);
719 len *= blockif_sectsz(p->bctx);
721 /* Pull request off free list */
722 aior = STAILQ_FIRST(&p->iofhd);
723 assert(aior != NULL);
724 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
730 aior->readop = readop;
731 breq = &aior->io_req;
732 breq->br_offset = lba + done;
733 ahci_build_iov(p, aior, prdt, hdr->prdtl);
735 /* Mark this command in-flight. */
736 p->pending |= 1 << slot;
738 /* Stuff request onto busy list. */
739 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
742 ahci_write_fis_d2h_ncq(p, slot);
745 err = blockif_read(p->bctx, breq);
747 err = blockif_write(p->bctx, breq);
752 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
754 struct ahci_ioreq *aior;
755 struct blockif_req *breq;
759 * Pull request off free list
761 aior = STAILQ_FIRST(&p->iofhd);
762 assert(aior != NULL);
763 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
769 breq = &aior->io_req;
772 * Mark this command in-flight.
774 p->pending |= 1 << slot;
777 * Stuff request onto busy list
779 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
781 err = blockif_flush(p->bctx, breq);
786 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
789 struct ahci_cmd_hdr *hdr;
790 struct ahci_prdt_entry *prdt;
794 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
797 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
798 for (i = 0; i < hdr->prdtl && len; i++) {
803 dbcsz = (prdt->dbc & DBCMASK) + 1;
804 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
805 sublen = MIN(len, dbcsz);
806 memcpy(to, ptr, sublen);
814 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
816 struct ahci_ioreq *aior;
817 struct blockif_req *breq;
825 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
826 len = (uint16_t)cfis[13] << 8 | cfis[12];
829 } else { /* ATA_SEND_FPDMA_QUEUED */
830 len = (uint16_t)cfis[11] << 8 | cfis[3];
834 read_prdt(p, slot, cfis, buf, sizeof(buf));
838 elba = ((uint64_t)entry[5] << 40) |
839 ((uint64_t)entry[4] << 32) |
840 ((uint64_t)entry[3] << 24) |
841 ((uint64_t)entry[2] << 16) |
842 ((uint64_t)entry[1] << 8) |
844 elen = (uint16_t)entry[7] << 8 | entry[6];
850 ahci_write_fis_d2h_ncq(p, slot);
851 ahci_write_fis_sdb(p, slot, cfis,
852 ATA_S_READY | ATA_S_DSC);
854 ahci_write_fis_d2h(p, slot, cfis,
855 ATA_S_READY | ATA_S_DSC);
857 p->pending &= ~(1 << slot);
858 ahci_check_stopped(p);
867 * Pull request off free list
869 aior = STAILQ_FIRST(&p->iofhd);
870 assert(aior != NULL);
871 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
876 aior->more = (len != done);
878 breq = &aior->io_req;
879 breq->br_offset = elba * blockif_sectsz(p->bctx);
880 breq->br_resid = elen * blockif_sectsz(p->bctx);
883 * Mark this command in-flight.
885 p->pending |= 1 << slot;
888 * Stuff request onto busy list
890 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
893 ahci_write_fis_d2h_ncq(p, slot);
895 err = blockif_delete(p->bctx, breq);
900 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
903 struct ahci_cmd_hdr *hdr;
904 struct ahci_prdt_entry *prdt;
908 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
911 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
912 for (i = 0; i < hdr->prdtl && len; i++) {
917 dbcsz = (prdt->dbc & DBCMASK) + 1;
918 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
919 sublen = MIN(len, dbcsz);
920 memcpy(ptr, from, sublen);
925 hdr->prdbc = size - len;
929 ahci_checksum(uint8_t *buf, int size)
934 for (i = 0; i < size - 1; i++)
936 buf[size - 1] = 0x100 - sum;
940 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
942 struct ahci_cmd_hdr *hdr;
944 uint8_t *buf8 = (uint8_t *)buf;
945 uint16_t *buf16 = (uint16_t *)buf;
947 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
948 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 ||
949 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
950 ahci_write_fis_d2h(p, slot, cfis,
951 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
955 memset(buf, 0, sizeof(buf));
956 if (cfis[4] == 0x00) { /* Log directory */
957 buf16[0x00] = 1; /* Version -- 1 */
958 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */
959 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */
960 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */
961 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis));
962 ahci_checksum(buf8, sizeof(buf));
963 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */
964 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) {
965 buf[0x00] = 1; /* SFQ DSM supported */
966 buf[0x01] = 1; /* SFQ DSM TRIM supported */
969 ahci_write_fis_d2h(p, slot, cfis,
970 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
974 if (cfis[2] == ATA_READ_LOG_EXT)
975 ahci_write_fis_piosetup(p);
976 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
977 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
981 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
983 struct ahci_cmd_hdr *hdr;
985 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
986 if (p->atapi || hdr->prdtl == 0) {
987 ahci_write_fis_d2h(p, slot, cfis,
988 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
990 ahci_write_fis_piosetup(p);
991 write_prdt(p, slot, cfis, (void*)&p->ata_ident, sizeof(struct ata_params));
992 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
997 ata_identify_init(struct ahci_port* p, int atapi)
999 struct ata_params* ata_ident = &p->ata_ident;
1002 ata_ident->config = ATA_PROTO_ATAPI | ATA_ATAPI_TYPE_CDROM |
1003 ATA_ATAPI_REMOVABLE | ATA_DRQ_FAST;
1004 ata_ident->capabilities1 = ATA_SUPPORT_LBA |
1006 ata_ident->capabilities2 = (1 << 14 | 1);
1007 ata_ident->atavalid = ATA_FLAG_54_58 | ATA_FLAG_64_70;
1008 ata_ident->obsolete62 = 0x3f;
1009 ata_ident->mwdmamodes = 7;
1010 if (p->xfermode & ATA_WDMA0)
1011 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1012 ata_ident->apiomodes = 3;
1013 ata_ident->mwdmamin = 0x0078;
1014 ata_ident->mwdmarec = 0x0078;
1015 ata_ident->pioblind = 0x0078;
1016 ata_ident->pioiordy = 0x0078;
1017 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
1018 ata_ident->satacapabilities2 = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
1019 ata_ident->satasupport = ATA_SUPPORT_NCQ_STREAM;
1020 ata_ident->version_major = 0x3f0;
1021 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1022 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1023 ata_ident->support.command2 = (1 << 14);
1024 ata_ident->support.extension = (1 << 14);
1025 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1026 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1027 ata_ident->enabled.extension = (1 << 14);
1028 ata_ident->udmamodes = 0x7f;
1029 if (p->xfermode & ATA_UDMA0)
1030 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1031 ata_ident->transport_major = 0x1020;
1032 ata_ident->integrity = 0x00a5;
1035 int sectsz, psectsz, psectoff, candelete, ro;
1037 uint8_t sech, heads;
1039 ro = blockif_is_ro(p->bctx);
1040 candelete = blockif_candelete(p->bctx);
1041 sectsz = blockif_sectsz(p->bctx);
1042 sectors = blockif_size(p->bctx) / sectsz;
1043 blockif_chs(p->bctx, &cyl, &heads, &sech);
1044 blockif_psectsz(p->bctx, &psectsz, &psectoff);
1045 ata_ident->config = ATA_DRQ_FAST;
1046 ata_ident->cylinders = cyl;
1047 ata_ident->heads = heads;
1048 ata_ident->sectors = sech;
1050 ata_ident->sectors_intr = (0x8000 | 128);
1053 ata_ident->capabilities1 = ATA_SUPPORT_DMA |
1054 ATA_SUPPORT_LBA | ATA_SUPPORT_IORDY;
1055 ata_ident->capabilities2 = (1 << 14);
1056 ata_ident->atavalid = ATA_FLAG_54_58 |
1058 if (p->mult_sectors)
1059 ata_ident->multi = (ATA_MULTI_VALID | p->mult_sectors);
1060 if (sectors <= 0x0fffffff) {
1061 ata_ident->lba_size_1 = sectors;
1062 ata_ident->lba_size_2 = (sectors >> 16);
1064 ata_ident->lba_size_1 = 0xffff;
1065 ata_ident->lba_size_2 = 0x0fff;
1067 ata_ident->mwdmamodes = 0x7;
1068 if (p->xfermode & ATA_WDMA0)
1069 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1070 ata_ident->apiomodes = 0x3;
1071 ata_ident->mwdmamin = 0x0078;
1072 ata_ident->mwdmarec = 0x0078;
1073 ata_ident->pioblind = 0x0078;
1074 ata_ident->pioiordy = 0x0078;
1075 ata_ident->support3 = 0;
1076 ata_ident->queue = 31;
1077 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
1079 ata_ident->satacapabilities2 = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
1080 (p->ssts & ATA_SS_SPD_MASK) >> 3);
1081 ata_ident->version_major = 0x3f0;
1082 ata_ident->version_minor = 0x28;
1083 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1084 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1085 ata_ident->support.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1086 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
1087 ata_ident->support.extension = (1 << 14);
1088 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1089 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1090 ata_ident->enabled.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1091 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
1092 ata_ident->enabled.extension = (1 << 14);
1093 ata_ident->udmamodes = 0x7f;
1094 if (p->xfermode & ATA_UDMA0)
1095 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1096 ata_ident->lba_size48_1 = sectors;
1097 ata_ident->lba_size48_2 = (sectors >> 16);
1098 ata_ident->lba_size48_3 = (sectors >> 32);
1099 ata_ident->lba_size48_4 = (sectors >> 48);
1101 if (candelete && !ro) {
1102 ata_ident->support3 |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
1103 ata_ident->max_dsm_blocks = 1;
1104 ata_ident->support_dsm = ATA_SUPPORT_DSM_TRIM;
1106 ata_ident->pss = ATA_PSS_VALID_VALUE;
1107 ata_ident->lsalign = 0x4000;
1108 if (psectsz > sectsz) {
1109 ata_ident->pss |= ATA_PSS_MULTLS;
1110 ata_ident->pss |= ffsl(psectsz / sectsz) - 1;
1111 ata_ident->lsalign |= (psectoff / sectsz);
1114 ata_ident->pss |= ATA_PSS_LSSABOVE512;
1115 ata_ident->lss_1 = sectsz / 2;
1116 ata_ident->lss_2 = ((sectsz / 2) >> 16);
1118 ata_ident->support2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1119 ata_ident->enabled2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1120 ata_ident->transport_major = 0x1020;
1121 ata_ident->integrity = 0x00a5;
1123 ahci_checksum((uint8_t*)ata_ident, sizeof(struct ata_params));
1127 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1130 ahci_write_fis_d2h(p, slot, cfis,
1131 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1133 ahci_write_fis_piosetup(p);
1134 write_prdt(p, slot, cfis, (void *)&p->ata_ident, sizeof(struct ata_params));
1135 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1140 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
1149 if (acmd[1] & 1) { /* VPD */
1150 if (acmd[2] == 0) { /* Supported VPD pages */
1158 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1160 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1161 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1162 ahci_write_fis_d2h(p, slot, cfis, tfd);
1174 atapi_string(buf + 8, "BHYVE", 8);
1175 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1176 atapi_string(buf + 32, "001", 4);
1182 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1183 write_prdt(p, slot, cfis, buf, len);
1184 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1188 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1193 sectors = blockif_size(p->bctx) / 2048;
1194 be32enc(buf, sectors - 1);
1195 be32enc(buf + 4, 2048);
1196 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1197 write_prdt(p, slot, cfis, buf, sizeof(buf));
1198 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1202 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1210 len = be16dec(acmd + 7);
1211 format = acmd[9] >> 6;
1217 uint8_t start_track, buf[20], *bp;
1219 msf = (acmd[1] >> 1) & 1;
1220 start_track = acmd[6];
1221 if (start_track > 1 && start_track != 0xaa) {
1223 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1225 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1226 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1227 ahci_write_fis_d2h(p, slot, cfis, tfd);
1233 if (start_track <= 1) {
1253 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1257 lba_to_msf(bp, sectors);
1260 be32enc(bp, sectors);
1264 be16enc(buf, size - 2);
1267 write_prdt(p, slot, cfis, buf, len);
1268 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1269 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1276 memset(buf, 0, sizeof(buf));
1280 if (len > sizeof(buf))
1282 write_prdt(p, slot, cfis, buf, len);
1283 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1284 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1291 uint8_t *bp, buf[50];
1293 msf = (acmd[1] >> 1) & 1;
1329 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1333 lba_to_msf(bp, sectors);
1336 be32enc(bp, sectors);
1359 be16enc(buf, size - 2);
1362 write_prdt(p, slot, cfis, buf, len);
1363 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1364 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1371 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1373 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1374 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1375 ahci_write_fis_d2h(p, slot, cfis, tfd);
1382 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1386 memset(buf, 0, sizeof(buf));
1389 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1390 write_prdt(p, slot, cfis, buf, sizeof(buf));
1391 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1395 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
1397 struct ahci_ioreq *aior;
1398 struct ahci_cmd_hdr *hdr;
1399 struct ahci_prdt_entry *prdt;
1400 struct blockif_req *breq;
1407 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1408 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1410 lba = be32dec(acmd + 2);
1411 if (acmd[0] == READ_10)
1412 len = be16dec(acmd + 7);
1414 len = be32dec(acmd + 6);
1416 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1417 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1423 * Pull request off free list
1425 aior = STAILQ_FIRST(&p->iofhd);
1426 assert(aior != NULL);
1427 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1433 breq = &aior->io_req;
1434 breq->br_offset = lba + done;
1435 ahci_build_iov(p, aior, prdt, hdr->prdtl);
1437 /* Mark this command in-flight. */
1438 p->pending |= 1 << slot;
1440 /* Stuff request onto busy list. */
1441 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1443 err = blockif_read(p->bctx, breq);
1448 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1456 if (len > sizeof(buf))
1458 memset(buf, 0, len);
1459 buf[0] = 0x70 | (1 << 7);
1460 buf[2] = p->sense_key;
1463 write_prdt(p, slot, cfis, buf, len);
1464 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1465 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1469 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1471 uint8_t *acmd = cfis + 0x40;
1474 switch (acmd[4] & 3) {
1478 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1479 tfd = ATA_S_READY | ATA_S_DSC;
1482 /* TODO eject media */
1483 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1484 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1486 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1489 ahci_write_fis_d2h(p, slot, cfis, tfd);
1493 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1501 len = be16dec(acmd + 7);
1503 code = acmd[2] & 0x3f;
1508 case MODEPAGE_RW_ERROR_RECOVERY:
1512 if (len > sizeof(buf))
1515 memset(buf, 0, sizeof(buf));
1516 be16enc(buf, 16 - 2);
1521 write_prdt(p, slot, cfis, buf, len);
1522 tfd = ATA_S_READY | ATA_S_DSC;
1525 case MODEPAGE_CD_CAPABILITIES:
1529 if (len > sizeof(buf))
1532 memset(buf, 0, sizeof(buf));
1533 be16enc(buf, 30 - 2);
1539 be16enc(&buf[18], 2);
1540 be16enc(&buf[20], 512);
1541 write_prdt(p, slot, cfis, buf, len);
1542 tfd = ATA_S_READY | ATA_S_DSC;
1551 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1553 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1558 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1560 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1563 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1564 ahci_write_fis_d2h(p, slot, cfis, tfd);
1568 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1576 /* we don't support asynchronous operation */
1577 if (!(acmd[1] & 1)) {
1578 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1580 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1585 len = be16dec(acmd + 7);
1586 if (len > sizeof(buf))
1589 memset(buf, 0, sizeof(buf));
1590 be16enc(buf, 8 - 2);
1594 write_prdt(p, slot, cfis, buf, len);
1595 tfd = ATA_S_READY | ATA_S_DSC;
1597 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1598 ahci_write_fis_d2h(p, slot, cfis, tfd);
1602 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1612 for (i = 0; i < 16; i++)
1613 DPRINTF("%02x ", acmd[i]);
1619 case TEST_UNIT_READY:
1620 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1621 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1624 atapi_inquiry(p, slot, cfis);
1627 atapi_read_capacity(p, slot, cfis);
1631 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1632 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1635 atapi_read_toc(p, slot, cfis);
1638 atapi_report_luns(p, slot, cfis);
1642 atapi_read(p, slot, cfis, 0);
1645 atapi_request_sense(p, slot, cfis);
1647 case START_STOP_UNIT:
1648 atapi_start_stop_unit(p, slot, cfis);
1651 atapi_mode_sense(p, slot, cfis);
1653 case GET_EVENT_STATUS_NOTIFICATION:
1654 atapi_get_event_status_notification(p, slot, cfis);
1657 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1658 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1660 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1661 ATA_S_READY | ATA_S_ERROR);
1667 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1670 p->tfd |= ATA_S_BUSY;
1672 case ATA_ATA_IDENTIFY:
1673 handle_identify(p, slot, cfis);
1675 case ATA_SETFEATURES:
1678 case ATA_SF_ENAB_SATA_SF:
1680 case ATA_SATA_SF_AN:
1681 p->tfd = ATA_S_DSC | ATA_S_READY;
1684 p->tfd = ATA_S_ERROR | ATA_S_READY;
1685 p->tfd |= (ATA_ERROR_ABORT << 8);
1689 case ATA_SF_ENAB_WCACHE:
1690 case ATA_SF_DIS_WCACHE:
1691 case ATA_SF_ENAB_RCACHE:
1692 case ATA_SF_DIS_RCACHE:
1693 p->tfd = ATA_S_DSC | ATA_S_READY;
1695 case ATA_SF_SETXFER:
1697 switch (cfis[12] & 0xf8) {
1703 p->xfermode = (cfis[12] & 0x7);
1706 p->tfd = ATA_S_DSC | ATA_S_READY;
1710 p->tfd = ATA_S_ERROR | ATA_S_READY;
1711 p->tfd |= (ATA_ERROR_ABORT << 8);
1714 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1718 if (cfis[12] != 0 &&
1719 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1720 p->tfd = ATA_S_ERROR | ATA_S_READY;
1721 p->tfd |= (ATA_ERROR_ABORT << 8);
1723 p->mult_sectors = cfis[12];
1724 p->tfd = ATA_S_DSC | ATA_S_READY;
1726 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1734 case ATA_READ_MUL48:
1735 case ATA_WRITE_MUL48:
1738 case ATA_READ_DMA48:
1739 case ATA_WRITE_DMA48:
1740 case ATA_READ_FPDMA_QUEUED:
1741 case ATA_WRITE_FPDMA_QUEUED:
1742 ahci_handle_rw(p, slot, cfis, 0);
1744 case ATA_FLUSHCACHE:
1745 case ATA_FLUSHCACHE48:
1746 ahci_handle_flush(p, slot, cfis);
1748 case ATA_DATA_SET_MANAGEMENT:
1749 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1750 cfis[13] == 0 && cfis[12] == 1) {
1751 ahci_handle_dsm_trim(p, slot, cfis, 0);
1754 ahci_write_fis_d2h(p, slot, cfis,
1755 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1757 case ATA_SEND_FPDMA_QUEUED:
1758 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1759 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1760 cfis[11] == 0 && cfis[3] == 1) {
1761 ahci_handle_dsm_trim(p, slot, cfis, 0);
1764 ahci_write_fis_d2h(p, slot, cfis,
1765 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1767 case ATA_READ_LOG_EXT:
1768 case ATA_READ_LOG_DMA_EXT:
1769 ahci_handle_read_log(p, slot, cfis);
1771 case ATA_SECURITY_FREEZE_LOCK:
1774 ahci_write_fis_d2h(p, slot, cfis,
1775 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1777 case ATA_CHECK_POWER_MODE:
1778 cfis[12] = 0xff; /* always on */
1779 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1781 case ATA_STANDBY_CMD:
1782 case ATA_STANDBY_IMMEDIATE:
1784 case ATA_IDLE_IMMEDIATE:
1786 case ATA_READ_VERIFY:
1787 case ATA_READ_VERIFY48:
1788 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1790 case ATA_ATAPI_IDENTIFY:
1791 handle_atapi_identify(p, slot, cfis);
1793 case ATA_PACKET_CMD:
1795 ahci_write_fis_d2h(p, slot, cfis,
1796 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1798 handle_packet_cmd(p, slot, cfis);
1801 WPRINTF("Unsupported cmd:%02x", cfis[2]);
1802 ahci_write_fis_d2h(p, slot, cfis,
1803 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1809 ahci_handle_slot(struct ahci_port *p, int slot)
1811 struct ahci_cmd_hdr *hdr;
1813 struct ahci_prdt_entry *prdt;
1815 struct pci_ahci_softc *sc;
1822 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1824 cfl = (hdr->flags & 0x1f) * 4;
1826 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1827 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1829 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1832 for (i = 0; i < cfl; i++) {
1835 DPRINTF("%02x ", cfis[i]);
1839 for (i = 0; i < hdr->prdtl; i++) {
1840 DPRINTF("%d@%08"PRIx64"", prdt->dbc & 0x3fffff, prdt->dba);
1845 if (cfis[0] != FIS_TYPE_REGH2D) {
1846 WPRINTF("Not a H2D FIS:%02x", cfis[0]);
1850 if (cfis[1] & 0x80) {
1851 ahci_handle_cmd(p, slot, cfis);
1853 if (cfis[15] & (1 << 2))
1855 else if (p->reset) {
1859 p->ci &= ~(1 << slot);
1864 ahci_handle_port(struct ahci_port *p)
1867 if (!(p->cmd & AHCI_P_CMD_ST))
1871 * Search for any new commands to issue ignoring those that
1872 * are already in-flight. Stop if device is busy or in error.
1874 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) {
1875 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0)
1877 if (p->waitforclear)
1879 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) {
1880 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1881 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT;
1882 ahci_handle_slot(p, p->ccs);
1888 * blockif callback routine - this runs in the context of the blockif
1889 * i/o thread, so the mutex needs to be acquired.
1892 ata_ioreq_cb(struct blockif_req *br, int err)
1894 struct ahci_cmd_hdr *hdr;
1895 struct ahci_ioreq *aior;
1896 struct ahci_port *p;
1897 struct pci_ahci_softc *sc;
1902 DPRINTF("%s %d", __func__, err);
1905 aior = br->br_param;
1910 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1912 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1913 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1914 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1916 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1917 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1918 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1921 pthread_mutex_lock(&sc->mtx);
1924 * Delete the blockif request from the busy list
1926 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1929 * Move the blockif request back to the free list
1931 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1934 hdr->prdbc = aior->done;
1936 if (!err && aior->more) {
1938 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1940 ahci_handle_rw(p, slot, cfis, aior->done);
1945 tfd = ATA_S_READY | ATA_S_DSC;
1947 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1949 ahci_write_fis_sdb(p, slot, cfis, tfd);
1951 ahci_write_fis_d2h(p, slot, cfis, tfd);
1954 * This command is now complete.
1956 p->pending &= ~(1 << slot);
1958 ahci_check_stopped(p);
1959 ahci_handle_port(p);
1961 pthread_mutex_unlock(&sc->mtx);
1962 DPRINTF("%s exit", __func__);
1966 atapi_ioreq_cb(struct blockif_req *br, int err)
1968 struct ahci_cmd_hdr *hdr;
1969 struct ahci_ioreq *aior;
1970 struct ahci_port *p;
1971 struct pci_ahci_softc *sc;
1976 DPRINTF("%s %d", __func__, err);
1978 aior = br->br_param;
1983 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1985 pthread_mutex_lock(&sc->mtx);
1988 * Delete the blockif request from the busy list
1990 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1993 * Move the blockif request back to the free list
1995 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1998 hdr->prdbc = aior->done;
2000 if (!err && aior->more) {
2001 atapi_read(p, slot, cfis, aior->done);
2006 tfd = ATA_S_READY | ATA_S_DSC;
2008 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
2010 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
2012 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
2013 ahci_write_fis_d2h(p, slot, cfis, tfd);
2016 * This command is now complete.
2018 p->pending &= ~(1 << slot);
2020 ahci_check_stopped(p);
2021 ahci_handle_port(p);
2023 pthread_mutex_unlock(&sc->mtx);
2024 DPRINTF("%s exit", __func__);
2028 pci_ahci_ioreq_init(struct ahci_port *pr)
2030 struct ahci_ioreq *vr;
2033 pr->ioqsz = blockif_queuesz(pr->bctx);
2034 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
2035 STAILQ_INIT(&pr->iofhd);
2038 * Add all i/o request entries to the free queue
2040 for (i = 0; i < pr->ioqsz; i++) {
2044 vr->io_req.br_callback = ata_ioreq_cb;
2046 vr->io_req.br_callback = atapi_ioreq_cb;
2047 vr->io_req.br_param = vr;
2048 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
2051 TAILQ_INIT(&pr->iobhd);
2055 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2057 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2058 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2059 struct ahci_port *p = &sc->port[port];
2061 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2062 port, offset, value);
2082 p->ie = value & 0xFDC000FF;
2087 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2088 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2089 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2090 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK);
2091 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2092 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2093 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2094 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value;
2096 if (!(value & AHCI_P_CMD_ST)) {
2101 p->cmd |= AHCI_P_CMD_CR;
2102 clb = (uint64_t)p->clbu << 32 | p->clb;
2103 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
2104 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
2107 if (value & AHCI_P_CMD_FRE) {
2110 p->cmd |= AHCI_P_CMD_FR;
2111 fb = (uint64_t)p->fbu << 32 | p->fb;
2112 /* we don't support FBSCP, so rfis size is 256Bytes */
2113 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
2115 p->cmd &= ~AHCI_P_CMD_FR;
2118 if (value & AHCI_P_CMD_CLO) {
2119 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ);
2120 p->cmd &= ~AHCI_P_CMD_CLO;
2123 if (value & AHCI_P_CMD_ICC_MASK) {
2124 p->cmd &= ~AHCI_P_CMD_ICC_MASK;
2127 ahci_handle_port(p);
2133 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"", offset);
2137 if (!(p->cmd & AHCI_P_CMD_ST)) {
2138 if (value & ATA_SC_DET_RESET)
2150 ahci_handle_port(p);
2160 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2162 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2170 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"", offset);
2173 if (value & AHCI_GHC_HR) {
2177 if (value & AHCI_GHC_IE)
2178 sc->ghc |= AHCI_GHC_IE;
2180 sc->ghc &= ~AHCI_GHC_IE;
2181 ahci_generate_intr(sc, 0xffffffff);
2185 ahci_generate_intr(sc, value);
2193 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
2194 int baridx, uint64_t offset, int size, uint64_t value)
2196 struct pci_ahci_softc *sc = pi->pi_arg;
2198 assert(baridx == 5);
2199 assert((offset % 4) == 0 && size == 4);
2201 pthread_mutex_lock(&sc->mtx);
2203 if (offset < AHCI_OFFSET)
2204 pci_ahci_host_write(sc, offset, value);
2205 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2206 pci_ahci_port_write(sc, offset, value);
2208 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"", offset);
2210 pthread_mutex_unlock(&sc->mtx);
2214 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2230 uint32_t *p = &sc->cap;
2231 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2239 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x",
2246 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2249 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2250 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2270 uint32_t *p= &sc->port[port].clb;
2271 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2280 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x",
2281 port, offset, value);
2287 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2288 uint64_t regoff, int size)
2290 struct pci_ahci_softc *sc = pi->pi_arg;
2294 assert(baridx == 5);
2295 assert(size == 1 || size == 2 || size == 4);
2296 assert((regoff & (size - 1)) == 0);
2298 pthread_mutex_lock(&sc->mtx);
2300 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */
2301 if (offset < AHCI_OFFSET)
2302 value = pci_ahci_host_read(sc, offset);
2303 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2304 value = pci_ahci_port_read(sc, offset);
2307 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"",
2310 value >>= 8 * (regoff & 0x3);
2312 pthread_mutex_unlock(&sc->mtx);
2318 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2320 char bident[sizeof("XX:XX:XX")];
2321 struct blockif_ctxt *bctxt;
2322 struct pci_ahci_softc *sc;
2327 char *bopt, *uopt, *xopts, *config;
2335 dbg = fopen("/tmp/log", "w+");
2338 sc = calloc(1, sizeof(struct pci_ahci_softc));
2341 pthread_mutex_init(&sc->mtx, NULL);
2346 for (p = 0; p < MAX_PORTS && opts != NULL; p++, opts = next) {
2347 struct ata_params *ata_ident = &sc->port[p].ata_ident;
2348 memset(ata_ident, 0, sizeof(struct ata_params));
2350 /* Identify and cut off type of present port. */
2351 if (strncmp(opts, "hd:", 3) == 0) {
2354 } else if (strncmp(opts, "cd:", 3) == 0) {
2359 /* Find and cut off the next port options. */
2360 next = strstr(opts, ",hd:");
2361 next2 = strstr(opts, ",cd:");
2362 if (next == NULL || (next2 != NULL && next2 < next))
2372 uopt = strdup(opts);
2374 fp = open_memstream(&bopt, &block_len);
2378 for (xopts = strtok(uopt, ",");
2380 xopts = strtok(NULL, ",")) {
2382 /* First option assume as block filename. */
2385 * Create an identifier for the backing file.
2386 * Use parts of the md5 sum of the filename
2388 char ident[AHCI_PORT_IDENT];
2390 MD5Update(&mdctx, opts, strlen(opts));
2391 MD5Final(digest, &mdctx);
2392 snprintf(ident, AHCI_PORT_IDENT,
2393 "BHYVE-%02X%02X-%02X%02X-%02X%02X",
2394 digest[0], digest[1], digest[2], digest[3], digest[4],
2396 ata_string((uint8_t*)&ata_ident->serial, ident, 20);
2397 ata_string((uint8_t*)&ata_ident->revision, "001", 8);
2399 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DVD ROM", 40);
2402 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DISK", 40);
2406 if ((config = strchr(xopts, '=')) != NULL) {
2408 if (!strcmp("nmrr", xopts)) {
2409 ata_ident->media_rotation_rate = atoi(config);
2411 else if (!strcmp("ser", xopts)) {
2412 ata_string((uint8_t*)(&ata_ident->serial), config, 20);
2414 else if (!strcmp("rev", xopts)) {
2415 ata_string((uint8_t*)(&ata_ident->revision), config, 8);
2417 else if (!strcmp("model", xopts)) {
2418 ata_string((uint8_t*)(&ata_ident->model), config, 40);
2421 /* Pass all other options to blockif_open. */
2423 fprintf(fp, "%s%s", comma ? "," : "", xopts);
2428 /* Pass all other options to blockif_open. */
2429 fprintf(fp, "%s%s", comma ? "," : "", xopts);
2437 DPRINTF("%s\n", bopt);
2440 * Attempt to open the backing image. Use the PCI slot/func
2441 * and the port number for the identifier string.
2443 snprintf(bident, sizeof(bident), "%d:%d:%d", pi->pi_slot,
2445 bctxt = blockif_open(bopt, bident);
2448 if (bctxt == NULL) {
2453 sc->port[p].bctx = bctxt;
2454 sc->port[p].pr_sc = sc;
2455 sc->port[p].port = p;
2456 sc->port[p].atapi = atapi;
2458 ata_identify_init(&sc->port[p], atapi);
2461 * Allocate blockif request structures and add them
2464 pci_ahci_ioreq_init(&sc->port[p]);
2467 if (sc->port[p].ioqsz < slots)
2468 slots = sc->port[p].ioqsz;
2472 /* Intel ICH8 AHCI */
2474 if (sc->ports < DEF_PORTS)
2475 sc->ports = DEF_PORTS;
2476 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2477 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2478 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2479 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2480 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2483 sc->cap2 = AHCI_CAP2_APST;
2486 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2487 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2488 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2489 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2490 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2491 p = MIN(sc->ports, 16);
2492 p = flsl(p) - ((p & (p - 1)) ? 0 : 1);
2493 pci_emul_add_msicap(pi, 1 << p);
2494 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2495 AHCI_OFFSET + sc->ports * AHCI_STEP);
2497 pci_lintr_request(pi);
2501 for (p = 0; p < sc->ports; p++) {
2502 if (sc->port[p].bctx != NULL)
2503 blockif_close(sc->port[p].bctx);
2512 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2515 return (pci_ahci_init(ctx, pi, opts, 0));
2519 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2522 return (pci_ahci_init(ctx, pi, opts, 1));
2525 #ifdef BHYVE_SNAPSHOT
2527 pci_ahci_snapshot_save_queues(struct ahci_port *port,
2528 struct vm_snapshot_meta *meta)
2532 struct ahci_ioreq *ioreq;
2534 STAILQ_FOREACH(ioreq, &port->iofhd, io_flist) {
2535 idx = ((void *) ioreq - (void *) port->ioreq) / sizeof(*ioreq);
2536 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2540 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2542 TAILQ_FOREACH(ioreq, &port->iobhd, io_blist) {
2543 idx = ((void *) ioreq - (void *) port->ioreq) / sizeof(*ioreq);
2544 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2547 * Snapshot only the busy requests; other requests are
2550 ret = blockif_snapshot_req(&ioreq->io_req, meta);
2552 fprintf(stderr, "%s: failed to snapshot req\r\n",
2559 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2566 pci_ahci_snapshot_restore_queues(struct ahci_port *port,
2567 struct vm_snapshot_meta *meta)
2571 struct ahci_ioreq *ioreq;
2573 /* Empty the free queue before restoring. */
2574 while (!STAILQ_EMPTY(&port->iofhd))
2575 STAILQ_REMOVE_HEAD(&port->iofhd, io_flist);
2577 /* Restore the free queue. */
2579 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2583 STAILQ_INSERT_TAIL(&port->iofhd, &port->ioreq[idx], io_flist);
2586 /* Restore the busy queue. */
2588 SNAPSHOT_VAR_OR_LEAVE(idx, meta, ret, done);
2592 ioreq = &port->ioreq[idx];
2593 TAILQ_INSERT_TAIL(&port->iobhd, ioreq, io_blist);
2596 * Restore only the busy requests; other requests are
2599 ret = blockif_snapshot_req(&ioreq->io_req, meta);
2601 fprintf(stderr, "%s: failed to restore request\r\n",
2606 /* Re-enqueue the requests in the block interface. */
2608 ret = blockif_read(port->bctx, &ioreq->io_req);
2610 ret = blockif_write(port->bctx, &ioreq->io_req);
2614 "%s: failed to re-enqueue request\r\n",
2625 pci_ahci_snapshot(struct vm_snapshot_meta *meta)
2629 struct pci_devinst *pi;
2630 struct pci_ahci_softc *sc;
2631 struct ahci_port *port;
2632 struct ahci_cmd_hdr *hdr;
2633 struct ahci_ioreq *ioreq;
2635 pi = meta->dev_data;
2638 /* TODO: add mtx lock/unlock */
2640 SNAPSHOT_VAR_OR_LEAVE(sc->ports, meta, ret, done);
2641 SNAPSHOT_VAR_OR_LEAVE(sc->cap, meta, ret, done);
2642 SNAPSHOT_VAR_OR_LEAVE(sc->ghc, meta, ret, done);
2643 SNAPSHOT_VAR_OR_LEAVE(sc->is, meta, ret, done);
2644 SNAPSHOT_VAR_OR_LEAVE(sc->pi, meta, ret, done);
2645 SNAPSHOT_VAR_OR_LEAVE(sc->vs, meta, ret, done);
2646 SNAPSHOT_VAR_OR_LEAVE(sc->ccc_ctl, meta, ret, done);
2647 SNAPSHOT_VAR_OR_LEAVE(sc->ccc_pts, meta, ret, done);
2648 SNAPSHOT_VAR_OR_LEAVE(sc->em_loc, meta, ret, done);
2649 SNAPSHOT_VAR_OR_LEAVE(sc->em_ctl, meta, ret, done);
2650 SNAPSHOT_VAR_OR_LEAVE(sc->cap2, meta, ret, done);
2651 SNAPSHOT_VAR_OR_LEAVE(sc->bohc, meta, ret, done);
2652 SNAPSHOT_VAR_OR_LEAVE(sc->lintr, meta, ret, done);
2654 for (i = 0; i < MAX_PORTS; i++) {
2655 port = &sc->port[i];
2657 if (meta->op == VM_SNAPSHOT_SAVE)
2660 SNAPSHOT_VAR_OR_LEAVE(bctx, meta, ret, done);
2661 SNAPSHOT_VAR_OR_LEAVE(port->port, meta, ret, done);
2663 /* Mostly for restore; save is ensured by the lines above. */
2664 if (((bctx == NULL) && (port->bctx != NULL)) ||
2665 ((bctx != NULL) && (port->bctx == NULL))) {
2666 fprintf(stderr, "%s: ports not matching\r\n", __func__);
2671 if (port->bctx == NULL)
2674 if (port->port != i) {
2675 fprintf(stderr, "%s: ports not matching: "
2676 "actual: %d expected: %d\r\n",
2677 __func__, port->port, i);
2682 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(port->cmd_lst,
2683 AHCI_CL_SIZE * AHCI_MAX_SLOTS, false, meta, ret, done);
2684 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(port->rfis, 256, false, meta,
2687 SNAPSHOT_VAR_OR_LEAVE(port->ata_ident, meta, ret, done);
2688 SNAPSHOT_VAR_OR_LEAVE(port->atapi, meta, ret, done);
2689 SNAPSHOT_VAR_OR_LEAVE(port->reset, meta, ret, done);
2690 SNAPSHOT_VAR_OR_LEAVE(port->waitforclear, meta, ret, done);
2691 SNAPSHOT_VAR_OR_LEAVE(port->mult_sectors, meta, ret, done);
2692 SNAPSHOT_VAR_OR_LEAVE(port->xfermode, meta, ret, done);
2693 SNAPSHOT_VAR_OR_LEAVE(port->err_cfis, meta, ret, done);
2694 SNAPSHOT_VAR_OR_LEAVE(port->sense_key, meta, ret, done);
2695 SNAPSHOT_VAR_OR_LEAVE(port->asc, meta, ret, done);
2696 SNAPSHOT_VAR_OR_LEAVE(port->ccs, meta, ret, done);
2697 SNAPSHOT_VAR_OR_LEAVE(port->pending, meta, ret, done);
2699 SNAPSHOT_VAR_OR_LEAVE(port->clb, meta, ret, done);
2700 SNAPSHOT_VAR_OR_LEAVE(port->clbu, meta, ret, done);
2701 SNAPSHOT_VAR_OR_LEAVE(port->fb, meta, ret, done);
2702 SNAPSHOT_VAR_OR_LEAVE(port->fbu, meta, ret, done);
2703 SNAPSHOT_VAR_OR_LEAVE(port->ie, meta, ret, done);
2704 SNAPSHOT_VAR_OR_LEAVE(port->cmd, meta, ret, done);
2705 SNAPSHOT_VAR_OR_LEAVE(port->unused0, meta, ret, done);
2706 SNAPSHOT_VAR_OR_LEAVE(port->tfd, meta, ret, done);
2707 SNAPSHOT_VAR_OR_LEAVE(port->sig, meta, ret, done);
2708 SNAPSHOT_VAR_OR_LEAVE(port->ssts, meta, ret, done);
2709 SNAPSHOT_VAR_OR_LEAVE(port->sctl, meta, ret, done);
2710 SNAPSHOT_VAR_OR_LEAVE(port->serr, meta, ret, done);
2711 SNAPSHOT_VAR_OR_LEAVE(port->sact, meta, ret, done);
2712 SNAPSHOT_VAR_OR_LEAVE(port->ci, meta, ret, done);
2713 SNAPSHOT_VAR_OR_LEAVE(port->sntf, meta, ret, done);
2714 SNAPSHOT_VAR_OR_LEAVE(port->fbs, meta, ret, done);
2715 SNAPSHOT_VAR_OR_LEAVE(port->ioqsz, meta, ret, done);
2717 for (j = 0; j < port->ioqsz; j++) {
2718 ioreq = &port->ioreq[j];
2720 /* blockif_req snapshot done only for busy requests. */
2721 hdr = (struct ahci_cmd_hdr *)(port->cmd_lst +
2722 ioreq->slot * AHCI_CL_SIZE);
2723 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(ioreq->cfis,
2724 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry),
2725 false, meta, ret, done);
2727 SNAPSHOT_VAR_OR_LEAVE(ioreq->len, meta, ret, done);
2728 SNAPSHOT_VAR_OR_LEAVE(ioreq->done, meta, ret, done);
2729 SNAPSHOT_VAR_OR_LEAVE(ioreq->slot, meta, ret, done);
2730 SNAPSHOT_VAR_OR_LEAVE(ioreq->more, meta, ret, done);
2731 SNAPSHOT_VAR_OR_LEAVE(ioreq->readop, meta, ret, done);
2734 /* Perform save / restore specific operations. */
2735 if (meta->op == VM_SNAPSHOT_SAVE) {
2736 ret = pci_ahci_snapshot_save_queues(port, meta);
2739 } else if (meta->op == VM_SNAPSHOT_RESTORE) {
2740 ret = pci_ahci_snapshot_restore_queues(port, meta);
2748 ret = blockif_snapshot(port->bctx, meta);
2750 fprintf(stderr, "%s: failed to restore blockif\r\n",
2761 pci_ahci_pause(struct vmctx *ctx, struct pci_devinst *pi)
2763 struct pci_ahci_softc *sc;
2764 struct blockif_ctxt *bctxt;
2769 for (i = 0; i < MAX_PORTS; i++) {
2770 bctxt = sc->port[i].bctx;
2774 blockif_pause(bctxt);
2781 pci_ahci_resume(struct vmctx *ctx, struct pci_devinst *pi)
2783 struct pci_ahci_softc *sc;
2784 struct blockif_ctxt *bctxt;
2789 for (i = 0; i < MAX_PORTS; i++) {
2790 bctxt = sc->port[i].bctx;
2794 blockif_resume(bctxt);
2802 * Use separate emulation names to distinguish drive and atapi devices
2804 struct pci_devemu pci_de_ahci = {
2806 .pe_init = pci_ahci_hd_init,
2807 .pe_barwrite = pci_ahci_write,
2808 .pe_barread = pci_ahci_read,
2809 #ifdef BHYVE_SNAPSHOT
2810 .pe_snapshot = pci_ahci_snapshot,
2811 .pe_pause = pci_ahci_pause,
2812 .pe_resume = pci_ahci_resume,
2815 PCI_EMUL_SET(pci_de_ahci);
2817 struct pci_devemu pci_de_ahci_hd = {
2818 .pe_emu = "ahci-hd",
2819 .pe_init = pci_ahci_hd_init,
2820 .pe_barwrite = pci_ahci_write,
2821 .pe_barread = pci_ahci_read,
2822 #ifdef BHYVE_SNAPSHOT
2823 .pe_snapshot = pci_ahci_snapshot,
2824 .pe_pause = pci_ahci_pause,
2825 .pe_resume = pci_ahci_resume,
2828 PCI_EMUL_SET(pci_de_ahci_hd);
2830 struct pci_devemu pci_de_ahci_cd = {
2831 .pe_emu = "ahci-cd",
2832 .pe_init = pci_ahci_atapi_init,
2833 .pe_barwrite = pci_ahci_write,
2834 .pe_barread = pci_ahci_read,
2835 #ifdef BHYVE_SNAPSHOT
2836 .pe_snapshot = pci_ahci_snapshot,
2837 .pe_pause = pci_ahci_pause,
2838 .pe_resume = pci_ahci_resume,
2841 PCI_EMUL_SET(pci_de_ahci_cd);