2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
58 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
60 #define PxSIG_ATA 0x00000101 /* ATA drive */
61 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
64 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
65 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
66 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
67 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
68 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
69 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
70 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
71 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
77 #define TEST_UNIT_READY 0x00
78 #define REQUEST_SENSE 0x03
80 #define START_STOP_UNIT 0x1B
81 #define PREVENT_ALLOW 0x1E
82 #define READ_CAPACITY 0x25
84 #define POSITION_TO_ELEMENT 0x2B
86 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
87 #define MODE_SENSE_10 0x5A
92 * SCSI mode page codes
94 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
95 #define MODEPAGE_CD_CAPABILITIES 0x2A
102 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
104 #define DPRINTF(format, arg...)
106 #define WPRINTF(format, arg...) printf(format, ##arg)
109 struct blockif_req io_req;
110 struct ahci_port *io_pr;
111 STAILQ_ENTRY(ahci_ioreq) io_list;
120 struct blockif_ctxt *bctx;
121 struct pci_ahci_softc *pr_sc;
152 struct ahci_ioreq *ioreq;
154 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
157 struct ahci_cmd_hdr {
162 uint32_t reserved[4];
165 struct ahci_prdt_entry {
168 #define DBCMASK 0x3fffff
172 struct pci_ahci_softc {
173 struct pci_devinst *asc_pi;
187 struct ahci_port port[MAX_PORTS];
189 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
191 static inline void lba_to_msf(uint8_t *buf, int lba)
194 buf[0] = (lba / 75) / 60;
195 buf[1] = (lba / 75) % 60;
200 * generate HBA intr depending on whether or not ports within
201 * the controller have an interrupt pending.
204 ahci_generate_intr(struct pci_ahci_softc *sc)
208 for (i = 0; i < sc->ports; i++) {
209 struct ahci_port *pr;
215 DPRINTF("%s %x\n", __func__, sc->is);
217 if (sc->is && (sc->ghc & AHCI_GHC_IE))
218 pci_generate_msi(sc->asc_pi, 0);
222 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
224 int offset, len, irq;
226 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
230 case FIS_TYPE_REGD2H:
235 case FIS_TYPE_SETDEVBITS:
240 case FIS_TYPE_PIOSETUP:
246 WPRINTF("unsupported fis type %d\n", ft);
249 memcpy(p->rfis + offset, fis, len);
252 ahci_generate_intr(p->pr_sc);
257 ahci_write_fis_piosetup(struct ahci_port *p)
261 memset(fis, 0, sizeof(fis));
262 fis[0] = FIS_TYPE_PIOSETUP;
263 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
267 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd)
272 error = (tfd >> 8) & 0xff;
273 memset(fis, 0, sizeof(fis));
276 *(uint32_t *)(fis + 4) = (1 << slot);
277 if (fis[2] & ATA_S_ERROR)
278 p->is |= AHCI_P_IX_TFE;
280 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
284 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
289 error = (tfd >> 8) & 0xff;
290 memset(fis, 0, sizeof(fis));
291 fis[0] = FIS_TYPE_REGD2H;
305 if (fis[2] & ATA_S_ERROR)
306 p->is |= AHCI_P_IX_TFE;
308 p->ci &= ~(1 << slot);
309 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
313 ahci_write_reset_fis_d2h(struct ahci_port *p)
317 memset(fis, 0, sizeof(fis));
318 fis[0] = FIS_TYPE_REGD2H;
326 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
330 ahci_port_reset(struct ahci_port *pr)
335 pr->xfermode = ATA_UDMA6;
336 pr->mult_sectors = 128;
339 pr->ssts = ATA_SS_DET_NO_DEVICE;
340 pr->sig = 0xFFFFFFFF;
344 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 |
346 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
349 pr->tfd |= ATA_S_READY;
351 pr->sig = PxSIG_ATAPI;
352 ahci_write_reset_fis_d2h(pr);
356 ahci_reset(struct pci_ahci_softc *sc)
360 sc->ghc = AHCI_GHC_AE;
362 for (i = 0; i < sc->ports; i++) {
365 ahci_port_reset(&sc->port[i]);
370 ata_string(uint8_t *dest, const char *src, int len)
374 for (i = 0; i < len; i++) {
376 dest[i ^ 1] = *src++;
383 atapi_string(uint8_t *dest, const char *src, int len)
387 for (i = 0; i < len; i++) {
396 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
399 struct ahci_ioreq *aior;
400 struct blockif_req *breq;
401 struct pci_ahci_softc *sc;
402 struct ahci_prdt_entry *prdt;
403 struct ahci_cmd_hdr *hdr;
406 int i, err, iovcnt, ncq, readop;
409 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
410 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
415 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
416 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
419 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
420 cfis[2] == ATA_READ_FPDMA_QUEUED) {
421 lba = ((uint64_t)cfis[10] << 40) |
422 ((uint64_t)cfis[9] << 32) |
423 ((uint64_t)cfis[8] << 24) |
424 ((uint64_t)cfis[6] << 16) |
425 ((uint64_t)cfis[5] << 8) |
427 len = cfis[11] << 8 | cfis[3];
431 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
432 lba = ((uint64_t)cfis[10] << 40) |
433 ((uint64_t)cfis[9] << 32) |
434 ((uint64_t)cfis[8] << 24) |
435 ((uint64_t)cfis[6] << 16) |
436 ((uint64_t)cfis[5] << 8) |
438 len = cfis[13] << 8 | cfis[12];
442 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
443 (cfis[5] << 8) | cfis[4];
448 lba *= blockif_sectsz(p->bctx);
449 len *= blockif_sectsz(p->bctx);
452 * Pull request off free list
454 aior = STAILQ_FIRST(&p->iofhd);
455 assert(aior != NULL);
456 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
461 breq = &aior->io_req;
462 breq->br_offset = lba + done;
463 iovcnt = hdr->prdtl - seek;
464 if (iovcnt > BLOCKIF_IOV_MAX) {
465 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
466 iovcnt = BLOCKIF_IOV_MAX;
469 breq->br_iovcnt = iovcnt;
472 * Build up the iovec based on the prdt
474 for (i = 0; i < iovcnt; i++) {
477 dbcsz = (prdt->dbc & DBCMASK) + 1;
478 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
480 breq->br_iov[i].iov_len = dbcsz;
485 err = blockif_read(p->bctx, breq);
487 err = blockif_write(p->bctx, breq);
490 if (!aior->prdtl && ncq)
491 p->ci &= ~(1 << slot);
495 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
497 struct ahci_ioreq *aior;
498 struct blockif_req *breq;
502 * Pull request off free list
504 aior = STAILQ_FIRST(&p->iofhd);
505 assert(aior != NULL);
506 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
512 breq = &aior->io_req;
514 err = blockif_flush(p->bctx, breq);
519 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
522 struct ahci_cmd_hdr *hdr;
523 struct ahci_prdt_entry *prdt;
527 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
530 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
531 for (i = 0; i < hdr->prdtl && len; i++) {
535 dbcsz = (prdt->dbc & DBCMASK) + 1;
536 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
537 memcpy(ptr, from, dbcsz);
542 hdr->prdbc = size - len;
546 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
548 struct ahci_cmd_hdr *hdr;
550 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
551 if (p->atapi || hdr->prdtl == 0) {
552 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
553 p->is |= AHCI_P_IX_TFE;
558 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
559 memset(buf, 0, sizeof(buf));
561 /* TODO emulate different serial? */
562 ata_string((uint8_t *)(buf+10), "123456", 20);
563 ata_string((uint8_t *)(buf+23), "001", 8);
564 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
565 buf[47] = (0x8000 | 128);
567 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
569 buf[53] = (1 << 1 | 1 << 2);
571 buf[59] = (0x100 | p->mult_sectors);
573 buf[61] = (sectors >> 16);
575 if (p->xfermode & ATA_WDMA0)
576 buf[63] |= (1 << ((p->xfermode & 7) + 8));
583 buf[76] = (1 << 8 | 1 << 2);
586 buf[82] = (1 << 5 | 1 << 14);
587 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
589 buf[85] = (1 << 5 | 1 << 14);
590 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
593 if (p->xfermode & ATA_UDMA0)
594 buf[88] |= (1 << ((p->xfermode & 7) + 8));
595 buf[93] = (1 | 1 <<14);
597 buf[101] = (sectors >> 16);
598 buf[102] = (sectors >> 32);
599 buf[103] = (sectors >> 48);
600 ahci_write_fis_piosetup(p);
601 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
602 p->tfd = ATA_S_DSC | ATA_S_READY;
603 p->is |= AHCI_P_IX_DP;
605 p->ci &= ~(1 << slot);
606 ahci_generate_intr(p->pr_sc);
610 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
613 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
614 p->is |= AHCI_P_IX_TFE;
618 memset(buf, 0, sizeof(buf));
619 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
620 /* TODO emulate different serial? */
621 ata_string((uint8_t *)(buf+10), "123456", 20);
622 ata_string((uint8_t *)(buf+23), "001", 8);
623 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
624 buf[49] = (1 << 9 | 1 << 8);
625 buf[50] = (1 << 14 | 1);
626 buf[53] = (1 << 2 | 1 << 1);
634 buf[76] = (1 << 2 | 1 << 1);
636 buf[80] = (0x1f << 4);
642 buf[88] = (1 << 14 | 0x7f);
643 ahci_write_fis_piosetup(p);
644 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
645 p->tfd = ATA_S_DSC | ATA_S_READY;
646 p->is |= AHCI_P_IX_DHR;
648 p->ci &= ~(1 << slot);
649 ahci_generate_intr(p->pr_sc);
653 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
669 atapi_string(buf + 8, "BHYVE", 8);
670 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
671 atapi_string(buf + 32, "001", 4);
676 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
677 write_prdt(p, slot, cfis, buf, len);
678 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
682 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
687 sectors = blockif_size(p->bctx) / 2048;
688 be32enc(buf, sectors - 1);
689 be32enc(buf + 4, 2048);
690 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
691 write_prdt(p, slot, cfis, buf, sizeof(buf));
692 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
696 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
704 len = be16dec(acmd + 7);
705 format = acmd[9] >> 6;
711 uint8_t start_track, buf[20], *bp;
713 msf = (acmd[1] >> 1) & 1;
714 start_track = acmd[6];
715 if (start_track > 1 && start_track != 0xaa) {
717 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
719 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
720 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
721 ahci_write_fis_d2h(p, slot, cfis, tfd);
727 if (start_track <= 1) {
747 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
751 lba_to_msf(bp, sectors);
754 be32enc(bp, sectors);
758 be16enc(buf, size - 2);
761 write_prdt(p, slot, cfis, buf, len);
762 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
763 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
770 memset(buf, 0, sizeof(buf));
774 if (len > sizeof(buf))
776 write_prdt(p, slot, cfis, buf, len);
777 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
778 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
785 uint8_t start_track, *bp, buf[50];
787 msf = (acmd[1] >> 1) & 1;
788 start_track = acmd[6];
824 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
828 lba_to_msf(bp, sectors);
831 be32enc(bp, sectors);
854 be16enc(buf, size - 2);
857 write_prdt(p, slot, cfis, buf, len);
858 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
859 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
866 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
868 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
869 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
870 ahci_write_fis_d2h(p, slot, cfis, tfd);
877 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
878 uint32_t done, int seek)
880 struct ahci_ioreq *aior;
881 struct ahci_cmd_hdr *hdr;
882 struct ahci_prdt_entry *prdt;
883 struct blockif_req *breq;
884 struct pci_ahci_softc *sc;
892 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
893 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
896 lba = be32dec(acmd + 2);
897 if (acmd[0] == READ_10)
898 len = be16dec(acmd + 7);
900 len = be32dec(acmd + 6);
902 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
903 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
909 * Pull request off free list
911 aior = STAILQ_FIRST(&p->iofhd);
912 assert(aior != NULL);
913 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
918 breq = &aior->io_req;
919 breq->br_offset = lba + done;
920 iovcnt = hdr->prdtl - seek;
921 if (iovcnt > BLOCKIF_IOV_MAX) {
922 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
923 iovcnt = BLOCKIF_IOV_MAX;
926 breq->br_iovcnt = iovcnt;
929 * Build up the iovec based on the prdt
931 for (i = 0; i < iovcnt; i++) {
934 dbcsz = (prdt->dbc & DBCMASK) + 1;
935 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
937 breq->br_iov[i].iov_len = dbcsz;
941 err = blockif_read(p->bctx, breq);
946 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
954 if (len > sizeof(buf))
957 buf[0] = 0x70 | (1 << 7);
958 buf[2] = p->sense_key;
961 write_prdt(p, slot, cfis, buf, len);
962 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
963 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
967 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
969 uint8_t *acmd = cfis + 0x40;
972 switch (acmd[4] & 3) {
976 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
977 tfd = ATA_S_READY | ATA_S_DSC;
980 /* TODO eject media */
981 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
982 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
984 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
987 ahci_write_fis_d2h(p, slot, cfis, tfd);
991 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
999 len = be16dec(acmd + 7);
1001 code = acmd[2] & 0x3f;
1006 case MODEPAGE_RW_ERROR_RECOVERY:
1010 if (len > sizeof(buf))
1013 memset(buf, 0, sizeof(buf));
1014 be16enc(buf, 16 - 2);
1019 write_prdt(p, slot, cfis, buf, len);
1020 tfd = ATA_S_READY | ATA_S_DSC;
1023 case MODEPAGE_CD_CAPABILITIES:
1027 if (len > sizeof(buf))
1030 memset(buf, 0, sizeof(buf));
1031 be16enc(buf, 30 - 2);
1037 be16enc(&buf[18], 2);
1038 be16enc(&buf[20], 512);
1039 write_prdt(p, slot, cfis, buf, len);
1040 tfd = ATA_S_READY | ATA_S_DSC;
1049 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1051 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1056 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1058 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1061 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1062 ahci_write_fis_d2h(p, slot, cfis, tfd);
1066 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1074 /* we don't support asynchronous operation */
1075 if (!(acmd[1] & 1)) {
1076 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1078 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1083 len = be16dec(acmd + 7);
1084 if (len > sizeof(buf))
1087 memset(buf, 0, sizeof(buf));
1088 be16enc(buf, 8 - 2);
1092 write_prdt(p, slot, cfis, buf, len);
1093 tfd = ATA_S_READY | ATA_S_DSC;
1095 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1096 ahci_write_fis_d2h(p, slot, cfis, tfd);
1100 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1110 for (i = 0; i < 16; i++)
1111 DPRINTF("%02x ", acmd[i]);
1117 case TEST_UNIT_READY:
1118 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1119 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1122 atapi_inquiry(p, slot, cfis);
1125 atapi_read_capacity(p, slot, cfis);
1129 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1130 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1133 atapi_read_toc(p, slot, cfis);
1137 atapi_read(p, slot, cfis, 0, 0);
1140 atapi_request_sense(p, slot, cfis);
1142 case START_STOP_UNIT:
1143 atapi_start_stop_unit(p, slot, cfis);
1146 atapi_mode_sense(p, slot, cfis);
1148 case GET_EVENT_STATUS_NOTIFICATION:
1149 atapi_get_event_status_notification(p, slot, cfis);
1152 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1153 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1155 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1156 ATA_S_READY | ATA_S_ERROR);
1162 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1166 case ATA_ATA_IDENTIFY:
1167 handle_identify(p, slot, cfis);
1169 case ATA_SETFEATURES:
1172 case ATA_SF_ENAB_WCACHE:
1173 case ATA_SF_DIS_WCACHE:
1174 case ATA_SF_ENAB_RCACHE:
1175 case ATA_SF_DIS_RCACHE:
1176 p->tfd = ATA_S_DSC | ATA_S_READY;
1178 case ATA_SF_SETXFER:
1180 switch (cfis[12] & 0xf8) {
1186 p->xfermode = (cfis[12] & 0x7);
1189 p->tfd = ATA_S_DSC | ATA_S_READY;
1193 p->tfd = ATA_S_ERROR | ATA_S_READY;
1194 p->tfd |= (ATA_ERROR_ABORT << 8);
1197 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1201 if (cfis[12] != 0 &&
1202 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1203 p->tfd = ATA_S_ERROR | ATA_S_READY;
1204 p->tfd |= (ATA_ERROR_ABORT << 8);
1206 p->mult_sectors = cfis[12];
1207 p->tfd = ATA_S_DSC | ATA_S_READY;
1209 p->is |= AHCI_P_IX_DP;
1210 p->ci &= ~(1 << slot);
1211 ahci_generate_intr(p->pr_sc);
1215 case ATA_READ_DMA48:
1216 case ATA_WRITE_DMA48:
1217 case ATA_READ_FPDMA_QUEUED:
1218 case ATA_WRITE_FPDMA_QUEUED:
1219 ahci_handle_dma(p, slot, cfis, 0, 0);
1221 case ATA_FLUSHCACHE:
1222 case ATA_FLUSHCACHE48:
1223 ahci_handle_flush(p, slot, cfis);
1225 case ATA_STANDBY_CMD:
1228 case ATA_STANDBY_IMMEDIATE:
1229 case ATA_IDLE_IMMEDIATE:
1231 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1233 case ATA_ATAPI_IDENTIFY:
1234 handle_atapi_identify(p, slot, cfis);
1236 case ATA_PACKET_CMD:
1238 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1239 p->is |= AHCI_P_IX_TFE;
1240 p->ci &= ~(1 << slot);
1241 ahci_generate_intr(p->pr_sc);
1243 handle_packet_cmd(p, slot, cfis);
1246 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1247 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1248 p->is |= AHCI_P_IX_TFE;
1249 p->ci &= ~(1 << slot);
1250 ahci_generate_intr(p->pr_sc);
1256 ahci_handle_slot(struct ahci_port *p, int slot)
1258 struct ahci_cmd_hdr *hdr;
1259 struct ahci_prdt_entry *prdt;
1260 struct pci_ahci_softc *sc;
1265 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1266 cfl = (hdr->flags & 0x1f) * 4;
1267 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1268 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1269 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1273 for (i = 0; i < cfl; i++) {
1276 DPRINTF("%02x ", cfis[i]);
1280 for (i = 0; i < hdr->prdtl; i++) {
1281 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1286 if (cfis[0] != FIS_TYPE_REGH2D) {
1287 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1291 if (cfis[1] & 0x80) {
1292 ahci_handle_cmd(p, slot, cfis);
1294 if (cfis[15] & (1 << 2))
1296 else if (p->reset) {
1300 p->ci &= ~(1 << slot);
1305 ahci_handle_port(struct ahci_port *p)
1309 if (!(p->cmd & AHCI_P_CMD_ST))
1312 for (i = 0; (i < 32) && p->ci; i++) {
1313 if (p->ci & (1 << i))
1314 ahci_handle_slot(p, i);
1319 * blockif callback routine - this runs in the context of the blockif
1320 * i/o thread, so the mutex needs to be acquired.
1323 ata_ioreq_cb(struct blockif_req *br, int err)
1325 struct ahci_cmd_hdr *hdr;
1326 struct ahci_ioreq *aior;
1327 struct ahci_port *p;
1328 struct pci_ahci_softc *sc;
1331 int pending, slot, ncq;
1333 DPRINTF("%s %d\n", __func__, err);
1336 aior = br->br_param;
1340 pending = aior->prdtl;
1342 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1344 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1345 cfis[2] == ATA_READ_FPDMA_QUEUED)
1348 pthread_mutex_lock(&sc->mtx);
1351 * Move the blockif request back to the free list
1353 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1355 if (pending && !err) {
1356 ahci_handle_dma(p, slot, cfis, aior->done,
1357 hdr->prdtl - pending);
1361 if (!err && aior->done == aior->len) {
1362 tfd = ATA_S_READY | ATA_S_DSC;
1366 hdr->prdbc = aior->len;
1368 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1371 p->serr |= (1 << slot);
1375 p->sact &= ~(1 << slot);
1376 ahci_write_fis_sdb(p, slot, tfd);
1378 ahci_write_fis_d2h(p, slot, cfis, tfd);
1381 pthread_mutex_unlock(&sc->mtx);
1382 DPRINTF("%s exit\n", __func__);
1386 atapi_ioreq_cb(struct blockif_req *br, int err)
1388 struct ahci_cmd_hdr *hdr;
1389 struct ahci_ioreq *aior;
1390 struct ahci_port *p;
1391 struct pci_ahci_softc *sc;
1396 DPRINTF("%s %d\n", __func__, err);
1398 aior = br->br_param;
1402 pending = aior->prdtl;
1404 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1406 pthread_mutex_lock(&sc->mtx);
1409 * Move the blockif request back to the free list
1411 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1413 if (pending && !err) {
1414 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1418 if (!err && aior->done == aior->len) {
1419 tfd = ATA_S_READY | ATA_S_DSC;
1420 hdr->prdbc = aior->len;
1422 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1424 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1428 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1429 ahci_write_fis_d2h(p, slot, cfis, tfd);
1432 pthread_mutex_unlock(&sc->mtx);
1433 DPRINTF("%s exit\n", __func__);
1437 pci_ahci_ioreq_init(struct ahci_port *pr)
1439 struct ahci_ioreq *vr;
1442 pr->ioqsz = blockif_queuesz(pr->bctx);
1443 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1444 STAILQ_INIT(&pr->iofhd);
1447 * Add all i/o request entries to the free queue
1449 for (i = 0; i < pr->ioqsz; i++) {
1453 vr->io_req.br_callback = ata_ioreq_cb;
1455 vr->io_req.br_callback = atapi_ioreq_cb;
1456 vr->io_req.br_param = vr;
1457 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_list);
1462 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1464 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1465 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1466 struct ahci_port *p = &sc->port[port];
1468 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1469 port, offset, value);
1488 p->ie = value & 0xFDC000FF;
1489 ahci_generate_intr(sc);
1495 if (!(value & AHCI_P_CMD_ST)) {
1496 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
1502 p->cmd |= AHCI_P_CMD_CR;
1503 clb = (uint64_t)p->clbu << 32 | p->clb;
1504 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1505 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1508 if (value & AHCI_P_CMD_FRE) {
1511 p->cmd |= AHCI_P_CMD_FR;
1512 fb = (uint64_t)p->fbu << 32 | p->fb;
1513 /* we don't support FBSCP, so rfis size is 256Bytes */
1514 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1516 p->cmd &= ~AHCI_P_CMD_FR;
1519 if (value & AHCI_P_CMD_CLO) {
1521 p->cmd &= ~AHCI_P_CMD_CLO;
1524 ahci_handle_port(p);
1530 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1533 if (!(p->cmd & AHCI_P_CMD_ST)) {
1534 if (value & ATA_SC_DET_RESET)
1547 ahci_handle_port(p);
1557 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1559 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1567 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1570 if (value & AHCI_GHC_HR)
1572 else if (value & AHCI_GHC_IE) {
1573 sc->ghc |= AHCI_GHC_IE;
1574 ahci_generate_intr(sc);
1579 ahci_generate_intr(sc);
1587 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1588 int baridx, uint64_t offset, int size, uint64_t value)
1590 struct pci_ahci_softc *sc = pi->pi_arg;
1592 assert(baridx == 5);
1595 pthread_mutex_lock(&sc->mtx);
1597 if (offset < AHCI_OFFSET)
1598 pci_ahci_host_write(sc, offset, value);
1599 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1600 pci_ahci_port_write(sc, offset, value);
1602 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1604 pthread_mutex_unlock(&sc->mtx);
1608 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1624 uint32_t *p = &sc->cap;
1625 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1633 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1640 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1643 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1644 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1664 uint32_t *p= &sc->port[port].clb;
1665 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1674 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1675 port, offset, value);
1681 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1682 uint64_t offset, int size)
1684 struct pci_ahci_softc *sc = pi->pi_arg;
1687 assert(baridx == 5);
1690 pthread_mutex_lock(&sc->mtx);
1692 if (offset < AHCI_OFFSET)
1693 value = pci_ahci_host_read(sc, offset);
1694 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1695 value = pci_ahci_port_read(sc, offset);
1698 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
1701 pthread_mutex_unlock(&sc->mtx);
1707 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
1709 char bident[sizeof("XX:X:X")];
1710 struct blockif_ctxt *bctxt;
1711 struct pci_ahci_softc *sc;
1717 fprintf(stderr, "pci_ahci: backing device required\n");
1722 dbg = fopen("/tmp/log", "w+");
1725 sc = malloc(sizeof(struct pci_ahci_softc));
1726 memset(sc, 0, sizeof(struct pci_ahci_softc));
1729 sc->ports = MAX_PORTS;
1732 * Only use port 0 for a backing device. All other ports will be
1735 sc->port[0].atapi = atapi;
1738 * Attempt to open the backing image. Use the PCI
1739 * slot/func for the identifier string.
1741 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
1742 bctxt = blockif_open(opts, bident);
1743 if (bctxt == NULL) {
1747 sc->port[0].bctx = bctxt;
1748 sc->port[0].pr_sc = sc;
1751 * Allocate blockif request structures and add them
1754 pci_ahci_ioreq_init(&sc->port[0]);
1756 pthread_mutex_init(&sc->mtx, NULL);
1758 /* Intel ICH8 AHCI */
1759 slots = sc->port[0].ioqsz;
1763 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
1764 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
1765 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
1766 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
1767 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
1769 /* Only port 0 implemented */
1772 sc->cap2 = AHCI_CAP2_APST;
1775 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
1776 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
1777 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
1778 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
1779 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
1780 pci_emul_add_msicap(pi, 1);
1781 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
1782 AHCI_OFFSET + sc->ports * AHCI_STEP);
1786 blockif_close(sc->port[0].bctx);
1794 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1797 return (pci_ahci_init(ctx, pi, opts, 0));
1801 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1804 return (pci_ahci_init(ctx, pi, opts, 1));
1808 * Use separate emulation names to distinguish drive and atapi devices
1810 struct pci_devemu pci_de_ahci_hd = {
1811 .pe_emu = "ahci-hd",
1812 .pe_init = pci_ahci_hd_init,
1813 .pe_barwrite = pci_ahci_write,
1814 .pe_barread = pci_ahci_read
1816 PCI_EMUL_SET(pci_de_ahci_hd);
1818 struct pci_devemu pci_de_ahci_cd = {
1819 .pe_emu = "ahci-cd",
1820 .pe_init = pci_ahci_atapi_init,
1821 .pe_barwrite = pci_ahci_write,
1822 .pe_barread = pci_ahci_read
1824 PCI_EMUL_SET(pci_de_ahci_cd);