2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
51 #include <pthread_np.h>
59 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
61 #define PxSIG_ATA 0x00000101 /* ATA drive */
62 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
65 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
66 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
67 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
68 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
69 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
70 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
71 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
72 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
78 #define TEST_UNIT_READY 0x00
79 #define REQUEST_SENSE 0x03
81 #define START_STOP_UNIT 0x1B
82 #define PREVENT_ALLOW 0x1E
83 #define READ_CAPACITY 0x25
85 #define POSITION_TO_ELEMENT 0x2B
87 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
88 #define MODE_SENSE_10 0x5A
89 #define REPORT_LUNS 0xA0
94 * SCSI mode page codes
96 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
97 #define MODEPAGE_CD_CAPABILITIES 0x2A
102 #define ATA_SF_ENAB_SATA_SF 0x10
103 #define ATA_SATA_SF_AN 0x05
104 #define ATA_SF_DIS_SATA_SF 0x90
111 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
113 #define DPRINTF(format, arg...)
115 #define WPRINTF(format, arg...) printf(format, ##arg)
118 struct blockif_req io_req;
119 struct ahci_port *io_pr;
120 STAILQ_ENTRY(ahci_ioreq) io_flist;
121 TAILQ_ENTRY(ahci_ioreq) io_blist;
130 struct blockif_ctxt *bctx;
131 struct pci_ahci_softc *pr_sc;
138 uint8_t err_cfis[20];
164 struct ahci_ioreq *ioreq;
166 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
167 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
170 struct ahci_cmd_hdr {
175 uint32_t reserved[4];
178 struct ahci_prdt_entry {
181 #define DBCMASK 0x3fffff
185 struct pci_ahci_softc {
186 struct pci_devinst *asc_pi;
201 struct ahci_port port[MAX_PORTS];
203 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
205 static inline void lba_to_msf(uint8_t *buf, int lba)
208 buf[0] = (lba / 75) / 60;
209 buf[1] = (lba / 75) % 60;
214 * generate HBA intr depending on whether or not ports within
215 * the controller have an interrupt pending.
218 ahci_generate_intr(struct pci_ahci_softc *sc)
220 struct pci_devinst *pi;
225 for (i = 0; i < sc->ports; i++) {
226 struct ahci_port *pr;
232 DPRINTF("%s %x\n", __func__, sc->is);
234 if (sc->is && (sc->ghc & AHCI_GHC_IE)) {
235 if (pci_msi_enabled(pi)) {
237 * Generate an MSI interrupt on every edge
239 pci_generate_msi(pi, 0);
240 } else if (!sc->lintr) {
242 * Only generate a pin-based interrupt if one wasn't
246 pci_lintr_assert(pi);
248 } else if (sc->lintr) {
250 * No interrupts: deassert pin-based signal if it had
253 pci_lintr_deassert(pi);
259 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
261 int offset, len, irq;
263 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
267 case FIS_TYPE_REGD2H:
272 case FIS_TYPE_SETDEVBITS:
277 case FIS_TYPE_PIOSETUP:
283 WPRINTF("unsupported fis type %d\n", ft);
286 memcpy(p->rfis + offset, fis, len);
289 ahci_generate_intr(p->pr_sc);
294 ahci_write_fis_piosetup(struct ahci_port *p)
298 memset(fis, 0, sizeof(fis));
299 fis[0] = FIS_TYPE_PIOSETUP;
300 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
304 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
309 error = (tfd >> 8) & 0xff;
310 memset(fis, 0, sizeof(fis));
311 fis[0] = FIS_TYPE_SETDEVBITS;
315 if (fis[2] & ATA_S_ERROR) {
316 p->is |= AHCI_P_IX_TFE;
317 p->err_cfis[0] = slot;
318 p->err_cfis[2] = tfd & 0x77;
319 p->err_cfis[3] = error;
320 memcpy(&p->err_cfis[4], cfis + 4, 16);
322 *(uint32_t *)(fis + 4) = (1 << slot);
323 p->sact &= ~(1 << slot);
326 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
330 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
335 error = (tfd >> 8) & 0xff;
336 memset(fis, 0, sizeof(fis));
337 fis[0] = FIS_TYPE_REGD2H;
351 if (fis[2] & ATA_S_ERROR) {
352 p->is |= AHCI_P_IX_TFE;
353 p->err_cfis[0] = 0x80;
354 p->err_cfis[2] = tfd & 0xff;
355 p->err_cfis[3] = error;
356 memcpy(&p->err_cfis[4], cfis + 4, 16);
358 p->ci &= ~(1 << slot);
360 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
364 ahci_write_reset_fis_d2h(struct ahci_port *p)
368 memset(fis, 0, sizeof(fis));
369 fis[0] = FIS_TYPE_REGD2H;
377 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
381 ahci_check_stopped(struct ahci_port *p)
384 * If we are no longer processing the command list and nothing
385 * is in-flight, clear the running bit, the current command
386 * slot, the command issue and active bits.
388 if (!(p->cmd & AHCI_P_CMD_ST)) {
389 if (p->pending == 0) {
390 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
398 ahci_port_stop(struct ahci_port *p)
400 struct ahci_ioreq *aior;
406 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
408 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
410 * Try to cancel the outstanding blockif request.
412 error = blockif_cancel(p->bctx, &aior->io_req);
418 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
419 cfis[2] == ATA_READ_FPDMA_QUEUED)
423 p->sact &= ~(1 << slot);
425 p->ci &= ~(1 << slot);
428 * This command is now done.
430 p->pending &= ~(1 << slot);
433 * Delete the blockif request from the busy list
435 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
438 * Move the blockif request back to the free list
440 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
443 ahci_check_stopped(p);
447 ahci_port_reset(struct ahci_port *pr)
451 pr->xfermode = ATA_UDMA6;
452 pr->mult_sectors = 128;
455 pr->ssts = ATA_SS_DET_NO_DEVICE;
456 pr->sig = 0xFFFFFFFF;
460 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
461 if (pr->sctl & ATA_SC_SPD_MASK)
462 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
464 pr->ssts |= ATA_SS_SPD_GEN3;
465 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
468 pr->tfd |= ATA_S_READY;
470 pr->sig = PxSIG_ATAPI;
471 ahci_write_reset_fis_d2h(pr);
475 ahci_reset(struct pci_ahci_softc *sc)
479 sc->ghc = AHCI_GHC_AE;
483 pci_lintr_deassert(sc->asc_pi);
487 for (i = 0; i < sc->ports; i++) {
490 sc->port[i].sctl = 0;
491 ahci_port_reset(&sc->port[i]);
496 ata_string(uint8_t *dest, const char *src, int len)
500 for (i = 0; i < len; i++) {
502 dest[i ^ 1] = *src++;
509 atapi_string(uint8_t *dest, const char *src, int len)
513 for (i = 0; i < len; i++) {
522 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
525 struct ahci_ioreq *aior;
526 struct blockif_req *breq;
527 struct pci_ahci_softc *sc;
528 struct ahci_prdt_entry *prdt;
529 struct ahci_cmd_hdr *hdr;
532 int i, err, iovcnt, ncq, readop;
535 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
536 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
541 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
542 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
543 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
544 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
547 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
548 cfis[2] == ATA_READ_FPDMA_QUEUED) {
549 lba = ((uint64_t)cfis[10] << 40) |
550 ((uint64_t)cfis[9] << 32) |
551 ((uint64_t)cfis[8] << 24) |
552 ((uint64_t)cfis[6] << 16) |
553 ((uint64_t)cfis[5] << 8) |
555 len = cfis[11] << 8 | cfis[3];
559 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
560 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
561 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
562 lba = ((uint64_t)cfis[10] << 40) |
563 ((uint64_t)cfis[9] << 32) |
564 ((uint64_t)cfis[8] << 24) |
565 ((uint64_t)cfis[6] << 16) |
566 ((uint64_t)cfis[5] << 8) |
568 len = cfis[13] << 8 | cfis[12];
572 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
573 (cfis[5] << 8) | cfis[4];
578 lba *= blockif_sectsz(p->bctx);
579 len *= blockif_sectsz(p->bctx);
582 * Pull request off free list
584 aior = STAILQ_FIRST(&p->iofhd);
585 assert(aior != NULL);
586 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
591 breq = &aior->io_req;
592 breq->br_offset = lba + done;
593 iovcnt = hdr->prdtl - seek;
594 if (iovcnt > BLOCKIF_IOV_MAX) {
595 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
596 iovcnt = BLOCKIF_IOV_MAX;
599 breq->br_iovcnt = iovcnt;
602 * Mark this command in-flight.
604 p->pending |= 1 << slot;
607 * Stuff request onto busy list
609 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
612 * Build up the iovec based on the prdt
614 for (i = 0; i < iovcnt; i++) {
617 dbcsz = (prdt->dbc & DBCMASK) + 1;
618 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
620 breq->br_iov[i].iov_len = dbcsz;
625 err = blockif_read(p->bctx, breq);
627 err = blockif_write(p->bctx, breq);
631 p->ci &= ~(1 << slot);
635 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
637 struct ahci_ioreq *aior;
638 struct blockif_req *breq;
642 * Pull request off free list
644 aior = STAILQ_FIRST(&p->iofhd);
645 assert(aior != NULL);
646 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
652 breq = &aior->io_req;
655 * Mark this command in-flight.
657 p->pending |= 1 << slot;
660 * Stuff request onto busy list
662 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
664 err = blockif_flush(p->bctx, breq);
669 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
672 struct ahci_cmd_hdr *hdr;
673 struct ahci_prdt_entry *prdt;
677 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
680 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
681 for (i = 0; i < hdr->prdtl && len; i++) {
686 dbcsz = (prdt->dbc & DBCMASK) + 1;
687 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
688 sublen = len < dbcsz ? len : dbcsz;
689 memcpy(to, ptr, sublen);
697 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
699 struct ahci_ioreq *aior;
700 struct blockif_req *breq;
707 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
708 len = (uint16_t)cfis[13] << 8 | cfis[12];
710 } else { /* ATA_SEND_FPDMA_QUEUED */
711 len = (uint16_t)cfis[11] << 8 | cfis[3];
714 read_prdt(p, slot, cfis, buf, sizeof(buf));
718 elba = ((uint64_t)entry[5] << 40) |
719 ((uint64_t)entry[4] << 32) |
720 ((uint64_t)entry[3] << 24) |
721 ((uint64_t)entry[2] << 16) |
722 ((uint64_t)entry[1] << 8) |
724 elen = (uint16_t)entry[7] << 8 | entry[6];
728 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
729 p->pending &= ~(1 << slot);
730 ahci_check_stopped(p);
737 * Pull request off free list
739 aior = STAILQ_FIRST(&p->iofhd);
740 assert(aior != NULL);
741 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
748 breq = &aior->io_req;
749 breq->br_offset = elba * blockif_sectsz(p->bctx);
751 breq->br_iov[0].iov_len = elen * blockif_sectsz(p->bctx);
754 * Mark this command in-flight.
756 p->pending |= 1 << slot;
759 * Stuff request onto busy list
761 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
763 err = blockif_delete(p->bctx, breq);
768 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
771 struct ahci_cmd_hdr *hdr;
772 struct ahci_prdt_entry *prdt;
776 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
779 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
780 for (i = 0; i < hdr->prdtl && len; i++) {
785 dbcsz = (prdt->dbc & DBCMASK) + 1;
786 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
787 sublen = len < dbcsz ? len : dbcsz;
788 memcpy(ptr, from, sublen);
793 hdr->prdbc = size - len;
797 ahci_checksum(uint8_t *buf, int size)
802 for (i = 0; i < size - 1; i++)
804 buf[size - 1] = 0x100 - sum;
808 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
810 struct ahci_cmd_hdr *hdr;
813 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
814 if (p->atapi || hdr->prdtl == 0 || cfis[4] != 0x10 ||
815 cfis[5] != 0 || cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
816 ahci_write_fis_d2h(p, slot, cfis,
817 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
821 memset(buf, 0, sizeof(buf));
822 memcpy(buf, p->err_cfis, sizeof(p->err_cfis));
823 ahci_checksum(buf, sizeof(buf));
825 if (cfis[2] == ATA_READ_LOG_EXT)
826 ahci_write_fis_piosetup(p);
827 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
828 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
832 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
834 struct ahci_cmd_hdr *hdr;
836 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
837 if (p->atapi || hdr->prdtl == 0) {
838 ahci_write_fis_d2h(p, slot, cfis,
839 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
843 int sectsz, psectsz, psectoff, candelete;
847 candelete = blockif_candelete(p->bctx);
848 sectsz = blockif_sectsz(p->bctx);
849 sectors = blockif_size(p->bctx) / sectsz;
850 blockif_chs(p->bctx, &cyl, &heads, &sech);
851 blockif_psectsz(p->bctx, &psectsz, &psectoff);
852 memset(buf, 0, sizeof(buf));
857 /* TODO emulate different serial? */
858 ata_string((uint8_t *)(buf+10), "123456", 20);
859 ata_string((uint8_t *)(buf+23), "001", 8);
860 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
861 buf[47] = (0x8000 | 128);
863 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
865 buf[53] = (1 << 1 | 1 << 2);
867 buf[59] = (0x100 | p->mult_sectors);
868 if (sectors <= 0x0fffffff) {
870 buf[61] = (sectors >> 16);
876 if (p->xfermode & ATA_WDMA0)
877 buf[63] |= (1 << ((p->xfermode & 7) + 8));
885 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
887 buf[77] = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
888 (p->ssts & ATA_SS_SPD_MASK) >> 3);
891 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
892 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
893 buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
894 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
896 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
897 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
898 buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
899 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
902 if (p->xfermode & ATA_UDMA0)
903 buf[88] |= (1 << ((p->xfermode & 7) + 8));
904 buf[93] = (1 | 1 <<14);
906 buf[101] = (sectors >> 16);
907 buf[102] = (sectors >> 32);
908 buf[103] = (sectors >> 48);
910 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
912 buf[169] = ATA_SUPPORT_DSM_TRIM;
916 if (psectsz > sectsz) {
918 buf[106] |= ffsl(psectsz / sectsz) - 1;
919 buf[209] |= (psectoff / sectsz);
923 buf[117] = sectsz / 2;
924 buf[118] = ((sectsz / 2) >> 16);
926 buf[119] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
927 buf[120] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
930 ahci_checksum((uint8_t *)buf, sizeof(buf));
931 ahci_write_fis_piosetup(p);
932 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
933 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
938 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
941 ahci_write_fis_d2h(p, slot, cfis,
942 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
946 memset(buf, 0, sizeof(buf));
947 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
948 /* TODO emulate different serial? */
949 ata_string((uint8_t *)(buf+10), "123456", 20);
950 ata_string((uint8_t *)(buf+23), "001", 8);
951 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
952 buf[49] = (1 << 9 | 1 << 8);
953 buf[50] = (1 << 14 | 1);
954 buf[53] = (1 << 2 | 1 << 1);
957 if (p->xfermode & ATA_WDMA0)
958 buf[63] |= (1 << ((p->xfermode & 7) + 8));
964 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
965 buf[77] = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
968 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
969 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
972 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
973 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
976 if (p->xfermode & ATA_UDMA0)
977 buf[88] |= (1 << ((p->xfermode & 7) + 8));
980 ahci_checksum((uint8_t *)buf, sizeof(buf));
981 ahci_write_fis_piosetup(p);
982 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
983 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
988 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
997 if (acmd[1] & 1) { /* VPD */
998 if (acmd[2] == 0) { /* Supported VPD pages */
1006 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1008 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1009 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1010 ahci_write_fis_d2h(p, slot, cfis, tfd);
1022 atapi_string(buf + 8, "BHYVE", 8);
1023 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1024 atapi_string(buf + 32, "001", 4);
1030 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1031 write_prdt(p, slot, cfis, buf, len);
1032 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1036 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1041 sectors = blockif_size(p->bctx) / 2048;
1042 be32enc(buf, sectors - 1);
1043 be32enc(buf + 4, 2048);
1044 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1045 write_prdt(p, slot, cfis, buf, sizeof(buf));
1046 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1050 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1058 len = be16dec(acmd + 7);
1059 format = acmd[9] >> 6;
1065 uint8_t start_track, buf[20], *bp;
1067 msf = (acmd[1] >> 1) & 1;
1068 start_track = acmd[6];
1069 if (start_track > 1 && start_track != 0xaa) {
1071 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1073 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1074 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1075 ahci_write_fis_d2h(p, slot, cfis, tfd);
1081 if (start_track <= 1) {
1101 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1105 lba_to_msf(bp, sectors);
1108 be32enc(bp, sectors);
1112 be16enc(buf, size - 2);
1115 write_prdt(p, slot, cfis, buf, len);
1116 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1117 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1124 memset(buf, 0, sizeof(buf));
1128 if (len > sizeof(buf))
1130 write_prdt(p, slot, cfis, buf, len);
1131 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1132 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1139 uint8_t start_track, *bp, buf[50];
1141 msf = (acmd[1] >> 1) & 1;
1142 start_track = acmd[6];
1178 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1182 lba_to_msf(bp, sectors);
1185 be32enc(bp, sectors);
1208 be16enc(buf, size - 2);
1211 write_prdt(p, slot, cfis, buf, len);
1212 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1213 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1220 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1222 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1223 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1224 ahci_write_fis_d2h(p, slot, cfis, tfd);
1231 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1235 memset(buf, 0, sizeof(buf));
1238 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1239 write_prdt(p, slot, cfis, buf, sizeof(buf));
1240 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1244 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
1245 uint32_t done, int seek)
1247 struct ahci_ioreq *aior;
1248 struct ahci_cmd_hdr *hdr;
1249 struct ahci_prdt_entry *prdt;
1250 struct blockif_req *breq;
1251 struct pci_ahci_softc *sc;
1259 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1260 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1263 lba = be32dec(acmd + 2);
1264 if (acmd[0] == READ_10)
1265 len = be16dec(acmd + 7);
1267 len = be32dec(acmd + 6);
1269 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1270 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1276 * Pull request off free list
1278 aior = STAILQ_FIRST(&p->iofhd);
1279 assert(aior != NULL);
1280 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1285 breq = &aior->io_req;
1286 breq->br_offset = lba + done;
1287 iovcnt = hdr->prdtl - seek;
1288 if (iovcnt > BLOCKIF_IOV_MAX) {
1289 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
1290 iovcnt = BLOCKIF_IOV_MAX;
1293 breq->br_iovcnt = iovcnt;
1296 * Mark this command in-flight.
1298 p->pending |= 1 << slot;
1301 * Stuff request onto busy list
1303 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1306 * Build up the iovec based on the prdt
1308 for (i = 0; i < iovcnt; i++) {
1311 dbcsz = (prdt->dbc & DBCMASK) + 1;
1312 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
1314 breq->br_iov[i].iov_len = dbcsz;
1315 aior->done += dbcsz;
1318 err = blockif_read(p->bctx, breq);
1323 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1331 if (len > sizeof(buf))
1333 memset(buf, 0, len);
1334 buf[0] = 0x70 | (1 << 7);
1335 buf[2] = p->sense_key;
1338 write_prdt(p, slot, cfis, buf, len);
1339 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1340 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1344 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1346 uint8_t *acmd = cfis + 0x40;
1349 switch (acmd[4] & 3) {
1353 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1354 tfd = ATA_S_READY | ATA_S_DSC;
1357 /* TODO eject media */
1358 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1359 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1361 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1364 ahci_write_fis_d2h(p, slot, cfis, tfd);
1368 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1376 len = be16dec(acmd + 7);
1378 code = acmd[2] & 0x3f;
1383 case MODEPAGE_RW_ERROR_RECOVERY:
1387 if (len > sizeof(buf))
1390 memset(buf, 0, sizeof(buf));
1391 be16enc(buf, 16 - 2);
1396 write_prdt(p, slot, cfis, buf, len);
1397 tfd = ATA_S_READY | ATA_S_DSC;
1400 case MODEPAGE_CD_CAPABILITIES:
1404 if (len > sizeof(buf))
1407 memset(buf, 0, sizeof(buf));
1408 be16enc(buf, 30 - 2);
1414 be16enc(&buf[18], 2);
1415 be16enc(&buf[20], 512);
1416 write_prdt(p, slot, cfis, buf, len);
1417 tfd = ATA_S_READY | ATA_S_DSC;
1426 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1428 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1433 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1435 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1438 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1439 ahci_write_fis_d2h(p, slot, cfis, tfd);
1443 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1451 /* we don't support asynchronous operation */
1452 if (!(acmd[1] & 1)) {
1453 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1455 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1460 len = be16dec(acmd + 7);
1461 if (len > sizeof(buf))
1464 memset(buf, 0, sizeof(buf));
1465 be16enc(buf, 8 - 2);
1469 write_prdt(p, slot, cfis, buf, len);
1470 tfd = ATA_S_READY | ATA_S_DSC;
1472 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1473 ahci_write_fis_d2h(p, slot, cfis, tfd);
1477 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1487 for (i = 0; i < 16; i++)
1488 DPRINTF("%02x ", acmd[i]);
1494 case TEST_UNIT_READY:
1495 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1496 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1499 atapi_inquiry(p, slot, cfis);
1502 atapi_read_capacity(p, slot, cfis);
1506 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1507 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1510 atapi_read_toc(p, slot, cfis);
1513 atapi_report_luns(p, slot, cfis);
1517 atapi_read(p, slot, cfis, 0, 0);
1520 atapi_request_sense(p, slot, cfis);
1522 case START_STOP_UNIT:
1523 atapi_start_stop_unit(p, slot, cfis);
1526 atapi_mode_sense(p, slot, cfis);
1528 case GET_EVENT_STATUS_NOTIFICATION:
1529 atapi_get_event_status_notification(p, slot, cfis);
1532 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1533 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1535 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1536 ATA_S_READY | ATA_S_ERROR);
1542 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1546 case ATA_ATA_IDENTIFY:
1547 handle_identify(p, slot, cfis);
1549 case ATA_SETFEATURES:
1552 case ATA_SF_ENAB_SATA_SF:
1554 case ATA_SATA_SF_AN:
1555 p->tfd = ATA_S_DSC | ATA_S_READY;
1558 p->tfd = ATA_S_ERROR | ATA_S_READY;
1559 p->tfd |= (ATA_ERROR_ABORT << 8);
1563 case ATA_SF_ENAB_WCACHE:
1564 case ATA_SF_DIS_WCACHE:
1565 case ATA_SF_ENAB_RCACHE:
1566 case ATA_SF_DIS_RCACHE:
1567 p->tfd = ATA_S_DSC | ATA_S_READY;
1569 case ATA_SF_SETXFER:
1571 switch (cfis[12] & 0xf8) {
1577 p->xfermode = (cfis[12] & 0x7);
1580 p->tfd = ATA_S_DSC | ATA_S_READY;
1584 p->tfd = ATA_S_ERROR | ATA_S_READY;
1585 p->tfd |= (ATA_ERROR_ABORT << 8);
1588 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1592 if (cfis[12] != 0 &&
1593 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1594 p->tfd = ATA_S_ERROR | ATA_S_READY;
1595 p->tfd |= (ATA_ERROR_ABORT << 8);
1597 p->mult_sectors = cfis[12];
1598 p->tfd = ATA_S_DSC | ATA_S_READY;
1600 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1608 case ATA_READ_MUL48:
1609 case ATA_WRITE_MUL48:
1612 case ATA_READ_DMA48:
1613 case ATA_WRITE_DMA48:
1614 case ATA_READ_FPDMA_QUEUED:
1615 case ATA_WRITE_FPDMA_QUEUED:
1616 ahci_handle_dma(p, slot, cfis, 0, 0);
1618 case ATA_FLUSHCACHE:
1619 case ATA_FLUSHCACHE48:
1620 ahci_handle_flush(p, slot, cfis);
1622 case ATA_DATA_SET_MANAGEMENT:
1623 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1624 cfis[13] == 0 && cfis[12] == 1) {
1625 ahci_handle_dsm_trim(p, slot, cfis, 0);
1628 ahci_write_fis_d2h(p, slot, cfis,
1629 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1631 case ATA_SEND_FPDMA_QUEUED:
1632 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1633 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1634 cfis[11] == 0 && cfis[13] == 1) {
1635 ahci_handle_dsm_trim(p, slot, cfis, 0);
1638 ahci_write_fis_d2h(p, slot, cfis,
1639 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1641 case ATA_READ_LOG_EXT:
1642 case ATA_READ_LOG_DMA_EXT:
1643 ahci_handle_read_log(p, slot, cfis);
1646 ahci_write_fis_d2h(p, slot, cfis,
1647 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1649 case ATA_STANDBY_CMD:
1650 case ATA_STANDBY_IMMEDIATE:
1652 case ATA_IDLE_IMMEDIATE:
1654 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1656 case ATA_ATAPI_IDENTIFY:
1657 handle_atapi_identify(p, slot, cfis);
1659 case ATA_PACKET_CMD:
1661 ahci_write_fis_d2h(p, slot, cfis,
1662 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1664 handle_packet_cmd(p, slot, cfis);
1667 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1668 ahci_write_fis_d2h(p, slot, cfis,
1669 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1675 ahci_handle_slot(struct ahci_port *p, int slot)
1677 struct ahci_cmd_hdr *hdr;
1678 struct ahci_prdt_entry *prdt;
1679 struct pci_ahci_softc *sc;
1684 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1685 cfl = (hdr->flags & 0x1f) * 4;
1686 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1687 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1688 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1692 for (i = 0; i < cfl; i++) {
1695 DPRINTF("%02x ", cfis[i]);
1699 for (i = 0; i < hdr->prdtl; i++) {
1700 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1705 if (cfis[0] != FIS_TYPE_REGH2D) {
1706 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1710 if (cfis[1] & 0x80) {
1711 ahci_handle_cmd(p, slot, cfis);
1713 if (cfis[15] & (1 << 2))
1715 else if (p->reset) {
1719 p->ci &= ~(1 << slot);
1724 ahci_handle_port(struct ahci_port *p)
1728 if (!(p->cmd & AHCI_P_CMD_ST))
1732 * Search for any new commands to issue ignoring those that
1733 * are already in-flight.
1735 for (i = 0; (i < 32) && p->ci; i++) {
1736 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) {
1737 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1738 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT;
1739 ahci_handle_slot(p, i);
1745 * blockif callback routine - this runs in the context of the blockif
1746 * i/o thread, so the mutex needs to be acquired.
1749 ata_ioreq_cb(struct blockif_req *br, int err)
1751 struct ahci_cmd_hdr *hdr;
1752 struct ahci_ioreq *aior;
1753 struct ahci_port *p;
1754 struct pci_ahci_softc *sc;
1757 int pending, slot, ncq, dsm;
1759 DPRINTF("%s %d\n", __func__, err);
1762 aior = br->br_param;
1766 pending = aior->prdtl;
1768 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1770 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1771 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1772 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1774 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1775 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1776 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1779 pthread_mutex_lock(&sc->mtx);
1782 * Delete the blockif request from the busy list
1784 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1787 * Move the blockif request back to the free list
1789 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1792 hdr->prdbc = aior->done;
1795 if (aior->done != aior->len && !err) {
1796 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1800 if (pending && !err) {
1801 ahci_handle_dma(p, slot, cfis, aior->done,
1802 hdr->prdtl - pending);
1807 if (!err && aior->done == aior->len) {
1808 tfd = ATA_S_READY | ATA_S_DSC;
1810 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1814 ahci_write_fis_sdb(p, slot, cfis, tfd);
1816 ahci_write_fis_d2h(p, slot, cfis, tfd);
1819 * This command is now complete.
1821 p->pending &= ~(1 << slot);
1823 ahci_check_stopped(p);
1825 pthread_mutex_unlock(&sc->mtx);
1826 DPRINTF("%s exit\n", __func__);
1830 atapi_ioreq_cb(struct blockif_req *br, int err)
1832 struct ahci_cmd_hdr *hdr;
1833 struct ahci_ioreq *aior;
1834 struct ahci_port *p;
1835 struct pci_ahci_softc *sc;
1840 DPRINTF("%s %d\n", __func__, err);
1842 aior = br->br_param;
1846 pending = aior->prdtl;
1848 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1850 pthread_mutex_lock(&sc->mtx);
1853 * Delete the blockif request from the busy list
1855 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1858 * Move the blockif request back to the free list
1860 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1863 hdr->prdbc = aior->done;
1865 if (pending && !err) {
1866 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1870 if (!err && aior->done == aior->len) {
1871 tfd = ATA_S_READY | ATA_S_DSC;
1873 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1875 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1878 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1879 ahci_write_fis_d2h(p, slot, cfis, tfd);
1882 * This command is now complete.
1884 p->pending &= ~(1 << slot);
1886 ahci_check_stopped(p);
1888 pthread_mutex_unlock(&sc->mtx);
1889 DPRINTF("%s exit\n", __func__);
1893 pci_ahci_ioreq_init(struct ahci_port *pr)
1895 struct ahci_ioreq *vr;
1898 pr->ioqsz = blockif_queuesz(pr->bctx);
1899 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1900 STAILQ_INIT(&pr->iofhd);
1903 * Add all i/o request entries to the free queue
1905 for (i = 0; i < pr->ioqsz; i++) {
1909 vr->io_req.br_callback = ata_ioreq_cb;
1911 vr->io_req.br_callback = atapi_ioreq_cb;
1912 vr->io_req.br_param = vr;
1913 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
1916 TAILQ_INIT(&pr->iobhd);
1920 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1922 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1923 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1924 struct ahci_port *p = &sc->port[port];
1926 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1927 port, offset, value);
1946 p->ie = value & 0xFDC000FF;
1947 ahci_generate_intr(sc);
1953 if (!(value & AHCI_P_CMD_ST)) {
1958 p->cmd |= AHCI_P_CMD_CR;
1959 clb = (uint64_t)p->clbu << 32 | p->clb;
1960 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1961 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1964 if (value & AHCI_P_CMD_FRE) {
1967 p->cmd |= AHCI_P_CMD_FR;
1968 fb = (uint64_t)p->fbu << 32 | p->fb;
1969 /* we don't support FBSCP, so rfis size is 256Bytes */
1970 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1972 p->cmd &= ~AHCI_P_CMD_FR;
1975 if (value & AHCI_P_CMD_CLO) {
1977 p->cmd &= ~AHCI_P_CMD_CLO;
1980 ahci_handle_port(p);
1986 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1990 if (!(p->cmd & AHCI_P_CMD_ST)) {
1991 if (value & ATA_SC_DET_RESET)
2003 ahci_handle_port(p);
2013 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2015 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
2023 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
2026 if (value & AHCI_GHC_HR)
2028 else if (value & AHCI_GHC_IE) {
2029 sc->ghc |= AHCI_GHC_IE;
2030 ahci_generate_intr(sc);
2035 ahci_generate_intr(sc);
2043 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
2044 int baridx, uint64_t offset, int size, uint64_t value)
2046 struct pci_ahci_softc *sc = pi->pi_arg;
2048 assert(baridx == 5);
2051 pthread_mutex_lock(&sc->mtx);
2053 if (offset < AHCI_OFFSET)
2054 pci_ahci_host_write(sc, offset, value);
2055 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2056 pci_ahci_port_write(sc, offset, value);
2058 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
2060 pthread_mutex_unlock(&sc->mtx);
2064 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2080 uint32_t *p = &sc->cap;
2081 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2089 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
2096 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2099 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2100 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2120 uint32_t *p= &sc->port[port].clb;
2121 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2130 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
2131 port, offset, value);
2137 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2138 uint64_t offset, int size)
2140 struct pci_ahci_softc *sc = pi->pi_arg;
2143 assert(baridx == 5);
2146 pthread_mutex_lock(&sc->mtx);
2148 if (offset < AHCI_OFFSET)
2149 value = pci_ahci_host_read(sc, offset);
2150 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2151 value = pci_ahci_port_read(sc, offset);
2154 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
2157 pthread_mutex_unlock(&sc->mtx);
2163 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2165 char bident[sizeof("XX:X:X")];
2166 struct blockif_ctxt *bctxt;
2167 struct pci_ahci_softc *sc;
2173 fprintf(stderr, "pci_ahci: backing device required\n");
2178 dbg = fopen("/tmp/log", "w+");
2181 sc = calloc(1, sizeof(struct pci_ahci_softc));
2184 sc->ports = MAX_PORTS;
2187 * Only use port 0 for a backing device. All other ports will be
2190 sc->port[0].atapi = atapi;
2193 * Attempt to open the backing image. Use the PCI
2194 * slot/func for the identifier string.
2196 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
2197 bctxt = blockif_open(opts, bident);
2198 if (bctxt == NULL) {
2202 sc->port[0].bctx = bctxt;
2203 sc->port[0].pr_sc = sc;
2206 * Allocate blockif request structures and add them
2209 pci_ahci_ioreq_init(&sc->port[0]);
2211 pthread_mutex_init(&sc->mtx, NULL);
2213 /* Intel ICH8 AHCI */
2214 slots = sc->port[0].ioqsz;
2218 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2219 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2220 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2221 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2222 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2224 /* Only port 0 implemented */
2227 sc->cap2 = AHCI_CAP2_APST;
2230 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2231 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2232 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2233 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2234 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2235 pci_emul_add_msicap(pi, 1);
2236 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2237 AHCI_OFFSET + sc->ports * AHCI_STEP);
2239 pci_lintr_request(pi);
2243 if (sc->port[0].bctx != NULL)
2244 blockif_close(sc->port[0].bctx);
2252 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2255 return (pci_ahci_init(ctx, pi, opts, 0));
2259 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2262 return (pci_ahci_init(ctx, pi, opts, 1));
2266 * Use separate emulation names to distinguish drive and atapi devices
2268 struct pci_devemu pci_de_ahci_hd = {
2269 .pe_emu = "ahci-hd",
2270 .pe_init = pci_ahci_hd_init,
2271 .pe_barwrite = pci_ahci_write,
2272 .pe_barread = pci_ahci_read
2274 PCI_EMUL_SET(pci_de_ahci_hd);
2276 struct pci_devemu pci_de_ahci_cd = {
2277 .pe_emu = "ahci-cd",
2278 .pe_init = pci_ahci_atapi_init,
2279 .pe_barwrite = pci_ahci_write,
2280 .pe_barread = pci_ahci_read
2282 PCI_EMUL_SET(pci_de_ahci_cd);